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From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <maxims@google.com>, <sjg@chromium.org>,
	<u-boot@lists.denx.de>
Cc: <ryan_chen@aspeedtech.com>, <joel@jms.id.au>
Subject: [PATCH v2 11/14] ast2600: spl: Locate load buffer in DRAM space
Date: Fri, 16 Jul 2021 13:55:43 +0800	[thread overview]
Message-ID: <20210716055546.1619-12-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20210716055546.1619-1-chiawei_wang@aspeedtech.com>

Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for
spl_get_load_buffer() to allow generic SPL image loading
code (e.g. FIT and Ymodem) to store data in DRAM.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
 arch/arm/mach-aspeed/ast2600/spl.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c
index 2172bb4ae7..42ef24316e 100644
--- a/arch/arm/mach-aspeed/ast2600/spl.c
+++ b/arch/arm/mach-aspeed/ast2600/spl.c
@@ -28,14 +28,7 @@ u32 spl_boot_device(void)
 
 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
 {
-	/*
-	 * When boot from SPI, AST2600 already remap 0x00000000 ~ 0x0fffffff
-	 * to BMC SPI memory space 0x20000000 ~ 0x2fffffff. The next stage BL
-	 * has been located in SPI for XIP. In this case, the load buffer for
-	 * SPL image loading will be set to the remapped address of the next
-	 * BL instead of the DRAM space CONFIG_SYS_LOAD_ADDR
-	 */
-	return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+	return (struct image_header *)(CONFIG_SYS_LOAD_ADDR);
 }
 
 #ifdef CONFIG_SPL_BOARD_INIT
-- 
2.17.1


  parent reply	other threads:[~2021-07-16  5:58 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-16  5:55 [PATCH v2 00/14] aspeed: Support secure boot chain with FIT image verification Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 01/14] aspeed: ast2600: Enlarge SRAM size Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 02/14] clk: ast2600: Add YCLK control for HACE Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 03/14] crypto: aspeed: Add AST2600 HACE support Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 04/14] ast2600: spl: Add HACE probing Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 05/14] ARM: dts: ast2600: Add HACE to device tree Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 06/14] common: fit: Use hash.c to call CRC/SHA function Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 07/14] clk: ast2600: Add RSACLK control for ARCY Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 08/14] crypto: aspeed: Add AST2600 ARCY support Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 09/14] ast2600: spl: Add ARCY probing Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 10/14] ARM: dts: ast2600: Add ARCY to device tree Chia-Wei Wang
2021-07-16  5:55 ` Chia-Wei Wang [this message]
2021-07-16  5:55 ` [PATCH v2 12/14] configs: ast2600-evb: Enable SPL FIT support Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 13/14] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific Chia-Wei Wang
2021-07-16  5:55 ` [PATCH v2 14/14] configs: ast2600: Boot kernel FIT in DRAM Chia-Wei Wang

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