[Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

[Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

[Fabrice Fontaine]

Fix the following build failure on riscv32:

system/base/target.scm:132:16: In procedure triplet-pointer-size:
unknown CPU word size "riscv32"

Fixes:
 - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8

Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
---
 ...stem-base-target.scm-support-riscv32.patch | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 package/guile/0004-module-system-base-target.scm-support-riscv32.patch

diff --git a/package/guile/0004-module-system-base-target.scm-support-riscv32.patch b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
new file mode 100644
index 0000000000..cadd040f12
--- /dev/null
+++ b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
@@ -0,0 +1,33 @@
+From 995a5e1da735b75733f059615c593c330b534d80 Mon Sep 17 00:00:00 2001
+From: Fabrice Fontaine <fontaine.fabrice@gmail.com>
+Date: Fri, 6 Aug 2021 19:49:37 +0200
+Subject: [PATCH] module/system/base/target.scm: support riscv32
+
+Fix the following build failure on riscv32:
+
+system/base/target.scm:132:16: In procedure triplet-pointer-size:
+unknown CPU word size "riscv32"
+
+Fixes:
+ - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
+
+Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
+---
+ module/system/base/target.scm | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/module/system/base/target.scm b/module/system/base/target.scm
+index 2088cd866..5544e234f 100644
+--- a/module/system/base/target.scm
++++ b/module/system/base/target.scm
+@@ -121,6 +121,7 @@
+           ((member cpu '("sparc" "powerpc" "mips" "mipsel" "nios2" "m68k" "sh3" "sh4")) 4)
+           ((member cpu '("s390x" "alpha")) 8)
+           ((string-match "^arm.*" cpu) 4)
++          ((string-match "^riscv.*" cpu) 8)
+           (else (error "unknown CPU word size" cpu)))))
+ 
+ (define (triplet-cpu t)
+-- 
+2.30.2
+
-- 
2.30.2

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Re: [Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

[Yann E. MORIN]

Fabrice, All,

On 2021-08-06 20:44 +0200, Fabrice Fontaine spake thusly:
> Fix the following build failure on riscv32:
> 
> system/base/target.scm:132:16: In procedure triplet-pointer-size:
> unknown CPU word size "riscv32"
> 
> Fixes:
>  - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> 
> Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> ---
>  ...stem-base-target.scm-support-riscv32.patch | 33 +++++++++++++++++++
>  1 file changed, 33 insertions(+)
>  create mode 100644 package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> 
> diff --git a/package/guile/0004-module-system-base-target.scm-support-riscv32.patch b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> new file mode 100644
> index 0000000000..cadd040f12
> --- /dev/null
> +++ b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> @@ -0,0 +1,33 @@
> +From 995a5e1da735b75733f059615c593c330b534d80 Mon Sep 17 00:00:00 2001
> +From: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> +Date: Fri, 6 Aug 2021 19:49:37 +0200
> +Subject: [PATCH] module/system/base/target.scm: support riscv32
> +
> +Fix the following build failure on riscv32:
> +
> +system/base/target.scm:132:16: In procedure triplet-pointer-size:
> +unknown CPU word size "riscv32"
> +
> +Fixes:
> + - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> +
> +Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> +---
> + module/system/base/target.scm | 1 +
> + 1 file changed, 1 insertion(+)
> +
> +diff --git a/module/system/base/target.scm b/module/system/base/target.scm
> +index 2088cd866..5544e234f 100644
> +--- a/module/system/base/target.scm
> ++++ b/module/system/base/target.scm
> +@@ -121,6 +121,7 @@
> +           ((member cpu '("sparc" "powerpc" "mips" "mipsel" "nios2" "m68k" "sh3" "sh4")) 4)
> +           ((member cpu '("s390x" "alpha")) 8)
> +           ((string-match "^arm.*" cpu) 4)
> ++          ((string-match "^riscv.*" cpu) 8)

Are you sure that a 32-bit CPU will have 8-byte wide words? I would
have naturrally expected them to be just 4-byte wide...

If htis is indeed the case, then please explain that in the patch commit
log...

Regards,
Yann E. MORIN.

> +           (else (error "unknown CPU word size" cpu)))))
> + 
> + (define (triplet-cpu t)
> +-- 
> +2.30.2
> +
> -- 
> 2.30.2
> 
> _______________________________________________
> buildroot mailing list
> buildroot@busybox.net
> http://lists.busybox.net/mailman/listinfo/buildroot

-- 
.-----------------.--------------------.------------------.--------------------.
|  Yann E. MORIN  | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
| +33 662 376 056 | Software  Designer | \ / CAMPAIGN     |  ___               |
| +33 561 099 427 `------------.-------:  X  AGAINST      |  \e/  There is no  |
| http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL    |   v   conspiracy.  |
'------------------------------^-------^------------------^--------------------'
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Re: [Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

[Fabrice Fontaine]

Yann,

Le sam. 7 août 2021 à 10:53, Yann E. MORIN <yann.morin.1998@free.fr> a écrit :
>
> Fabrice, All,
>
> On 2021-08-06 20:44 +0200, Fabrice Fontaine spake thusly:
> > Fix the following build failure on riscv32:
> >
> > system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > unknown CPU word size "riscv32"
> >
> > Fixes:
> >  - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> >
> > Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> > ---
> >  ...stem-base-target.scm-support-riscv32.patch | 33 +++++++++++++++++++
> >  1 file changed, 33 insertions(+)
> >  create mode 100644 package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> >
> > diff --git a/package/guile/0004-module-system-base-target.scm-support-riscv32.patch b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> > new file mode 100644
> > index 0000000000..cadd040f12
> > --- /dev/null
> > +++ b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> > @@ -0,0 +1,33 @@
> > +From 995a5e1da735b75733f059615c593c330b534d80 Mon Sep 17 00:00:00 2001
> > +From: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> > +Date: Fri, 6 Aug 2021 19:49:37 +0200
> > +Subject: [PATCH] module/system/base/target.scm: support riscv32
> > +
> > +Fix the following build failure on riscv32:
> > +
> > +system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > +unknown CPU word size "riscv32"
> > +
> > +Fixes:
> > + - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> > +
> > +Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> > +---
> > + module/system/base/target.scm | 1 +
> > + 1 file changed, 1 insertion(+)
> > +
> > +diff --git a/module/system/base/target.scm b/module/system/base/target.scm
> > +index 2088cd866..5544e234f 100644
> > +--- a/module/system/base/target.scm
> > ++++ b/module/system/base/target.scm
> > +@@ -121,6 +121,7 @@
> > +           ((member cpu '("sparc" "powerpc" "mips" "mipsel" "nios2" "m68k" "sh3" "sh4")) 4)
> > +           ((member cpu '("s390x" "alpha")) 8)
> > +           ((string-match "^arm.*" cpu) 4)
> > ++          ((string-match "^riscv.*" cpu) 8)
>
> Are you sure that a 32-bit CPU will have 8-byte wide words? I would
> have naturrally expected them to be just 4-byte wide...
As I'm not an expert in riscv, I searched on wikipedia and here is an
extract of https://en.wikipedia.org/wiki/RISC-V:
"Memory is addressed as 8-bit bytes, with words being in little-endian order"
It would be great if a riscv expert could confirm or not this information.
>
> If htis is indeed the case, then please explain that in the patch commit
> log...
>
> Regards,
> Yann E. MORIN.
>
> > +           (else (error "unknown CPU word size" cpu)))))
> > +
> > + (define (triplet-cpu t)
> > +--
> > +2.30.2
> > +
> > --
> > 2.30.2
> >
> > _______________________________________________
> > buildroot mailing list
> > buildroot@busybox.net
> > http://lists.busybox.net/mailman/listinfo/buildroot
>
> --
> .-----------------.--------------------.------------------.--------------------.
> |  Yann E. MORIN  | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
> | +33 662 376 056 | Software  Designer | \ / CAMPAIGN     |  ___               |
> | +33 561 099 427 `------------.-------:  X  AGAINST      |  \e/  There is no  |
> | http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL    |   v   conspiracy.  |
> '------------------------------^-------^------------------^--------------------'
Best Regards,

Fabrice
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Re: [Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

[Yann E. MORIN]

Fabrice, All,

On 2021-08-07 17:08 +0200, Fabrice Fontaine spake thusly:
> Le sam. 7 août 2021 à 10:53, Yann E. MORIN <yann.morin.1998@free.fr> a écrit :
> > On 2021-08-06 20:44 +0200, Fabrice Fontaine spake thusly:
> > > Fix the following build failure on riscv32:
> > > system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > > unknown CPU word size "riscv32"
[--SNIP--]
> > > ++          ((string-match "^riscv.*" cpu) 8)
> > Are you sure that a 32-bit CPU will have 8-byte wide words? I would
> > have naturrally expected them to be just 4-byte wide...
> As I'm not an expert in riscv, I searched on wikipedia and here is an
> extract of https://en.wikipedia.org/wiki/RISC-V:
> "Memory is addressed as 8-bit bytes, with words being in little-endian order"
> It would be great if a riscv expert could confirm or not this information.

So, yes. Re-read that carefully:

  - 8-bit bytes. I.e. a byte is 8 bits

  - words being in little-endian order

That indeed says nothing about word size in bytes (not in bits!).

I might be wrong, but on a 32-bit arch, words are always 4-bytes wides,
i.e. 32 bits, while on a 64-bit architecutre, words are 8-byte wide,
i.e. 64 bits.

So, I would wager that riscv32 has 4-byte wide, ie 32-bit wide, words.

Regards,
Yann E. MORIN.

> > If htis is indeed the case, then please explain that in the patch commit
> > log...
> >
> > Regards,
> > Yann E. MORIN.
> >
> > > +           (else (error "unknown CPU word size" cpu)))))
> > > +
> > > + (define (triplet-cpu t)
> > > +--
> > > +2.30.2
> > > +
> > > --
> > > 2.30.2
> > >
> > > _______________________________________________
> > > buildroot mailing list
> > > buildroot@busybox.net
> > > http://lists.busybox.net/mailman/listinfo/buildroot
> >
> > --
> > .-----------------.--------------------.------------------.--------------------.
> > |  Yann E. MORIN  | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
> > | +33 662 376 056 | Software  Designer | \ / CAMPAIGN     |  ___               |
> > | +33 561 099 427 `------------.-------:  X  AGAINST      |  \e/  There is no  |
> > | http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL    |   v   conspiracy.  |
> > '------------------------------^-------^------------------^--------------------'
> Best Regards,
> 
> Fabrice

-- 
.-----------------.--------------------.------------------.--------------------.
|  Yann E. MORIN  | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
| +33 662 376 056 | Software  Designer | \ / CAMPAIGN     |  ___               |
| +33 561 099 427 `------------.-------:  X  AGAINST      |  \e/  There is no  |
| http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL    |   v   conspiracy.  |
'------------------------------^-------^------------------^--------------------'
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Re: [Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

[Fabrice Fontaine]

Yann,

Le sam. 7 août 2021 à 19:12, Yann E. MORIN <yann.morin.1998@free.fr> a écrit :
>
> Fabrice, All,
>
> On 2021-08-07 17:08 +0200, Fabrice Fontaine spake thusly:
> > Le sam. 7 août 2021 à 10:53, Yann E. MORIN <yann.morin.1998@free.fr> a écrit :
> > > On 2021-08-06 20:44 +0200, Fabrice Fontaine spake thusly:
> > > > Fix the following build failure on riscv32:
> > > > system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > > > unknown CPU word size "riscv32"
> [--SNIP--]
> > > > ++          ((string-match "^riscv.*" cpu) 8)
> > > Are you sure that a 32-bit CPU will have 8-byte wide words? I would
> > > have naturrally expected them to be just 4-byte wide...
> > As I'm not an expert in riscv, I searched on wikipedia and here is an
> > extract of https://en.wikipedia.org/wiki/RISC-V:
> > "Memory is addressed as 8-bit bytes, with words being in little-endian order"
> > It would be great if a riscv expert could confirm or not this information.
>
> So, yes. Re-read that carefully:
>
>   - 8-bit bytes. I.e. a byte is 8 bits
>
>   - words being in little-endian order
>
> That indeed says nothing about word size in bytes (not in bits!).
>
> I might be wrong, but on a 32-bit arch, words are always 4-bytes wides,
> i.e. 32 bits, while on a 64-bit architecutre, words are 8-byte wide,
> i.e. 64 bits.
>
> So, I would wager that riscv32 has 4-byte wide, ie 32-bit wide, words.
Thanks for spotting my mistake, I'll resend a v2.
>
> Regards,
> Yann E. MORIN.
>
> > > If htis is indeed the case, then please explain that in the patch commit
> > > log...
> > >
> > > Regards,
> > > Yann E. MORIN.
> > >
> > > > +           (else (error "unknown CPU word size" cpu)))))
> > > > +
> > > > + (define (triplet-cpu t)
> > > > +--
> > > > +2.30.2
> > > > +
> > > > --
> > > > 2.30.2
> > > >
> > > > _______________________________________________
> > > > buildroot mailing list
> > > > buildroot@busybox.net
> > > > http://lists.busybox.net/mailman/listinfo/buildroot
> > >
> > > --
> > > .-----------------.--------------------.------------------.--------------------.
> > > |  Yann E. MORIN  | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
> > > | +33 662 376 056 | Software  Designer | \ / CAMPAIGN     |  ___               |
> > > | +33 561 099 427 `------------.-------:  X  AGAINST      |  \e/  There is no  |
> > > | http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL    |   v   conspiracy.  |
> > > '------------------------------^-------^------------------^--------------------'
> > Best Regards,
> >
> > Fabrice
>
> --
> .-----------------.--------------------.------------------.--------------------.
> |  Yann E. MORIN  | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
> | +33 662 376 056 | Software  Designer | \ / CAMPAIGN     |  ___               |
> | +33 561 099 427 `------------.-------:  X  AGAINST      |  \e/  There is no  |
> | http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL    |   v   conspiracy.  |
> '------------------------------^-------^------------------^--------------------'
Best Regards,

Fabrice
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Re: [Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

[Alistair Francis]

On Sat, Aug 7, 2021 at 6:53 PM Yann E. MORIN <yann.morin.1998@free.fr> wrote:
>
> Fabrice, All,
>
> On 2021-08-06 20:44 +0200, Fabrice Fontaine spake thusly:
> > Fix the following build failure on riscv32:
> >
> > system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > unknown CPU word size "riscv32"
> >
> > Fixes:
> >  - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> >
> > Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> > ---
> >  ...stem-base-target.scm-support-riscv32.patch | 33 +++++++++++++++++++
> >  1 file changed, 33 insertions(+)
> >  create mode 100644 package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> >
> > diff --git a/package/guile/0004-module-system-base-target.scm-support-riscv32.patch b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> > new file mode 100644
> > index 0000000000..cadd040f12
> > --- /dev/null
> > +++ b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> > @@ -0,0 +1,33 @@
> > +From 995a5e1da735b75733f059615c593c330b534d80 Mon Sep 17 00:00:00 2001
> > +From: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> > +Date: Fri, 6 Aug 2021 19:49:37 +0200
> > +Subject: [PATCH] module/system/base/target.scm: support riscv32
> > +
> > +Fix the following build failure on riscv32:
> > +
> > +system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > +unknown CPU word size "riscv32"
> > +
> > +Fixes:
> > + - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> > +
> > +Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> > +---
> > + module/system/base/target.scm | 1 +
> > + 1 file changed, 1 insertion(+)
> > +
> > +diff --git a/module/system/base/target.scm b/module/system/base/target.scm
> > +index 2088cd866..5544e234f 100644
> > +--- a/module/system/base/target.scm
> > ++++ b/module/system/base/target.scm
> > +@@ -121,6 +121,7 @@
> > +           ((member cpu '("sparc" "powerpc" "mips" "mipsel" "nios2" "m68k" "sh3" "sh4")) 4)
> > +           ((member cpu '("s390x" "alpha")) 8)
> > +           ((string-match "^arm.*" cpu) 4)
> > ++          ((string-match "^riscv.*" cpu) 8)
>
> Are you sure that a 32-bit CPU will have 8-byte wide words? I would
> have naturrally expected them to be just 4-byte wide...
>
> If htis is indeed the case, then please explain that in the patch commit
> log...

It should be 4-byte words for riscv32. Basically the same as 32-bit
arm except when it comes to time_t types (which are always 64-bits).

Alistair
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