* [PATCH v2 01/32] pci: Drop old code from pci command
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 02/32] ppc: Remove UCP1020 board Simon Glass
` (31 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
Drop the pre-driver model code from this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
cmd/pci.c | 212 ------------------------------------------------------
1 file changed, 212 deletions(-)
diff --git a/cmd/pci.c b/cmd/pci.c
index e53b7c858c6..8cfa5bbdaa7 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -47,7 +47,6 @@ static int pci_field_width(enum pci_size_t size)
return pci_byte_size(size) * 2;
}
-#ifdef CONFIG_DM_PCI
static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
{
for (; regs->name; regs++) {
@@ -59,40 +58,7 @@ static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
pci_field_width(regs->size), val);
}
}
-#else
-static unsigned long pci_read_config(pci_dev_t dev, int offset,
- enum pci_size_t size)
-{
- u32 val32;
- u16 val16;
- u8 val8;
- switch (size) {
- case PCI_SIZE_8:
- pci_read_config_byte(dev, offset, &val8);
- return val8;
- case PCI_SIZE_16:
- pci_read_config_word(dev, offset, &val16);
- return val16;
- case PCI_SIZE_32:
- default:
- pci_read_config_dword(dev, offset, &val32);
- return val32;
- }
-}
-
-static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
-{
- for (; regs->name; regs++) {
- printf(" %s =%*s%#.*lx\n", regs->name,
- (int)(28 - strlen(regs->name)), "",
- pci_field_width(regs->size),
- pci_read_config(dev, regs->offset, regs->size));
- }
-}
-#endif
-
-#ifdef CONFIG_DM_PCI
int pci_bar_show(struct udevice *dev)
{
u8 header_type;
@@ -162,7 +128,6 @@ int pci_bar_show(struct udevice *dev)
return 0;
}
-#endif
static struct pci_reg_info regs_start[] = {
{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
@@ -258,23 +223,12 @@ static struct pci_reg_info regs_cardbus[] = {
*
* @dev: Bus+Device+Function number
*/
-#ifdef CONFIG_DM_PCI
void pci_header_show(struct udevice *dev)
-#else
-void pci_header_show(pci_dev_t dev)
-#endif
{
-#ifdef CONFIG_DM_PCI
unsigned long class, header_type;
dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
-#else
- u8 class, header_type;
-
- pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
-#endif
pci_show_regs(dev, regs_start);
printf(" class code = 0x%.2x (%s)\n", (int)class,
pci_class_str(class));
@@ -307,7 +261,6 @@ void pciinfo_header(int busnum, bool short_listing)
}
}
-#ifdef CONFIG_DM_PCI
/**
* pci_header_show_brief() - Show the short-form PCI device header
*
@@ -355,102 +308,6 @@ static void pciinfo(struct udevice *bus, bool short_listing)
}
}
-#else
-
-/**
- * pci_header_show_brief() - Show the short-form PCI device header
- *
- * Reads and prints the header of the specified PCI device in short form.
- *
- * @dev: Bus+Device+Function number
- */
-void pci_header_show_brief(pci_dev_t dev)
-{
- u16 vendor, device;
- u8 class, subclass;
-
- pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(dev, PCI_DEVICE_ID, &device);
- pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
- pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
-
- printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
- vendor, device,
- pci_class_str(class), subclass);
-}
-
-/**
- * pciinfo() - Show a list of devices on the PCI bus
- *
- * Show information about devices on PCI bus. Depending on @short_pci_listing
- * the output will be more or less exhaustive.
- *
- * @bus_num: The number of the bus to be scanned
- * @short_pci_listing: true to use short form, showing only a brief header
- * for each device
- */
-void pciinfo(int bus_num, int short_pci_listing)
-{
- struct pci_controller *hose = pci_bus_to_hose(bus_num);
- int device;
- int function;
- unsigned char header_type;
- unsigned short vendor_id;
- pci_dev_t dev;
- int ret;
-
- if (!hose)
- return;
-
- pciinfo_header(bus_num, short_pci_listing);
-
- for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
- header_type = 0;
- vendor_id = 0;
- for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
- function++) {
- /*
- * If this is not a multi-function device, we skip
- * the rest.
- */
- if (function && !(header_type & 0x80))
- break;
-
- dev = PCI_BDF(bus_num, device, function);
-
- if (pci_skip_dev(hose, dev))
- continue;
-
- ret = pci_read_config_word(dev, PCI_VENDOR_ID,
- &vendor_id);
- if (ret)
- goto error;
- if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
- continue;
-
- if (!function) {
- pci_read_config_byte(dev, PCI_HEADER_TYPE,
- &header_type);
- }
-
- if (short_pci_listing) {
- printf("%02x.%02x.%02x ", bus_num, device,
- function);
- pci_header_show_brief(dev);
- } else {
- printf("\nFound PCI device %02x.%02x.%02x:\n",
- bus_num, device, function);
- pci_header_show(dev);
- }
- }
- }
-
- return;
-error:
- printf("Cannot read bus configuration: %d\n", ret);
-}
-#endif
-
/**
* get_pci_dev() - Convert the "bus.device.function" identifier into a number
*
@@ -482,13 +339,8 @@ static pci_dev_t get_pci_dev(char *name)
return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}
-#ifdef CONFIG_DM_PCI
static int pci_cfg_display(struct udevice *dev, ulong addr,
enum pci_size_t size, ulong length)
-#else
-static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
- ulong length)
-#endif
{
#define DISP_LINE_LEN 16
ulong i, nbytes, linebytes;
@@ -509,11 +361,7 @@ static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
for (i = 0; i < linebytes; i += byte_size) {
unsigned long val;
-#ifdef CONFIG_DM_PCI
dm_pci_read_config(dev, addr, &val, size);
-#else
- val = pci_read_config(bdf, addr, size);
-#endif
printf(" %0*lx", pci_field_width(size), val);
addr += byte_size;
}
@@ -528,31 +376,8 @@ static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
return (rc);
}
-#ifndef CONFIG_DM_PCI
-static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
-{
- if (size == 4) {
- pci_write_config_dword(bdf, addr, value);
- }
- else if (size == 2) {
- ushort val = value & 0xffff;
- pci_write_config_word(bdf, addr, val);
- }
- else {
- u_char val = value & 0xff;
- pci_write_config_byte(bdf, addr, val);
- }
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DM_PCI
static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
ulong value, int incrflag)
-#else
-static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
- int incrflag)
-#endif
{
ulong i;
int nbytes;
@@ -563,11 +388,7 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
*/
do {
printf("%08lx:", addr);
-#ifdef CONFIG_DM_PCI
dm_pci_read_config(dev, addr, &val, size);
-#else
- val = pci_read_config(bdf, addr, size);
-#endif
printf(" %0*lx", pci_field_width(size), val);
nbytes = cli_readline(" ? ");
@@ -594,11 +415,7 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
/* good enough to not time out
*/
bootretry_reset_cmd_timeout();
-#ifdef CONFIG_DM_PCI
dm_pci_write_config(dev, addr, i, size);
-#else
- pci_cfg_write(bdf, addr, size, i);
-#endif
if (incrflag)
addr += size;
}
@@ -608,7 +425,6 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
return 0;
}
-#ifdef CONFIG_DM_PCI
static const struct pci_flag_info {
uint flag;
const char *name;
@@ -647,7 +463,6 @@ static void pci_show_regions(struct udevice *bus)
printf("\n");
}
}
-#endif
/* PCI Configuration Space access commands
*
@@ -661,11 +476,7 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
ulong addr = 0, value = 0, cmd_size = 0;
enum pci_size_t size = PCI_SIZE_32;
-#ifdef CONFIG_DM_PCI
struct udevice *dev, *bus;
-#else
- pci_dev_t dev;
-#endif
int busnum = 0;
pci_dev_t bdf = 0;
char cmd = 's';
@@ -687,19 +498,15 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
if (argc > 4)
value = simple_strtoul(argv[4], NULL, 16);
case 'h': /* header */
-#ifdef CONFIG_DM_PCI
case 'b': /* bars */
-#endif
if (argc < 3)
goto usage;
if ((bdf = get_pci_dev(argv[2])) == -1)
return 1;
break;
-#if defined(CONFIG_DM_PCI)
case 'e':
pci_init();
return 0;
-#endif
case 'r': /* no break */
default: /* scan bus */
value = 1; /* short listing */
@@ -711,7 +518,6 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
if (argc > 1)
busnum = simple_strtoul(argv[1], NULL, 16);
}
-#ifdef CONFIG_DM_PCI
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
if (ret) {
printf("No such bus\n");
@@ -721,21 +527,14 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
pci_show_regions(bus);
else
pciinfo(bus, value);
-#else
- pciinfo(busnum, value);
-#endif
return 0;
}
-#ifdef CONFIG_DM_PCI
ret = dm_pci_bus_find_bdf(bdf, &dev);
if (ret) {
printf("No such device\n");
return CMD_RET_FAILURE;
}
-#else
- dev = bdf;
-#endif
switch (argv[1][0]) {
case 'h': /* header */
@@ -756,17 +555,10 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
case 'w': /* write */
if (argc < 5)
goto usage;
-#ifdef CONFIG_DM_PCI
ret = dm_pci_write_config(dev, addr, value, size);
-#else
- ret = pci_cfg_write(dev, addr, size, value);
-#endif
break;
-#ifdef CONFIG_DM_PCI
-
case 'b': /* bars */
return pci_bar_show(dev);
-#endif
default:
ret = CMD_RET_USAGE;
break;
@@ -783,18 +575,14 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
static char pci_help_text[] =
"[bus] [long]\n"
" - short or long list of PCI devices on bus 'bus'\n"
-#if defined(CONFIG_DM_PCI)
"pci enum\n"
" - Enumerate PCI buses\n"
-#endif
"pci header b.d.f\n"
" - show header of PCI device 'bus.device.function'\n"
-#ifdef CONFIG_DM_PCI
"pci bar b.d.f\n"
" - show BARs base and size for device b.d.f'\n"
"pci regions\n"
" - show PCI regions\n"
-#endif
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
" - display PCI configuration space (CFG)\n"
"pci next[.b, .w, .l] b.d.f address\n"
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 02/32] ppc: Remove UCP1020 board
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
2021-08-02 0:54 ` [PATCH v2 01/32] pci: Drop old code from pci command Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-02 3:00 ` Tom Rini
` (2 more replies)
2021-08-02 0:54 ` [PATCH v2 03/32] pci: Drop old code from header file Simon Glass
` (30 subsequent siblings)
32 siblings, 3 replies; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six,
Oleksandr Zhadan and Michael Durrant, Priyanka Jain,
Stefan Roese, Wolfgang Denk
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Leave the Kconfig options to avoid warnings on other boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Update to mention DM_PCI instead
board/Arcturus/ucp1020/Kconfig | 28 +-
board/Arcturus/ucp1020/MAINTAINERS | 7 -
board/Arcturus/ucp1020/Makefile | 31 -
board/Arcturus/ucp1020/README | 54 --
board/Arcturus/ucp1020/cmd_arc.c | 408 -------------
board/Arcturus/ucp1020/ddr.c | 161 ------
board/Arcturus/ucp1020/law.c | 24 -
board/Arcturus/ucp1020/spl.c | 127 ----
board/Arcturus/ucp1020/spl_minimal.c | 67 ---
board/Arcturus/ucp1020/tlb.c | 100 ----
board/Arcturus/ucp1020/ucp1020.c | 372 ------------
board/Arcturus/ucp1020/ucp1020.h | 45 --
configs/UCP1020_defconfig | 58 --
include/configs/UCP1020.h | 832 ---------------------------
14 files changed, 1 insertion(+), 2313 deletions(-)
delete mode 100644 board/Arcturus/ucp1020/MAINTAINERS
delete mode 100644 board/Arcturus/ucp1020/Makefile
delete mode 100644 board/Arcturus/ucp1020/README
delete mode 100644 board/Arcturus/ucp1020/cmd_arc.c
delete mode 100644 board/Arcturus/ucp1020/ddr.c
delete mode 100644 board/Arcturus/ucp1020/law.c
delete mode 100644 board/Arcturus/ucp1020/spl.c
delete mode 100644 board/Arcturus/ucp1020/spl_minimal.c
delete mode 100644 board/Arcturus/ucp1020/tlb.c
delete mode 100644 board/Arcturus/ucp1020/ucp1020.c
delete mode 100644 board/Arcturus/ucp1020/ucp1020.h
delete mode 100644 configs/UCP1020_defconfig
delete mode 100644 include/configs/UCP1020.h
diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig
index fe2c3be1b7a..60d80bab822 100644
--- a/board/Arcturus/ucp1020/Kconfig
+++ b/board/Arcturus/ucp1020/Kconfig
@@ -1,28 +1,4 @@
-if TARGET_UCP1020
-
-config SYS_BOARD
- string
- default "ucp1020"
-
-config SYS_VENDOR
- string
- default "Arcturus"
-
-config SYS_CONFIG_NAME
- string
- default "UCP1020"
-
-choice
- prompt "Target image select"
-
-config TARGET_UCP1020_NOR
- bool "NOR flash u-boot image"
-
-config TARGET_UCP1020_SPIFLASH
- bool "SPI flash u-boot image"
-
-endchoice
-
+# This exists only to avoid a warning for an unconverted value
if TARGET_UCP1020_SPIFLASH
config UCBOOT
bool
@@ -32,5 +8,3 @@ config SPIFLASH
bool
default y
endif
-
-endif
diff --git a/board/Arcturus/ucp1020/MAINTAINERS b/board/Arcturus/ucp1020/MAINTAINERS
deleted file mode 100644
index e4a4718188f..00000000000
--- a/board/Arcturus/ucp1020/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-UCP1020 BOARD
-M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
-S: Maintained
-F: board/Arcturus/ucp1020/
-F: include/configs/UCP1020.h
-F: configs/UCP1020_defconfig
-F: configs/UCP1020_SPIFLASH_defconfig
diff --git a/board/Arcturus/ucp1020/Makefile b/board/Arcturus/ucp1020/Makefile
deleted file mode 100644
index 46d04fb78c1..00000000000
--- a/board/Arcturus/ucp1020/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013-2015 Arcturus Networks, Inc.
-# based on board/freescale/p1_p2_rdb_pc/Makefile
-# original copyright follows:
-# Copyright 2010-2011 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-
-obj-y += ucp1020.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += cmd_arc.o
-
-endif
diff --git a/board/Arcturus/ucp1020/README b/board/Arcturus/ucp1020/README
deleted file mode 100644
index 555c4ef79fe..00000000000
--- a/board/Arcturus/ucp1020/README
+++ /dev/null
@@ -1,54 +0,0 @@
-The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
-product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
-DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
-
-Information on the generic product family can be found here:
- http://www.arcturusnetworks.com/products/ucp1020
-
-The UCP1020 several configurable options
-========================================
-
-- the selection of populated phy(s):
- KSZ9031 (current default for eTSEC 1 and 3)
-
-- the selection of boot location:
- SPI Flash or NOR flash
-
-The UCP1020 includes 2 default configurations
-=============================================
-NOR boot image:
- configs/UCP1020_defconfig
-SPI boot image:
- configs/UCP1020_SPIFLASH_defconfig
-
-The UCP1020 adds an additional command in cmd_arc.c to access and program
-SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
-HW Addresses.
-
-
-Build example
-=============
-
-make distclean
-make UCP1020_defconfig
-make
-
-Default Scripts
-===============
-A default upgrade scripts is included in the default environment variable example:
-
-B$ run tftpflash
-
-Dual Environment
-================
-
-This build enables dual / failover environment environment.
-
-NOR Flash Partition declarations and scripts
-============================================
-Several scripts are available to allow TFTP of images and programming directly
-into defined NOR flash partitions. Examples:
-
-B$ run program0
-B$ run program1
-B$ run program2
diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c
deleted file mode 100644
index 4b30b66e208..00000000000
--- a/board/Arcturus/ucp1020/cmd_arc.c
+++ /dev/null
@@ -1,408 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Command for accessing Arcturus factory environment.
- *
- * Copyright 2013-2019 Arcturus Networks Inc.
- * https://www.arcturusnetworks.com/products/
- * by Oleksandr G Zhadan et al.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <div64.h>
-#include <env.h>
-#include <flash.h>
-#include <malloc.h>
-#include <spi_flash.h>
-#include <mmc.h>
-#include <version.h>
-#include <asm/io.h>
-#include <linux/stringify.h>
-
-static ulong fwenv_addr[MAX_FWENV_ADDR];
-const char mystrerr[] = "ERROR: Failed to save factory info";
-
-static int ishwaddr(char *hwaddr)
-{
- if (strlen(hwaddr) == MAX_HWADDR_SIZE)
- if (hwaddr[2] == ':' &&
- hwaddr[5] == ':' &&
- hwaddr[8] == ':' &&
- hwaddr[11] == ':' &&
- hwaddr[14] == ':')
- return 0;
- return -1;
-}
-
-#if (FWENV_TYPE == FWENV_MMC)
-
-static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */
-
-int set_mmc_arc_product(int argc, char *const argv[])
-{
- struct mmc *mmc;
- u32 blk, cnt, n;
- int i, err = 1;
- void *addr;
- const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
-
- mmc = find_mmc_device(mmc_dev_num);
- if (!mmc) {
- printf("No SD/MMC/eMMC card found\n");
- return 0;
- }
- if (mmc_init(mmc)) {
- printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
- mmc_dev_num);
- return 0;
- }
- if (mmc_getwp(mmc) == 1) {
- printf("Error: card is write protected!\n");
- return CMD_RET_FAILURE;
- }
-
- /* Save factory defaults */
- addr = (void *)smac;
- cnt = 1; /* One 512 bytes block */
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- blk = fwenv_addr[i] / 512;
- n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
- if (n != cnt)
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- }
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_mmc_arc_info(void)
-{
- struct mmc *mmc;
- u32 blk, cnt, n;
- int i;
- void *addr;
- const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
-
- mmc = find_mmc_device(mmc_dev_num);
- if (!mmc) {
- printf("No SD/MMC/eMMC card found\n");
- return 0;
- }
- if (mmc_init(mmc)) {
- printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
- mmc_dev_num);
- return 0;
- }
-
- addr = (void *)smac;
- cnt = 1; /* One 512 bytes block */
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- blk = fwenv_addr[i] / 512;
- n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
- flush_cache((ulong) addr, 512);
- if (n == cnt)
- return (i + 1);
- }
- return 0;
-}
-#endif
-
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
-
-static struct spi_flash *flash;
-static char smac[4][18];
-
-int set_spi_arc_product(int argc, char *const argv[])
-{
- int i, err = 1;
-
- flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!flash) {
- printf("Failed to initialize SPI flash at %u:%u\n",
- CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
- return -1;
- }
-
- /* Save factory defaults */
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- if (spi_flash_write
- (flash, fwenv_addr[i], sizeof(smac), smac))
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_spi_arc_info(void)
-{
- int i;
-
- flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!flash) {
- printf("Failed to initialize SPI flash at %u:%u\n",
- CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
- return 0;
- }
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- if (!spi_flash_read
- (flash, fwenv_addr[i], sizeof(smac), smac))
- return (i + 1);
- return 0;
-}
-#endif
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
-
-static char smac[4][18];
-
-int set_nor_arc_product(int argc, char *const argv[])
-{
- int i, err = 1;
-
- /* Save factory defaults */
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- ulong fwenv_end = fwenv_addr[i] + 4;
-
- flash_sect_roundb(&fwenv_end);
- flash_sect_protect(0, fwenv_addr[i], fwenv_end);
- if (flash_write
- ((char *)smac, fwenv_addr[i], sizeof(smac)))
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- flash_sect_protect(1, fwenv_addr[i], fwenv_end);
- }
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_nor_arc_info(void)
-{
- int i;
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- memcpy(smac, (void *)fwenv_addr[i], sizeof(smac));
- return (i + 1);
- }
-
- return 0;
-}
-#endif
-
-int set_arc_product(int argc, char *const argv[])
-{
- if (argc != 5)
- return -1;
-
- /* Check serial number */
- if (strlen(argv[1]) != MAX_SERIAL_SIZE)
- return -1;
-
- /* Check HWaddrs */
- if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
- return -1;
-
- strcpy(smac[0], argv[1]);
- strcpy(smac[1], argv[2]);
- strcpy(smac[2], argv[3]);
- strcpy(smac[3], argv[4]);
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
- return set_nor_arc_product(argc, argv);
-#endif
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
- return set_spi_arc_product(argc, argv);
-#endif
-#if (FWENV_TYPE == FWENV_MMC)
- return set_mmc_arc_product(argc, argv);
-#endif
- return -2;
-}
-
-static int read_arc_info(void)
-{
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
- return read_nor_arc_info();
-#endif
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
- return read_spi_arc_info();
-#endif
-#if (FWENV_TYPE == FWENV_MMC)
- return read_mmc_arc_info();
-#endif
- return 0;
-}
-
-static int do_get_arc_info(void)
-{
- int l = read_arc_info();
- char *oldserial = env_get("SERIAL");
- char *oldversion = env_get("VERSION");
-
- if (oldversion != NULL)
- if (strcmp(oldversion, U_BOOT_VERSION) != 0)
- oldversion = NULL;
-
- if (l == 0) {
- printf("%s: failed to read factory info\n", __func__);
- return -2;
- }
-
- printf("\rSERIAL: ");
- if (smac[0][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- printf("%s\n", smac[0]);
- env_set("SERIAL", smac[0]);
- }
-
- if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
- env_set("ethaddr", NULL);
- env_set("eth1addr", NULL);
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR0: ");
- if (smac[1][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("ethaddr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[1]);
- printf("%s\n", smac[1]);
- } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
- env_set("ethaddr", smac[1]);
- printf("%s (factory)\n", smac[1]);
- } else {
- printf("%s\n", ret);
- }
- }
-
- if (strcmp(smac[2], "00:00:00:00:00:00") == 0) {
- env_set("eth1addr", NULL);
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR1: ");
- if (smac[2][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("eth1addr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[2]);
- printf("%s\n", smac[2]);
- } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
- env_set("eth1addr", smac[2]);
- printf("%s (factory)\n", smac[2]);
- } else {
- printf("%s\n", ret);
- }
- }
-
- if (strcmp(smac[3], "00:00:00:00:00:00") == 0) {
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR2: ");
- if (smac[3][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("eth2addr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[3]);
- printf("%s\n", smac[3]);
- } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
- env_set("eth2addr", smac[3]);
- printf("%s (factory)\n", smac[3]);
- } else {
- printf("%s\n", ret);
- }
- }
-done:
- if (oldserial == NULL || oldversion == NULL) {
- if (oldversion == NULL)
- env_set("VERSION", U_BOOT_VERSION);
- env_save();
- }
-
- return 0;
-}
-
-static int init_fwenv(void)
-{
- int i, ret = -1;
-
- fwenv_addr[0] = FWENV_ADDR1;
- fwenv_addr[1] = FWENV_ADDR2;
- fwenv_addr[2] = FWENV_ADDR3;
- fwenv_addr[3] = FWENV_ADDR4;
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- ret = 0;
- if (ret)
- printf("%s: No firmfare info storage address is defined\n",
- __func__);
- return ret;
-}
-
-void get_arc_info(void)
-{
- if (!init_fwenv())
- do_get_arc_info();
-}
-
-static int do_arc_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- const char *cmd;
- int ret = -1;
-
- cmd = argv[1];
- --argc;
- ++argv;
-
- if (init_fwenv())
- return ret;
-
- if (strcmp(cmd, "product") == 0)
- ret = set_arc_product(argc, argv);
- else if (strcmp(cmd, "info") == 0)
- ret = do_get_arc_info();
-
- if (ret == -1)
- return CMD_RET_USAGE;
-
- return ret;
-}
-
-U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
- "Arcturus product command sub-system",
- "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
- "info - show Arcturus factory env\n\n");
diff --git a/board/Arcturus/ucp1020/ddr.c b/board/Arcturus/ucp1020/ddr.c
deleted file mode 100644
index a3285ebe5cd..00000000000
--- a/board/Arcturus/ucp1020/ddr.c
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
-/*
- * Micron MT41J128M16HA-15E
- * */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 536870912u,
- .capacity = 536870912u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1650,
- .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
- .taa_ps = 14050,
- .twr_ps = 15000,
- .trcd_ps = 13500,
- .trrd_ps = 75000,
- .trp_ps = 13500,
- .tras_ps = 40000,
- .trc_ps = 49500,
- .trfc_ps = 160000,
- .twtr_ps = 75000,
- .trtp_ps = 75000,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
-
-#else
-#error Missing raw timing data for this board
-#endif
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
-
-#ifdef CONFIG_SYS_DDR_CS0_BNDS
-/* Fixed sdram init -- doesn't use serial presence detect. */
-phys_size_t fixed_sdram(void)
-{
- sys_info_t sysinfo;
- char buf[32];
- size_t ddr_size;
- fsl_ddr_cfg_regs_t ddr_cfg_regs = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
-#endif
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
- .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
- };
-
- get_sys_info(&sysinfo);
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freq_ddrbus));
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return ddr_size;
-}
-#endif
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
-
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- if (pdimm->primary_sdram_width == 64)
- popts->data_bus_width = 0;
- else if (pdimm->primary_sdram_width == 32)
- popts->data_bus_width = 1;
- else
- printf("Error in DDR bus width configuration!\n");
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
diff --git a/board/Arcturus/ucp1020/law.c b/board/Arcturus/ucp1020/law.c
deleted file mode 100644
index cb53692a32b..00000000000
--- a/board/Arcturus/ucp1020/law.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_VSC7385_ENET
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#endif
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
deleted file mode 100644
index f7c4960da7c..00000000000
--- a/board/Arcturus/ucp1020/spl.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const u32 sysclk_tbl[] = {
- 66666000, 7499900, 83332500, 8999900,
- 99999000, 11111000, 12499800, 13333200
-};
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- gd->bus_clk = bus_clk;
-
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- struct bd_info *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(struct bd_info));
- gd->bd = bd;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
-
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
- gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#else
- env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C_LEGACY
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/Arcturus/ucp1020/spl_minimal.c b/board/Arcturus/ucp1020/spl_minimal.c
deleted file mode 100644
index 90abec9cce5..00000000000
--- a/board/Arcturus/ucp1020/spl_minimal.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
- * original copyright follows:
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
-
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c
deleted file mode 100644
index 2c07df63e5b..00000000000
--- a/board/Arcturus/ucp1020/tlb.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/tlb.c
- * original copyright follows:
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI memory 1.5G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O effective: 192K */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#ifdef CONFIG_VSC7385_ENET
- /* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-#endif
-#endif /* not SPL */
-
-#ifdef CONFIG_SYS_NAND_BASE
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* *I*G - eSDHC/eSPI/NAND boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-
-#endif /* RAMBOOT/SPL */
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1)
-#endif
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c
deleted file mode 100644
index 24d1d57ec4b..00000000000
--- a/board/Arcturus/ucp1020/ucp1020.c
+++ /dev/null
@@ -1,372 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * by Oleksandr G Zhadan et al.
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <ioports.h>
-#include <netdev.h>
-#include <micrel.h>
-#include <spi_flash.h>
-#include <mmc.h>
-#include <linux/ctype.h>
-#include <asm/fsl_serdes.h>
-#include <asm/gpio.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_lbc.h>
-#include <asm/mp.h>
-#include "ucp1020.h"
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- /* TO DO: It's actially have to be in spi/ */
-}
-
-/*
- * To be compatible with cmd_gpio
- */
-int name_to_gpio(const char *name)
-{
- int gpio = 31 - simple_strtoul(name, NULL, 10);
-
- if (gpio < 16)
- gpio = -1;
-
- return gpio;
-}
-
-void board_gpio_init(void)
-{
- int i;
- char envname[8], *val;
-
- for (i = 0; i < GPIO_MAX_NUM; i++) {
- sprintf(envname, "GPIO%d", i);
- val = env_get(envname);
- if (val) {
- char direction = toupper(val[0]);
- char level = toupper(val[1]);
-
- if (direction == 'I') {
- gpio_direction_input(i);
- } else {
- if (direction == 'O') {
- if (level == '1')
- gpio_direction_output(i, 1);
- else
- gpio_direction_output(i, 0);
- }
- }
- }
- }
-
- val = env_get("PCIE_OFF");
- if (val) {
- gpio_direction_input(GPIO_PCIE1_EN);
- gpio_direction_input(GPIO_PCIE2_EN);
- } else {
- gpio_direction_output(GPIO_PCIE1_EN, 1);
- gpio_direction_output(GPIO_PCIE2_EN, 1);
- }
-
- val = env_get("SDHC_CDWP_OFF");
- if (!val) {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
- }
-}
-
-int board_early_init_f(void)
-{
- return 0; /* Just in case. Could be disable in config file */
-}
-
-int checkboard(void)
-{
- printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
- board_gpio_init();
-#ifdef CONFIG_MMC
- printf("SD/MMC: 4-bit Mode\n");
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-#if defined(CONFIG_PHY_MICREL_KSZ9021)
- int regval;
- static int cnt;
-
- if (cnt++ == 0)
- printf("PHYs address [");
-
- if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
- regval =
- ksz9021_phy_extended_read(phydev,
- MII_KSZ9021_EXT_STRAP_STATUS);
- /*
- * min rx data delay
- */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x6666);
- /*
- * max rx/tx clock delay, min rx/tx control
- */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf6f6);
- printf("0x%x", (regval & 0x1f));
- } else {
- printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
- }
- if (cnt == 3)
- printf("] ");
- else
- printf(",");
-#endif
-
-#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
- regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
- if (regval >= 0)
- printf(" (ADDR 0x%x) ", regval & 0x1f);
-#endif
-
- return 0;
-}
-
-int last_stage_init(void)
-{
- static char newkernelargs[256];
- static u8 id1[16];
- static u8 id2;
-#ifdef CONFIG_MMC
- struct mmc *mmc;
-#endif
- char *sval, *kval;
-
- if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
- printf("Error reading i2c IDT6V49205B information!\n");
- } else {
- printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
- i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
- if (!(id1[1] & 0x02)) {
- id1[1] |= 0x02;
- i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
- asm("nop; nop");
- }
- }
-
- if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
- printf("Error reading i2c NCT72 information!\n");
- else
- printf("NCT72(0x%x): ready\n", id2);
-
- kval = env_get("kernelargs");
-
-#ifdef CONFIG_MMC
- mmc = find_mmc_device(0);
- if (mmc)
- if (!mmc_init(mmc)) {
- printf("MMC/SD card detected\n");
- if (kval) {
- int n = strlen(defkargs);
- char *tmp = strstr(kval, defkargs);
-
- *tmp = 0;
- strcpy(newkernelargs, kval);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, mmckargs);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, &tmp[n]);
- env_set("kernelargs", newkernelargs);
- } else {
- env_set("kernelargs", mmckargs);
- }
- }
-#endif
- get_arc_info();
-
- if (kval) {
- sval = env_get("SERIAL");
- if (sval) {
- strcpy(newkernelargs, "SN=");
- strcat(newkernelargs, sval);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, kval);
- env_set("kernelargs", newkernelargs);
- }
- } else {
- printf("Error reading kernelargs env variable!\n");
- }
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
-#ifdef CONFIG_TSEC2
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
- }
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
- const char *soc_usb_compat = "fsl-usb2-dr";
- int err, usb1_off, usb2_off;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- /* Delete eLBC node as it is muxed with USB2 controller */
- if (hwconfig("usb2")) {
- const char *soc_elbc_compat = "fsl,p1020-elbc";
- int off = fdt_node_offset_by_compatible(blob, -1,
- soc_elbc_compat);
- if (off < 0) {
- printf
- ("WARNING: could not find compatible node %s: %s\n",
- soc_elbc_compat, fdt_strerror(off));
- return off;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s\n",
- soc_elbc_compat, fdt_strerror(err));
- }
- return err;
- }
-#endif
-
-/* Delete USB2 node as it is muxed with eLBC */
- usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
- if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat, fdt_strerror(usb1_off));
- return usb1_off;
- }
- usb2_off =
- fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
- if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat, fdt_strerror(usb2_off));
- return usb2_off;
- }
- err = fdt_del_node(blob, usb2_off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_usb_compat, fdt_strerror(err));
- }
- return 0;
-}
-#endif
diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h
deleted file mode 100644
index 1b527cdb1cf..00000000000
--- a/board/Arcturus/ucp1020/ucp1020.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * by Oleksandr G Zhadan et al.
- */
-
-#ifndef __UCP1020_H__
-#define __UCP1020_H__
-
-#define GPIO0 31
-#define GPIO1 30
-#define GPIO2 29
-#define GPIO3 28
-#define GPIO4 27
-#define GPIO5 26
-#define GPIO6 25
-#define GPIO7 24
-#define GPIO8 23
-#define GPIO9 22
-#define GPIO10 21
-#define GPIO11 20
-#define GPIO12 19
-#define GPIO13 18
-#define GPIO14 17
-#define GPIO15 16
-#define GPIO_MAX_NUM 16
-
-#define GPIO_SDHC_CD GPIO8
-#define GPIO_SDHC_WP GPIO9
-#define GPIO_USB_PCTL0 GPIO10
-#define GPIO_PCIE1_EN GPIO11
-#define GPIO_PCIE2_EN GPIO10
-#define GPIO_USB_PCTL1 GPIO11
-
-#define GPIO_WD GPIO15
-
-#ifdef CONFIG_MMC
-static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
-static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
-#endif
-
-int get_arc_info(void);
-
-#endif
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
deleted file mode 100644
index 1fdb1952c8f..00000000000
--- a/configs/UCP1020_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF80000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_UCP1020=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="B$ "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_PCI is not set
-# CONFIG_CMD_SATA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_CRAMFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEC0C0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_FS_CRAMFS=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
deleted file mode 100644
index d9a777ea1a0..00000000000
--- a/include/configs/UCP1020.h
+++ /dev/null
@@ -1,832 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * based on include/configs/p1_p2_rdb_pc.h
- * original copyright follows:
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * QorIQ uCP1020-xx boards configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*** Arcturus FirmWare Environment */
-
-#define MAX_SERIAL_SIZE 15
-#define MAX_HWADDR_SIZE 17
-
-#define MAX_FWENV_ADDR 4
-
-#define FWENV_MMC 1
-#define FWENV_SPI_FLASH 2
-#define FWENV_NOR_FLASH 3
-/*
- #define FWENV_TYPE FWENV_MMC
- #define FWENV_TYPE FWENV_SPI_FLASH
-*/
-#define FWENV_TYPE FWENV_NOR_FLASH
-
-#if (FWENV_TYPE == FWENV_MMC)
-#define FWENV_ADDR1 -1
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0
-#endif
-
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
-#ifndef CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_SF_DEFAULT_SPEED 1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE0
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-#define CONFIG_SF_DEFAULT_CS 0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-#define CONFIG_SF_DEFAULT_BUS 0
-#endif
-#define FWENV_ADDR1 (0x200 - sizeof(smac))
-#define FWENV_ADDR2 (0x400 - sizeof(smac))
-#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
-#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
-#define EMPY_CHAR 0xff
-#endif
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
-#define FWENV_ADDR1 0xEC080000
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0xff
-#endif
-/***********************************/
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#if defined(CONFIG_TARTGET_UCP1020T1)
-
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
-#define CONFIG_IPADDR 10.80.41.229
-#define CONFIG_SERVERIP 10.80.41.227
-#define CONFIG_NETMASK 255.255.252.0
-#define CONFIG_ETHPRIME "eTSEC3"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#if defined(CONFIG_TARGET_UCP1020)
-
-#define CONFIG_UCP1020
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
-#define CONFIG_IPADDR 192.168.1.81
-#define CONFIG_IPADDR1 192.168.1.82
-#define CONFIG_IPADDR2 192.168.1.83
-#define CONFIG_SERVERIP 192.168.1.80
-#define CONFIG_GATEWAYIP 102.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
- SPL code*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* Default settings for DDR3 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#ifdef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
-#else
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#endif
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x40461520
-#define CONFIG_SYS_DDR_MODE_2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
- * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
- * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
- * (early boot only)
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-
-#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
-
-#define CONFIG_SYS_PMC_BASE 0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
-
-#define CONFIG_RTC_DS1337
-#define CONFIG_RTC_DS1337_NOOSC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
-#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
-#define CONFIG_SYS_I2C_IDT6V49205B 0x69
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/*
- * Environment
- */
-#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Misc Extra Settings */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
-#else
-#error "UCP1020 module revision is not defined !!!"
-#endif
-
-#define CONFIG_BOOTP_SERVERIP
-
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 4
-#define TSEC2_PHY_ADDR 0
-#define TSEC2_PHY_ADDR_SGMII 0x00
-#define TSEC3_PHY_ADDR 6
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#endif
-
-#define CONFIG_HOSTNAME "UCP1020"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#if defined(CONFIG_DONGLE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run prog_spi_mbrbootcramfs\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020d.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"mmbr=uCP1020Quiet.mbr\0" \
-"mmcpart=0:2\0" \
-"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "mmc erase 1 1; " \
- "mmc write $loadaddr 1 1\0" \
-"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
- "mmc erase 0x40 0x400; " \
- "mmc write $loadaddr 0x40 0x400\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"prog_spi_mbr=run spi__mbr\0" \
-"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
-"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
- "run spi__cramfs\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeFF80000 +$filesize; " \
- "erase 0xEFF80000 +$filesize; " \
- "cp.b $loadaddr 0xEFF80000 $filesize; " \
- "cmp.b $loadaddr 0xEFF80000 $filesize; " \
- "protect on 0xeFF80000 +$filesize\0" \
-"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
- "sf probe 0; sf erase 0x8000 +$filesize; " \
- "sf write $loadaddr 0x8000 $filesize\0" \
-"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
- "protect off 0xec0a0000 +$filesize; " \
- "erase 0xeC0A0000 +$filesize; " \
- "cp.b $loadaddr 0xeC0A0000 $filesize; " \
- "protect on 0xec0a0000 +$filesize\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 1; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"ubootd=u-boot4dongle.bin\0" \
-"upgrade=run flashworking\0" \
-"usb_phy_type=ulpi\0 " \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else
-
-#if defined(CONFIG_UCP1020T1)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"othbootargs=quiet\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"silent=1\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashworking\0" \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else /* For Arcturus Modules */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run norkernel\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashuboot=tftp $loadaddr $ubootfile; " \
- "protect off $nor_ubootaddr0 +$filesize; " \
- "erase $nor_ubootaddr0 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
- "protect on $nor_ubootaddr0 +$filesize; " \
- "protect off $nor_ubootaddr1 +$filesize; " \
- "erase $nor_ubootaddr1 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
- "protect on $nor_ubootaddr1 +$filesize\0 " \
-"format0=protect off $part0base +$part0size; " \
- "erase $part0base +$part0size\0" \
-"format1=protect off $part1base +$part1size; " \
- "erase $part1base +$part1size\0" \
-"format2=protect off $part2base +$part2size; " \
- "erase $part2base +$part2size\0" \
-"format3=protect off $part3base +$part3size; " \
- "erase $part3base +$part3size\0" \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_ubootaddr0=0xEC000000\0" \
-"nor_ubootaddr1=0xEFF80000\0" \
-"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
- "run norkernelload; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $part0base; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"part0base=0xEC100000\0" \
-"part0size=0x00700000\0" \
-"part1base=0xEC800000\0" \
-"part1size=0x02000000\0" \
-"part2base=0xEE800000\0" \
-"part2size=0x00800000\0" \
-"part3base=0xEF000000\0" \
-"part3size=0x00F80000\0" \
-"partENVbase=0xEC080000\0" \
-"partENVsize=0x00080000\0" \
-"program0=tftp part0-000000.bin; " \
- "protect off $part0base +$filesize; " \
- "erase $part0base +$filesize; " \
- "cp.b $loadaddr $part0base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part0base $filesize\0" \
-"program1=tftp part1-000000.bin; " \
- "protect off $part1base +$filesize; " \
- "erase $part1base +$filesize; " \
- "cp.b $loadaddr $part1base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part1base $filesize\0" \
-"program2=tftp part2-000000.bin; " \
- "protect off $part2base +$filesize; " \
- "erase $part2base +$filesize; " \
- "cp.b $loadaddr $part2base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part2base $filesize\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashuboot\0" \
-"usb_phy_type=ulpi\0 " \
-"boot_nfs= " \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_hd = " \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_usb_fat = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "fatload usb 0:2 $loadaddr $bootfile;" \
- "fatload usb 0:2 $fdtaddr $fdtfile;" \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_usb_ext2 = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_nor = " \
- "setenv bootargs root=/dev/$jffs2nor rw " \
- "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
- "bootm $norbootaddr - $norfdtaddr\0 " \
-"boot_ram = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
-
-#endif
-#endif
-
-#endif /* __CONFIG_H */
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 02/32] ppc: Remove UCP1020 board
2021-08-02 0:54 ` [PATCH v2 02/32] ppc: Remove UCP1020 board Simon Glass
@ 2021-08-02 3:00 ` Tom Rini
2021-09-13 18:46 ` Arcturus Support
2021-09-14 1:02 ` Tom Rini
2 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-02 3:00 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six,
Oleksandr Zhadan and Michael Durrant, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 495 bytes --]
On Sun, Aug 01, 2021 at 06:54:15PM -0600, Simon Glass wrote:
> This board has not been converted to CONFIG_DM_PCI by the deadline.
> Remove it.
>
> Leave the Kconfig options to avoid warnings on other boards.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Update to mention DM_PCI instead
Again, note that an alternative here would be to disable PCI, and other
non-required on the board features and enable DM as soon as possible.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 02/32] ppc: Remove UCP1020 board
2021-08-02 0:54 ` [PATCH v2 02/32] ppc: Remove UCP1020 board Simon Glass
2021-08-02 3:00 ` Tom Rini
@ 2021-09-13 18:46 ` Arcturus Support
2021-09-14 1:02 ` Tom Rini
2 siblings, 0 replies; 73+ messages in thread
From: Arcturus Support @ 2021-09-13 18:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Leave the Kconfig options to avoid warnings on other boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan and Michael Durrant
<arcsupport@arcturusnetworks.com>
---
Changes in v2:
- Update to mention DM_PCI instead
board/Arcturus/ucp1020/Kconfig | 28 +-
board/Arcturus/ucp1020/MAINTAINERS | 7 -
board/Arcturus/ucp1020/Makefile | 31 -
board/Arcturus/ucp1020/README | 54 --
board/Arcturus/ucp1020/cmd_arc.c | 408 -------------
board/Arcturus/ucp1020/ddr.c | 161 ------
board/Arcturus/ucp1020/law.c | 24 -
board/Arcturus/ucp1020/spl.c | 127 ----
board/Arcturus/ucp1020/spl_minimal.c | 67 ---
board/Arcturus/ucp1020/tlb.c | 100 ----
board/Arcturus/ucp1020/ucp1020.c | 372 ------------
board/Arcturus/ucp1020/ucp1020.h | 45 --
configs/UCP1020_defconfig | 58 --
include/configs/UCP1020.h | 832 ---------------------------
14 files changed, 1 insertion(+), 2313 deletions(-)
delete mode 100644 board/Arcturus/ucp1020/MAINTAINERS
delete mode 100644 board/Arcturus/ucp1020/Makefile
delete mode 100644 board/Arcturus/ucp1020/README
delete mode 100644 board/Arcturus/ucp1020/cmd_arc.c
delete mode 100644 board/Arcturus/ucp1020/ddr.c
delete mode 100644 board/Arcturus/ucp1020/law.c
delete mode 100644 board/Arcturus/ucp1020/spl.c
delete mode 100644 board/Arcturus/ucp1020/spl_minimal.c
delete mode 100644 board/Arcturus/ucp1020/tlb.c
delete mode 100644 board/Arcturus/ucp1020/ucp1020.c
delete mode 100644 board/Arcturus/ucp1020/ucp1020.h
delete mode 100644 configs/UCP1020_defconfig
delete mode 100644 include/configs/UCP1020.h
diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig
index fe2c3be1b7a..60d80bab822 100644
--- a/board/Arcturus/ucp1020/Kconfig
+++ b/board/Arcturus/ucp1020/Kconfig
@@ -1,28 +1,4 @@
-if TARGET_UCP1020
-
-config SYS_BOARD
- string
- default "ucp1020"
-
-config SYS_VENDOR
- string
- default "Arcturus"
-
-config SYS_CONFIG_NAME
- string
- default "UCP1020"
-
-choice
- prompt "Target image select"
-
-config TARGET_UCP1020_NOR
- bool "NOR flash u-boot image"
-
-config TARGET_UCP1020_SPIFLASH
- bool "SPI flash u-boot image"
-
-endchoice
-
+# This exists only to avoid a warning for an unconverted value
if TARGET_UCP1020_SPIFLASH
config UCBOOT
bool
@@ -32,5 +8,3 @@ config SPIFLASH
bool
default y
endif
-
-endif
diff --git a/board/Arcturus/ucp1020/MAINTAINERS
b/board/Arcturus/ucp1020/MAINTAINERS
deleted file mode 100644
index e4a4718188f..00000000000
--- a/board/Arcturus/ucp1020/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-UCP1020 BOARD
-M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
-S: Maintained
-F: board/Arcturus/ucp1020/
-F: include/configs/UCP1020.h
-F: configs/UCP1020_defconfig
-F: configs/UCP1020_SPIFLASH_defconfig
diff --git a/board/Arcturus/ucp1020/Makefile
b/board/Arcturus/ucp1020/Makefile
deleted file mode 100644
index 46d04fb78c1..00000000000
--- a/board/Arcturus/ucp1020/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013-2015 Arcturus Networks, Inc.
-# based on board/freescale/p1_p2_rdb_pc/Makefile
-# original copyright follows:
-# Copyright 2010-2011 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-
-obj-y += ucp1020.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += cmd_arc.o
-
-endif
diff --git a/board/Arcturus/ucp1020/README b/board/Arcturus/ucp1020/README
deleted file mode 100644
index 555c4ef79fe..00000000000
--- a/board/Arcturus/ucp1020/README
+++ /dev/null
@@ -1,54 +0,0 @@
-The uCP1020 product family (ucp1020) is an Arcturus Networks Inc.
System on Modules
-product featuring a Freescale P1020 CPU, optionally populated with 1, 2
or 3 Gig-Ethernet PHYs,
-DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
-
-Information on the generic product family can be found here:
- http://www.arcturusnetworks.com/products/ucp1020
-
-The UCP1020 several configurable options
-========================================
-
-- the selection of populated phy(s):
- KSZ9031 (current default for eTSEC 1 and 3)
-
-- the selection of boot location:
- SPI Flash or NOR flash
-
-The UCP1020 includes 2 default configurations
-=============================================
-NOR boot image:
- configs/UCP1020_defconfig
-SPI boot image:
- configs/UCP1020_SPIFLASH_defconfig
-
-The UCP1020 adds an additional command in cmd_arc.c to access and program
-SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
-HW Addresses.
-
-
-Build example
-=============
-
-make distclean
-make UCP1020_defconfig
-make
-
-Default Scripts
-===============
-A default upgrade scripts is included in the default environment
variable example:
-
-B$ run tftpflash
-
-Dual Environment
-================
-
-This build enables dual / failover environment environment.
-
-NOR Flash Partition declarations and scripts
-============================================
-Several scripts are available to allow TFTP of images and programming
directly
-into defined NOR flash partitions. Examples:
-
-B$ run program0
-B$ run program1
-B$ run program2
diff --git a/board/Arcturus/ucp1020/cmd_arc.c
b/board/Arcturus/ucp1020/cmd_arc.c
deleted file mode 100644
index 4b30b66e208..00000000000
--- a/board/Arcturus/ucp1020/cmd_arc.c
+++ /dev/null
@@ -1,408 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Command for accessing Arcturus factory environment.
- *
- * Copyright 2013-2019 Arcturus Networks Inc.
- * https://www.arcturusnetworks.com/products/
- * by Oleksandr G Zhadan et al.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <div64.h>
-#include <env.h>
-#include <flash.h>
-#include <malloc.h>
-#include <spi_flash.h>
-#include <mmc.h>
-#include <version.h>
-#include <asm/io.h>
-#include <linux/stringify.h>
-
-static ulong fwenv_addr[MAX_FWENV_ADDR];
-const char mystrerr[] = "ERROR: Failed to save factory info";
-
-static int ishwaddr(char *hwaddr)
-{
- if (strlen(hwaddr) == MAX_HWADDR_SIZE)
- if (hwaddr[2] == ':' &&
- hwaddr[5] == ':' &&
- hwaddr[8] == ':' &&
- hwaddr[11] == ':' &&
- hwaddr[14] == ':')
- return 0;
- return -1;
-}
-
-#if (FWENV_TYPE == FWENV_MMC)
-
-static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC
block is 512 bytes */
-
-int set_mmc_arc_product(int argc, char *const argv[])
-{
- struct mmc *mmc;
- u32 blk, cnt, n;
- int i, err = 1;
- void *addr;
- const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
-
- mmc = find_mmc_device(mmc_dev_num);
- if (!mmc) {
- printf("No SD/MMC/eMMC card found\n");
- return 0;
- }
- if (mmc_init(mmc)) {
- printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
- mmc_dev_num);
- return 0;
- }
- if (mmc_getwp(mmc) == 1) {
- printf("Error: card is write protected!\n");
- return CMD_RET_FAILURE;
- }
-
- /* Save factory defaults */
- addr = (void *)smac;
- cnt = 1; /* One 512 bytes block */
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- blk = fwenv_addr[i] / 512;
- n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
- if (n != cnt)
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- }
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_mmc_arc_info(void)
-{
- struct mmc *mmc;
- u32 blk, cnt, n;
- int i;
- void *addr;
- const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
-
- mmc = find_mmc_device(mmc_dev_num);
- if (!mmc) {
- printf("No SD/MMC/eMMC card found\n");
- return 0;
- }
- if (mmc_init(mmc)) {
- printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
- mmc_dev_num);
- return 0;
- }
-
- addr = (void *)smac;
- cnt = 1; /* One 512 bytes block */
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- blk = fwenv_addr[i] / 512;
- n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
- flush_cache((ulong) addr, 512);
- if (n == cnt)
- return (i + 1);
- }
- return 0;
-}
-#endif
-
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
-
-static struct spi_flash *flash;
-static char smac[4][18];
-
-int set_spi_arc_product(int argc, char *const argv[])
-{
- int i, err = 1;
-
- flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!flash) {
- printf("Failed to initialize SPI flash at %u:%u\n",
- CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
- return -1;
- }
-
- /* Save factory defaults */
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- if (spi_flash_write
- (flash, fwenv_addr[i], sizeof(smac), smac))
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_spi_arc_info(void)
-{
- int i;
-
- flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!flash) {
- printf("Failed to initialize SPI flash at %u:%u\n",
- CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
- return 0;
- }
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- if (!spi_flash_read
- (flash, fwenv_addr[i], sizeof(smac), smac))
- return (i + 1);
- return 0;
-}
-#endif
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
-
-static char smac[4][18];
-
-int set_nor_arc_product(int argc, char *const argv[])
-{
- int i, err = 1;
-
- /* Save factory defaults */
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- ulong fwenv_end = fwenv_addr[i] + 4;
-
- flash_sect_roundb(&fwenv_end);
- flash_sect_protect(0, fwenv_addr[i], fwenv_end);
- if (flash_write
- ((char *)smac, fwenv_addr[i], sizeof(smac)))
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- flash_sect_protect(1, fwenv_addr[i], fwenv_end);
- }
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_nor_arc_info(void)
-{
- int i;
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- memcpy(smac, (void *)fwenv_addr[i], sizeof(smac));
- return (i + 1);
- }
-
- return 0;
-}
-#endif
-
-int set_arc_product(int argc, char *const argv[])
-{
- if (argc != 5)
- return -1;
-
- /* Check serial number */
- if (strlen(argv[1]) != MAX_SERIAL_SIZE)
- return -1;
-
- /* Check HWaddrs */
- if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
- return -1;
-
- strcpy(smac[0], argv[1]);
- strcpy(smac[1], argv[2]);
- strcpy(smac[2], argv[3]);
- strcpy(smac[3], argv[4]);
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
- return set_nor_arc_product(argc, argv);
-#endif
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
- return set_spi_arc_product(argc, argv);
-#endif
-#if (FWENV_TYPE == FWENV_MMC)
- return set_mmc_arc_product(argc, argv);
-#endif
- return -2;
-}
-
-static int read_arc_info(void)
-{
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
- return read_nor_arc_info();
-#endif
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
- return read_spi_arc_info();
-#endif
-#if (FWENV_TYPE == FWENV_MMC)
- return read_mmc_arc_info();
-#endif
- return 0;
-}
-
-static int do_get_arc_info(void)
-{
- int l = read_arc_info();
- char *oldserial = env_get("SERIAL");
- char *oldversion = env_get("VERSION");
-
- if (oldversion != NULL)
- if (strcmp(oldversion, U_BOOT_VERSION) != 0)
- oldversion = NULL;
-
- if (l == 0) {
- printf("%s: failed to read factory info\n", __func__);
- return -2;
- }
-
- printf("\rSERIAL: ");
- if (smac[0][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- printf("%s\n", smac[0]);
- env_set("SERIAL", smac[0]);
- }
-
- if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
- env_set("ethaddr", NULL);
- env_set("eth1addr", NULL);
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR0: ");
- if (smac[1][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("ethaddr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[1]);
- printf("%s\n", smac[1]);
- } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
- env_set("ethaddr", smac[1]);
- printf("%s (factory)\n", smac[1]);
- } else {
- printf("%s\n", ret);
- }
- }
-
- if (strcmp(smac[2], "00:00:00:00:00:00") == 0) {
- env_set("eth1addr", NULL);
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR1: ");
- if (smac[2][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("eth1addr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[2]);
- printf("%s\n", smac[2]);
- } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
- env_set("eth1addr", smac[2]);
- printf("%s (factory)\n", smac[2]);
- } else {
- printf("%s\n", ret);
- }
- }
-
- if (strcmp(smac[3], "00:00:00:00:00:00") == 0) {
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR2: ");
- if (smac[3][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("eth2addr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[3]);
- printf("%s\n", smac[3]);
- } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
- env_set("eth2addr", smac[3]);
- printf("%s (factory)\n", smac[3]);
- } else {
- printf("%s\n", ret);
- }
- }
-done:
- if (oldserial == NULL || oldversion == NULL) {
- if (oldversion == NULL)
- env_set("VERSION", U_BOOT_VERSION);
- env_save();
- }
-
- return 0;
-}
-
-static int init_fwenv(void)
-{
- int i, ret = -1;
-
- fwenv_addr[0] = FWENV_ADDR1;
- fwenv_addr[1] = FWENV_ADDR2;
- fwenv_addr[2] = FWENV_ADDR3;
- fwenv_addr[3] = FWENV_ADDR4;
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- ret = 0;
- if (ret)
- printf("%s: No firmfare info storage address is defined\n",
- __func__);
- return ret;
-}
-
-void get_arc_info(void)
-{
- if (!init_fwenv())
- do_get_arc_info();
-}
-
-static int do_arc_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- const char *cmd;
- int ret = -1;
-
- cmd = argv[1];
- --argc;
- ++argv;
-
- if (init_fwenv())
- return ret;
-
- if (strcmp(cmd, "product") == 0)
- ret = set_arc_product(argc, argv);
- else if (strcmp(cmd, "info") == 0)
- ret = do_get_arc_info();
-
- if (ret == -1)
- return CMD_RET_USAGE;
-
- return ret;
-}
-
-U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
- "Arcturus product command sub-system",
- "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
- "info - show Arcturus factory env\n\n");
diff --git a/board/Arcturus/ucp1020/ddr.c b/board/Arcturus/ucp1020/ddr.c
deleted file mode 100644
index a3285ebe5cd..00000000000
--- a/board/Arcturus/ucp1020/ddr.c
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
-/*
- * Micron MT41J128M16HA-15E
- * */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 536870912u,
- .capacity = 536870912u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1650,
- .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
- .taa_ps = 14050,
- .twr_ps = 15000,
- .trcd_ps = 13500,
- .trrd_ps = 75000,
- .trp_ps = 13500,
- .tras_ps = 40000,
- .trc_ps = 49500,
- .trfc_ps = 160000,
- .twtr_ps = 75000,
- .trtp_ps = 75000,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
-
-#else
-#error Missing raw timing data for this board
-#endif
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
-
-#ifdef CONFIG_SYS_DDR_CS0_BNDS
-/* Fixed sdram init -- doesn't use serial presence detect. */
-phys_size_t fixed_sdram(void)
-{
- sys_info_t sysinfo;
- char buf[32];
- size_t ddr_size;
- fsl_ddr_cfg_regs_t ddr_cfg_regs = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
-#endif
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
- .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
- };
-
- get_sys_info(&sysinfo);
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freq_ddrbus));
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return ddr_size;
-}
-#endif
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
-
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- if (pdimm->primary_sdram_width == 64)
- popts->data_bus_width = 0;
- else if (pdimm->primary_sdram_width == 32)
- popts->data_bus_width = 1;
- else
- printf("Error in DDR bus width configuration!\n");
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
diff --git a/board/Arcturus/ucp1020/law.c b/board/Arcturus/ucp1020/law.c
deleted file mode 100644
index cb53692a32b..00000000000
--- a/board/Arcturus/ucp1020/law.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_VSC7385_ENET
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#endif
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
deleted file mode 100644
index f7c4960da7c..00000000000
--- a/board/Arcturus/ucp1020/spl.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const u32 sysclk_tbl[] = {
- 66666000, 7499900, 83332500, 8999900,
- 99999000, 11111000, 12499800, 13333200
-};
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- gd->bus_clk = bus_clk;
-
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- struct bd_info *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(struct bd_info));
- gd->bd = bd;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
-
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
- gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#else
- env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C_LEGACY
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/Arcturus/ucp1020/spl_minimal.c
b/board/Arcturus/ucp1020/spl_minimal.c
deleted file mode 100644
index 90abec9cce5..00000000000
--- a/board/Arcturus/ucp1020/spl_minimal.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
- * original copyright follows:
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) &&
defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
-
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c
deleted file mode 100644
index 2c07df63e5b..00000000000
--- a/board/Arcturus/ucp1020/tlb.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/tlb.c
- * original copyright follows:
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI memory 1.5G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O effective: 192K */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#ifdef CONFIG_VSC7385_ENET
- /* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-#endif
-#endif /* not SPL */
-
-#ifdef CONFIG_SYS_NAND_BASE
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* *I*G - eSDHC/eSPI/NAND boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-
-#endif /* RAMBOOT/SPL */
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1)
-#endif
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/Arcturus/ucp1020/ucp1020.c
b/board/Arcturus/ucp1020/ucp1020.c
deleted file mode 100644
index 24d1d57ec4b..00000000000
--- a/board/Arcturus/ucp1020/ucp1020.c
+++ /dev/null
@@ -1,372 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * by Oleksandr G Zhadan et al.
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <ioports.h>
-#include <netdev.h>
-#include <micrel.h>
-#include <spi_flash.h>
-#include <mmc.h>
-#include <linux/ctype.h>
-#include <asm/fsl_serdes.h>
-#include <asm/gpio.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_lbc.h>
-#include <asm/mp.h>
-#include "ucp1020.h"
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- /* TO DO: It's actially have to be in spi/ */
-}
-
-/*
- * To be compatible with cmd_gpio
- */
-int name_to_gpio(const char *name)
-{
- int gpio = 31 - simple_strtoul(name, NULL, 10);
-
- if (gpio < 16)
- gpio = -1;
-
- return gpio;
-}
-
-void board_gpio_init(void)
-{
- int i;
- char envname[8], *val;
-
- for (i = 0; i < GPIO_MAX_NUM; i++) {
- sprintf(envname, "GPIO%d", i);
- val = env_get(envname);
- if (val) {
- char direction = toupper(val[0]);
- char level = toupper(val[1]);
-
- if (direction == 'I') {
- gpio_direction_input(i);
- } else {
- if (direction == 'O') {
- if (level == '1')
- gpio_direction_output(i, 1);
- else
- gpio_direction_output(i, 0);
- }
- }
- }
- }
-
- val = env_get("PCIE_OFF");
- if (val) {
- gpio_direction_input(GPIO_PCIE1_EN);
- gpio_direction_input(GPIO_PCIE2_EN);
- } else {
- gpio_direction_output(GPIO_PCIE1_EN, 1);
- gpio_direction_output(GPIO_PCIE2_EN, 1);
- }
-
- val = env_get("SDHC_CDWP_OFF");
- if (!val) {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
- }
-}
-
-int board_early_init_f(void)
-{
- return 0; /* Just in case. Could be disable in config file */
-}
-
-int checkboard(void)
-{
- printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
- board_gpio_init();
-#ifdef CONFIG_MMC
- printf("SD/MMC: 4-bit Mode\n");
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-#if defined(CONFIG_PHY_MICREL_KSZ9021)
- int regval;
- static int cnt;
-
- if (cnt++ == 0)
- printf("PHYs address [");
-
- if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
- regval =
- ksz9021_phy_extended_read(phydev,
- MII_KSZ9021_EXT_STRAP_STATUS);
- /*
- * min rx data delay
- */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x6666);
- /*
- * max rx/tx clock delay, min rx/tx control
- */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf6f6);
- printf("0x%x", (regval & 0x1f));
- } else {
- printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
- }
- if (cnt == 3)
- printf("] ");
- else
- printf(",");
-#endif
-
-#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
- regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
- if (regval >= 0)
- printf(" (ADDR 0x%x) ", regval & 0x1f);
-#endif
-
- return 0;
-}
-
-int last_stage_init(void)
-{
- static char newkernelargs[256];
- static u8 id1[16];
- static u8 id2;
-#ifdef CONFIG_MMC
- struct mmc *mmc;
-#endif
- char *sval, *kval;
-
- if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
- printf("Error reading i2c IDT6V49205B information!\n");
- } else {
- printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
- i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
- if (!(id1[1] & 0x02)) {
- id1[1] |= 0x02;
- i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
- asm("nop; nop");
- }
- }
-
- if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
- printf("Error reading i2c NCT72 information!\n");
- else
- printf("NCT72(0x%x): ready\n", id2);
-
- kval = env_get("kernelargs");
-
-#ifdef CONFIG_MMC
- mmc = find_mmc_device(0);
- if (mmc)
- if (!mmc_init(mmc)) {
- printf("MMC/SD card detected\n");
- if (kval) {
- int n = strlen(defkargs);
- char *tmp = strstr(kval, defkargs);
-
- *tmp = 0;
- strcpy(newkernelargs, kval);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, mmckargs);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, &tmp[n]);
- env_set("kernelargs", newkernelargs);
- } else {
- env_set("kernelargs", mmckargs);
- }
- }
-#endif
- get_arc_info();
-
- if (kval) {
- sval = env_get("SERIAL");
- if (sval) {
- strcpy(newkernelargs, "SN=");
- strcat(newkernelargs, sval);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, kval);
- env_set("kernelargs", newkernelargs);
- }
- } else {
- printf("Error reading kernelargs env variable!\n");
- }
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
-#ifdef CONFIG_TSEC2
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
- }
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
- const char *soc_usb_compat = "fsl-usb2-dr";
- int err, usb1_off, usb2_off;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- /* Delete eLBC node as it is muxed with USB2 controller */
- if (hwconfig("usb2")) {
- const char *soc_elbc_compat = "fsl,p1020-elbc";
- int off = fdt_node_offset_by_compatible(blob, -1,
- soc_elbc_compat);
- if (off < 0) {
- printf
- ("WARNING: could not find compatible node %s: %s\n",
- soc_elbc_compat, fdt_strerror(off));
- return off;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s\n",
- soc_elbc_compat, fdt_strerror(err));
- }
- return err;
- }
-#endif
-
-/* Delete USB2 node as it is muxed with eLBC */
- usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
- if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat, fdt_strerror(usb1_off));
- return usb1_off;
- }
- usb2_off =
- fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
- if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat, fdt_strerror(usb2_off));
- return usb2_off;
- }
- err = fdt_del_node(blob, usb2_off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_usb_compat, fdt_strerror(err));
- }
- return 0;
-}
-#endif
diff --git a/board/Arcturus/ucp1020/ucp1020.h
b/board/Arcturus/ucp1020/ucp1020.h
deleted file mode 100644
index 1b527cdb1cf..00000000000
--- a/board/Arcturus/ucp1020/ucp1020.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * by Oleksandr G Zhadan et al.
- */
-
-#ifndef __UCP1020_H__
-#define __UCP1020_H__
-
-#define GPIO0 31
-#define GPIO1 30
-#define GPIO2 29
-#define GPIO3 28
-#define GPIO4 27
-#define GPIO5 26
-#define GPIO6 25
-#define GPIO7 24
-#define GPIO8 23
-#define GPIO9 22
-#define GPIO10 21
-#define GPIO11 20
-#define GPIO12 19
-#define GPIO13 18
-#define GPIO14 17
-#define GPIO15 16
-#define GPIO_MAX_NUM 16
-
-#define GPIO_SDHC_CD GPIO8
-#define GPIO_SDHC_WP GPIO9
-#define GPIO_USB_PCTL0 GPIO10
-#define GPIO_PCIE1_EN GPIO11
-#define GPIO_PCIE2_EN GPIO10
-#define GPIO_USB_PCTL1 GPIO11
-
-#define GPIO_WD GPIO15
-
-#ifdef CONFIG_MMC
-static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
-static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
-#endif
-
-int get_arc_info(void);
-
-#endif
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
deleted file mode 100644
index 1fdb1952c8f..00000000000
--- a/configs/UCP1020_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF80000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_UCP1020=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to
stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="B$ "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_PCI is not set
-# CONFIG_CMD_SATA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_CRAMFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEC0C0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_FS_CRAMFS=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
deleted file mode 100644
index d9a777ea1a0..00000000000
--- a/include/configs/UCP1020.h
+++ /dev/null
@@ -1,832 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * based on include/configs/p1_p2_rdb_pc.h
- * original copyright follows:
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * QorIQ uCP1020-xx boards configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*** Arcturus FirmWare Environment */
-
-#define MAX_SERIAL_SIZE 15
-#define MAX_HWADDR_SIZE 17
-
-#define MAX_FWENV_ADDR 4
-
-#define FWENV_MMC 1
-#define FWENV_SPI_FLASH 2
-#define FWENV_NOR_FLASH 3
-/*
- #define FWENV_TYPE FWENV_MMC
- #define FWENV_TYPE FWENV_SPI_FLASH
-*/
-#define FWENV_TYPE FWENV_NOR_FLASH
-
-#if (FWENV_TYPE == FWENV_MMC)
-#define FWENV_ADDR1 -1
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0
-#endif
-
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
-#ifndef CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_SF_DEFAULT_SPEED 1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE0
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-#define CONFIG_SF_DEFAULT_CS 0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-#define CONFIG_SF_DEFAULT_BUS 0
-#endif
-#define FWENV_ADDR1 (0x200 - sizeof(smac))
-#define FWENV_ADDR2 (0x400 - sizeof(smac))
-#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
-#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
-#define EMPY_CHAR 0xff
-#endif
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
-#define FWENV_ADDR1 0xEC080000
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0xff
-#endif
-/***********************************/
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#if defined(CONFIG_TARTGET_UCP1020T1)
-
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
-#define CONFIG_IPADDR 10.80.41.229
-#define CONFIG_SERVERIP 10.80.41.227
-#define CONFIG_NETMASK 255.255.252.0
-#define CONFIG_ETHPRIME "eTSEC3"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#if defined(CONFIG_TARGET_UCP1020)
-
-#define CONFIG_UCP1020
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
-#define CONFIG_IPADDR 192.168.1.81
-#define CONFIG_IPADDR1 192.168.1.82
-#define CONFIG_IPADDR2 192.168.1.83
-#define CONFIG_SERVERIP 192.168.1.80
-#define CONFIG_GATEWAYIP 102.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in
the 4k
- SPL code*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* Default settings for DDR3 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#ifdef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
-#else
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#endif
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x40461520
-#define CONFIG_SYS_DDR_MODE_2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
- * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
- * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
- * (early boot only)
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-
-#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
-
-#define CONFIG_SYS_PMC_BASE 0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base
Addr */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
-
-#define CONFIG_RTC_DS1337
-#define CONFIG_RTC_DS1337_NOOSC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
-#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
-#define CONFIG_SYS_I2C_IDT6V49205B 0x69
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/*
- * Environment
- */
-#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Misc Extra Settings */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
-#else
-#error "UCP1020 module revision is not defined !!!"
-#endif
-
-#define CONFIG_BOOTP_SERVERIP
-
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 4
-#define TSEC2_PHY_ADDR 0
-#define TSEC2_PHY_ADDR_SGMII 0x00
-#define TSEC3_PHY_ADDR 6
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#endif
-
-#define CONFIG_HOSTNAME "UCP1020"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#if defined(CONFIG_DONGLE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run prog_spi_mbrbootcramfs\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020d.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"mmbr=uCP1020Quiet.mbr\0" \
-"mmcpart=0:2\0" \
-"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "mmc erase 1 1; " \
- "mmc write $loadaddr 1 1\0" \
-"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
- "mmc erase 0x40 0x400; " \
- "mmc write $loadaddr 0x40 0x400\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"prog_spi_mbr=run spi__mbr\0" \
-"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
-"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
- "run spi__cramfs\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeFF80000 +$filesize; " \
- "erase 0xEFF80000 +$filesize; " \
- "cp.b $loadaddr 0xEFF80000 $filesize; " \
- "cmp.b $loadaddr 0xEFF80000 $filesize; " \
- "protect on 0xeFF80000 +$filesize\0" \
-"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
- "sf probe 0; sf erase 0x8000 +$filesize; " \
- "sf write $loadaddr 0x8000 $filesize\0" \
-"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
- "protect off 0xec0a0000 +$filesize; " \
- "erase 0xeC0A0000 +$filesize; " \
- "cp.b $loadaddr 0xeC0A0000 $filesize; " \
- "protect on 0xec0a0000 +$filesize\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 1; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"ubootd=u-boot4dongle.bin\0" \
-"upgrade=run flashworking\0" \
-"usb_phy_type=ulpi\0 " \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else
-
-#if defined(CONFIG_UCP1020T1)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"othbootargs=quiet\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"silent=1\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashworking\0" \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else /* For Arcturus Modules */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run norkernel\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashuboot=tftp $loadaddr $ubootfile; " \
- "protect off $nor_ubootaddr0 +$filesize; " \
- "erase $nor_ubootaddr0 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
- "protect on $nor_ubootaddr0 +$filesize; " \
- "protect off $nor_ubootaddr1 +$filesize; " \
- "erase $nor_ubootaddr1 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
- "protect on $nor_ubootaddr1 +$filesize\0 " \
-"format0=protect off $part0base +$part0size; " \
- "erase $part0base +$part0size\0" \
-"format1=protect off $part1base +$part1size; " \
- "erase $part1base +$part1size\0" \
-"format2=protect off $part2base +$part2size; " \
- "erase $part2base +$part2size\0" \
-"format3=protect off $part3base +$part3size; " \
- "erase $part3base +$part3size\0" \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_ubootaddr0=0xEC000000\0" \
-"nor_ubootaddr1=0xEFF80000\0" \
-"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
- "run norkernelload; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $part0base; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"part0base=0xEC100000\0" \
-"part0size=0x00700000\0" \
-"part1base=0xEC800000\0" \
-"part1size=0x02000000\0" \
-"part2base=0xEE800000\0" \
-"part2size=0x00800000\0" \
-"part3base=0xEF000000\0" \
-"part3size=0x00F80000\0" \
-"partENVbase=0xEC080000\0" \
-"partENVsize=0x00080000\0" \
-"program0=tftp part0-000000.bin; " \
- "protect off $part0base +$filesize; " \
- "erase $part0base +$filesize; " \
- "cp.b $loadaddr $part0base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part0base $filesize\0" \
-"program1=tftp part1-000000.bin; " \
- "protect off $part1base +$filesize; " \
- "erase $part1base +$filesize; " \
- "cp.b $loadaddr $part1base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part1base $filesize\0" \
-"program2=tftp part2-000000.bin; " \
- "protect off $part2base +$filesize; " \
- "erase $part2base +$filesize; " \
- "cp.b $loadaddr $part2base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part2base $filesize\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashuboot\0" \
-"usb_phy_type=ulpi\0 " \
-"boot_nfs= " \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_hd = " \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_usb_fat = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "fatload usb 0:2 $loadaddr $bootfile;" \
- "fatload usb 0:2 $fdtaddr $fdtfile;" \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_usb_ext2 = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_nor = " \
- "setenv bootargs root=/dev/$jffs2nor rw " \
- "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
- "bootm $norbootaddr - $norfdtaddr\0 " \
-"boot_ram = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
-
-#endif
-#endif
-
-#endif /* __CONFIG_H */
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 02/32] ppc: Remove UCP1020 board
2021-08-02 0:54 ` [PATCH v2 02/32] ppc: Remove UCP1020 board Simon Glass
2021-08-02 3:00 ` Tom Rini
2021-09-13 18:46 ` Arcturus Support
@ 2021-09-14 1:02 ` Tom Rini
2 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-09-14 1:02 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six,
Oleksandr Zhadan and Michael Durrant, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 716 bytes --]
On Sun, Aug 01, 2021 at 06:54:15PM -0600, Simon Glass wrote:
> This board has not been converted to CONFIG_DM_PCI by the deadline.
> Remove it.
>
> Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt
> because it's not really migrated at this point.
>
> Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
> Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
> Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> [trini: Handle CONFIG_SPIFLASH differently and
> delete Kconfig file]
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 03/32] pci: Drop old code from header file
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
2021-08-02 0:54 ` [PATCH v2 01/32] pci: Drop old code from pci command Simon Glass
2021-08-02 0:54 ` [PATCH v2 02/32] ppc: Remove UCP1020 board Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-09-14 1:03 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 04/32] pci: Remove guard around compatibility functions Simon Glass
` (29 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
We don't need this code anymore since when PCI is enabled, driver model is
always used.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
include/pci.h | 60 +++------------------------------------------------
1 file changed, 3 insertions(+), 57 deletions(-)
diff --git a/include/pci.h b/include/pci.h
index 258c8f831ce..e07d6c31bc1 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -623,13 +623,9 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev
* about a small subset of PCI devices. This is normally false.
*/
struct pci_controller {
-#ifdef CONFIG_DM_PCI
struct udevice *bus;
struct udevice *ctlr;
bool skip_auto_config_until_reloc;
-#else
- struct pci_controller *next;
-#endif
int first_busno;
int last_busno;
@@ -655,54 +651,16 @@ struct pci_controller {
struct pci_config_table *config_table;
void (*fixup_irq)(struct pci_controller *, pci_dev_t);
-#ifndef CONFIG_DM_PCI
- /* Low-level architecture-dependent routines */
- int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
- int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
- int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
- int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
- int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
- int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
-#endif
/* Used by auto config */
struct pci_region *pci_mem, *pci_io, *pci_prefetch;
-
-#ifndef CONFIG_DM_PCI
- int current_busno;
-
- void *priv_data;
-#endif
};
-#ifndef CONFIG_DM_PCI
-static inline void pci_set_ops(struct pci_controller *hose,
- int (*read_byte)(struct pci_controller*,
- pci_dev_t, int where, u8 *),
- int (*read_word)(struct pci_controller*,
- pci_dev_t, int where, u16 *),
- int (*read_dword)(struct pci_controller*,
- pci_dev_t, int where, u32 *),
- int (*write_byte)(struct pci_controller*,
- pci_dev_t, int where, u8),
- int (*write_word)(struct pci_controller*,
- pci_dev_t, int where, u16),
- int (*write_dword)(struct pci_controller*,
- pci_dev_t, int where, u32)) {
- hose->read_byte = read_byte;
- hose->read_word = read_word;
- hose->read_dword = read_dword;
- hose->write_byte = write_byte;
- hose->write_word = write_word;
- hose->write_dword = write_dword;
-}
-#endif
-
#ifdef CONFIG_PCI_INDIRECT_BRIDGE
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
#endif
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+#if defined(CONFIG_DM_PCI_COMPAT)
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
@@ -752,15 +710,6 @@ extern int pci_hose_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u32 val);
#endif
-#ifndef CONFIG_DM_PCI
-extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
-extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
-extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
-extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
-extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
-extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
-#endif
-
void pciauto_region_init(struct pci_region *res);
void pciauto_region_align(struct pci_region *res, pci_size_t size);
void pciauto_config_init(struct pci_controller *hose);
@@ -780,7 +729,7 @@ void pciauto_config_init(struct pci_controller *hose);
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
pci_addr_t *bar, bool supports_64bit);
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+#if defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
@@ -827,7 +776,7 @@ int pci_find_next_ext_capability(struct pci_controller *hose,
int pci_hose_find_ext_capability(struct pci_controller *hose,
pci_dev_t dev, int cap);
-#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
+#endif /* defined(CONFIG_DM_PCI_COMPAT) */
const char * pci_class_str(u8 class);
int pci_last_busno(void);
@@ -890,7 +839,6 @@ enum pci_size_t {
struct udevice;
-#ifdef CONFIG_DM_PCI
/**
* struct pci_child_plat - information stored about each PCI device
*
@@ -1691,8 +1639,6 @@ int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
*/
extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
-#endif /* CONFIG_DM_PCI */
-
/**
* PCI_DEVICE - macro used to describe a specific pci device
* @vend: the 16 bit PCI Vendor ID
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 04/32] pci: Remove guard around compatibility functions
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (2 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 03/32] pci: Drop old code from header file Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 05/32] pci: Drop DM_PCI check from fdtdec Simon Glass
` (28 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
This prevents use of IS_ENABLED() in other files. Functions should be
visible in headers even if they are not available at link time.
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
include/pci.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/pci.h b/include/pci.h
index e07d6c31bc1..ca086420ff2 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -789,7 +789,6 @@ extern void pci_mpc85xx_init (struct pci_controller *hose);
extern void imx_pcie_remove(void);
#endif
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
/**
* pci_write_bar32() - Write the address of a BAR including control bits
*
@@ -797,6 +796,8 @@ extern void imx_pcie_remove(void);
* with devices which require hard-coded addresses, not part of the normal
* PCI enumeration process.
*
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
* @hose: PCI hose to use
* @dev: PCI device to update
* @barnum: BAR number (0-5)
@@ -808,6 +809,8 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
/**
* pci_read_bar32() - read the address of a bar
*
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
* @hose: PCI hose to use
* @dev: PCI device to inspect
* @barnum: BAR number (0-5)
@@ -818,6 +821,8 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
/**
* pci_hose_find_devices() - Find devices by vendor/device ID
*
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
* @hose: PCI hose to search
* @busnum: Bus number to search
* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
@@ -828,7 +833,6 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
*/
pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
struct pci_device_id *ids, int *indexp);
-#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
/* Access sizes for PCI reads and writes */
enum pci_size_t {
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 05/32] pci: Drop DM_PCI check from fdtdec
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (3 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 04/32] pci: Remove guard around compatibility functions Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-09-14 1:03 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 06/32] pci: Drop DM_PCI check from pci_common Simon Glass
` (27 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Sadly this doesn't work with nds32 for some reason to do with the
toolchain. Add a work-around for that.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
lib/fdtdec.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4b097fb588e..d12c6d340a0 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -192,7 +192,6 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name)
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
-#if CONFIG_IS_ENABLED(PCI) && defined(CONFIG_DM_PCI)
int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device)
{
const char *list, *end;
@@ -240,7 +239,15 @@ int fdtdec_get_pci_bar32(const struct udevice *dev, struct fdt_pci_addr *addr,
return -EINVAL;
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
+
+ /*
+ * There is a strange toolchain bug with nds32 which complains about
+ * an undefined reference here, even if fdtdec_get_pci_bar32() is never
+ * called. An #ifdef seems to be the only fix!
+ */
+#if !IS_ENABLED(CONFIG_NDS32)
*bar = dm_pci_read_bar32(dev, barnum);
+#endif
return 0;
}
@@ -260,7 +267,6 @@ int fdtdec_get_pci_bus_range(const void *blob, int node,
return 0;
}
-#endif
uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
uint64_t default_val)
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 06/32] pci: Drop DM_PCI check from pci_common
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (4 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 05/32] pci: Drop DM_PCI check from fdtdec Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 07/32] ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID Simon Glass
` (26 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/pci/pci_common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index 5231b69dc9a..02a71da30fa 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -99,7 +99,7 @@ __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
return 0;
}
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+#if defined(CONFIG_DM_PCI_COMPAT)
/* Get a virtual address associated with a BAR region */
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
@@ -361,4 +361,4 @@ pci_dev_t pci_find_class(uint find_class, int index)
return -ENODEV;
}
-#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
+#endif /* CONFIG_DM_PCI_COMPAT */
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 07/32] ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (5 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 06/32] pci: Drop DM_PCI check from pci_common Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 08/32] pci: powerpc: Drop old code Simon Glass
` (25 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
This is not used. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
include/configs/MPC8349EMDS.h | 1 -
include/configs/MPC8349EMDS_SDRAM.h | 1 -
include/configs/MPC837XERDB.h | 1 -
include/configs/MPC8540ADS.h | 1 -
include/configs/MPC8560ADS.h | 1 -
scripts/config_whitelist.txt | 1 -
6 files changed, 6 deletions(-)
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 4dad6a58ff5..d6ae419456a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -228,7 +228,6 @@
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index f7c13d417f8..8ebca99d98b 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -283,7 +283,6 @@
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index e16a5930ad8..0a136b4f92f 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -258,7 +258,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
/*
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index d843ba1ff78..ac9afa179a5 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -241,7 +241,6 @@
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 464e7c72844..02aeb6f3d53 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -238,7 +238,6 @@
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 812d8f2836f..17615226d5b 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2937,7 +2937,6 @@ CONFIG_SYS_PCI_NR_INBOUND_WIN
CONFIG_SYS_PCI_SLV_MEM_BUS
CONFIG_SYS_PCI_SLV_MEM_LOCAL
CONFIG_SYS_PCI_SLV_MEM_SIZE
-CONFIG_SYS_PCI_SUBSYS_VENDORID
CONFIG_SYS_PCI_SYS_MEM_BUS
CONFIG_SYS_PCI_SYS_MEM_PHYS
CONFIG_SYS_PCI_SYS_MEM_SIZE
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 07/32] ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID
2021-08-02 0:54 ` [PATCH v2 07/32] ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID Simon Glass
@ 2021-08-06 21:20 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:20 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 196 bytes --]
On Sun, Aug 01, 2021 at 06:54:20PM -0600, Simon Glass wrote:
> This is not used. Drop it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 08/32] pci: powerpc: Drop old code
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (6 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 07/32] ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 09/32] pci: freescale: " Simon Glass
` (24 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
Drop the old pre-driver model code from these drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/powerpc/cpu/mpc83xx/pci.c | 160 -------------------------
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/pci.c | 191 ------------------------------
3 files changed, 352 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/pci.c
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 507ab3417b3..65ef0497c2a 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -27,166 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
static struct pci_controller pci_hose[MAX_BUSES];
static int pci_num_buses;
-#if !defined(CONFIG_DM_PCI)
-static void pci_init_bus(int bus, struct pci_region *reg)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile pot83xx_t *pot = immr->ios.pot;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
- struct pci_controller *hose = &pci_hose[bus];
- u32 dev;
- u16 reg16;
- int i;
-
- if (bus == 1)
- pot += 3;
-
- /* Setup outbound translation windows */
- for (i = 0; i < 3; i++, reg++, pot++) {
- if (reg->size == 0)
- break;
-
- hose->regions[i] = *reg;
- hose->region_count++;
-
- pot->potar = reg->bus_start >> 12;
- pot->pobar = reg->phys_start >> 12;
- pot->pocmr = ~(reg->size - 1) >> 12;
-
- if (reg->flags & PCI_REGION_IO)
- pot->pocmr |= POCMR_IO;
-#ifdef CONFIG_83XX_PCI_STREAMING
- else if (reg->flags & PCI_REGION_PREFETCH)
- pot->pocmr |= POCMR_SE;
-#endif
-
- if (bus == 1)
- pot->pocmr |= POCMR_DST;
-
- pot->pocmr |= POCMR_EN;
- }
-
- /* Point inbound translation at RAM */
- pci_ctrl->pitar1 = 0;
- pci_ctrl->pibar1 = 0;
- pci_ctrl->piebar1 = 0;
- pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
-
- i = hose->region_count++;
- hose->regions[i].bus_start = 0;
- hose->regions[i].phys_start = 0;
- hose->regions[i].size = gd->ram_size;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
- hose->first_busno = pci_last_busno() + 1;
- hose->last_busno = 0xff;
-
- pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
- CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
-#ifndef CONFIG_PCISLAVE
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-
-/*
- * The caller must have already set OCCR, and the PCI_LAW BARs
- * must have been set to cover all of the requested regions.
- *
- * If fewer than three regions are requested, then the region
- * list is terminated with a region of size 0.
- */
-void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- int i;
-
- if (num_buses > MAX_BUSES) {
- printf("%d PCI buses requested, %d supported\n",
- num_buses, MAX_BUSES);
-
- num_buses = MAX_BUSES;
- }
-
- pci_num_buses = num_buses;
-
- /*
- * Release PCI RST Output signal.
- * Power on to RST high must be at least 100 ms as per PCI spec.
- * On warm boots only 1 ms is required, but we play it safe.
- */
- udelay(100000);
-
- for (i = 0; i < num_buses; i++)
- immr->pci_ctrl[i].gcr = 1;
-
- /*
- * RST high to first config access must be at least 2^25 cycles
- * as per PCI spec. This could be cut in half if we know we're
- * running at 66MHz. This could be insufficiently long if we're
- * running the PCI bus at significantly less than 33MHz.
- */
- udelay(1020000);
-
- for (i = 0; i < num_buses; i++)
- pci_init_bus(i, reg[i]);
-}
-
-#ifdef CONFIG_PCISLAVE
-
-#define PCI_FUNCTION_CONFIG 0x44
-#define PCI_FUNCTION_CFG_LOCK 0x20
-
-/*
- * Unlock the configuration bit so that the host system can begin booting
- *
- * This should be used after you have:
- * 1) Called mpc83xx_pci_init()
- * 2) Set up your inbound translation windows to the appropriate size
- */
-void mpc83xx_pcislave_unlock(int bus)
-{
- struct pci_controller *hose = &pci_hose[bus];
- u32 dev;
- u16 reg16;
-
- /* Unlock configuration lock in PCI function configuration register */
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
- reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
- pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
-
- /* The configuration bit is now unlocked, so we can scan the bus */
- hose->last_busno = pci_hose_scan(hose);
-}
-#endif
-#endif /* CONFIG_DM_PCI */
-
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, struct bd_info *bd)
{
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 993e4873184..15248a40824 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_CPM2) += ether_fcc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_CORENET) += liodn.o
obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
deleted file mode 100644
index b7835c0fee5..00000000000
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
- */
-
-/*
- * PCI Configuration space access support for MPC85xx PCI Bridge
- */
-#include <common.h>
-#include <asm/bitops.h>
-#include <asm/cpm_85xx.h>
-#include <pci.h>
-
-#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
-
-#ifndef CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI2_MEM_BUS
-#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI2_IO_BUS
-#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
-#endif
-
-static struct pci_controller *pci_hose;
-
-void
-pci_mpc85xx_init(struct pci_controller *board_hose)
-{
- u16 reg16;
- u32 dev;
-
- volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-#ifdef CONFIG_MPC85XX_PCI2
- volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
-#endif
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct pci_controller * hose;
-
- pci_hose = board_hose;
-
- hose = &pci_hose[0];
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8000),
- (CONFIG_SYS_IMMR+0x8004));
-
- /*
- * Hose scan.
- */
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
- /* PCI-X init */
- if (CONFIG_SYS_CLK_FREQ < 66000000)
- printf("PCI-X will only work at 66 MHz\n");
-
- reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
- | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
- }
-
- pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
- pcix->potear1 = 0x00000000;
- pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
- pcix->powbear1 = 0x00000000;
- pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
-
- pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
- pcix->potear2 = 0x00000000;
- pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
- pcix->powbear2 = 0x00000000;
- pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
-
- pcix->pitar1 = 0x00000000;
- pcix->piwbar1 = 0x00000000;
- pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
-
- pcix->powar3 = 0;
- pcix->powar4 = 0;
- pcix->piwar2 = 0;
- pcix->piwar3 = 0;
-
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 2;
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC85XX_PCI2
- hose = &pci_hose[1];
-
- hose->first_busno = pci_hose[0].last_busno + 1;
- hose->last_busno = 0xff;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x9000),
- (CONFIG_SYS_IMMR+0x9004));
-
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-
- pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
- pcix2->potear1 = 0x00000000;
- pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
- pcix2->powbear1 = 0x00000000;
- pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
-
- pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
- pcix2->potear2 = 0x00000000;
- pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
- pcix2->powbear2 = 0x00000000;
- pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
-
- pcix2->pitar1 = 0x00000000;
- pcix2->piwbar1 = 0x00000000;
- pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
-
- pcix2->powar3 = 0;
- pcix2->powar4 = 0;
- pcix2->piwar2 = 0;
- pcix2->piwar3 = 0;
-
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BUS,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_IO_BUS,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 2;
-
- /*
- * Hose scan.
- */
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-#endif /* !CONFIG_FSL_PCI_INIT */
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 08/32] pci: powerpc: Drop old code
2021-08-02 0:54 ` [PATCH v2 08/32] pci: powerpc: Drop old code Simon Glass
@ 2021-08-06 21:20 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:20 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 224 bytes --]
On Sun, Aug 01, 2021 at 06:54:21PM -0600, Simon Glass wrote:
> Drop the old pre-driver model code from these drivers.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 09/32] pci: freescale: Drop old code
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (7 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 08/32] pci: powerpc: Drop old code Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 10/32] pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci() Simon Glass
` (23 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
Drop this old pre-driver model code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
board/freescale/common/cds_pci_ft.c | 59 ----------
board/freescale/common/p_corenet/Makefile | 1 -
board/freescale/common/p_corenet/pci.c | 25 -----
board/freescale/mpc8548cds/mpc8548cds.c | 114 --------------------
board/freescale/p1010rdb/p1010rdb.c | 11 --
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 11 --
board/freescale/t102xrdb/Makefile | 1 -
board/freescale/t102xrdb/pci.c | 25 -----
board/freescale/t104xrdb/Makefile | 1 -
board/freescale/t104xrdb/pci.c | 25 -----
board/freescale/t208xqds/Makefile | 1 -
board/freescale/t208xqds/pci.c | 25 -----
board/freescale/t208xrdb/Makefile | 1 -
board/freescale/t208xrdb/pci.c | 25 -----
board/freescale/t4rdb/Makefile | 1 -
board/freescale/t4rdb/pci.c | 25 -----
16 files changed, 351 deletions(-)
delete mode 100644 board/freescale/common/p_corenet/pci.c
delete mode 100644 board/freescale/t102xrdb/pci.c
delete mode 100644 board/freescale/t104xrdb/pci.c
delete mode 100644 board/freescale/t208xqds/pci.c
delete mode 100644 board/freescale/t208xrdb/pci.c
delete mode 100644 board/freescale/t4rdb/pci.c
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index be97a28ed25..dc2d62850d1 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -9,68 +9,9 @@
#include "cadmus.h"
#if defined(CONFIG_OF_BOARD_SETUP)
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-static void cds_pci_fixup(void *blob)
-{
- int node;
- const char *path;
- int len, slot, i;
- u32 *map = NULL, *piccells = NULL;
- int off, cells;
-
- node = fdt_path_offset(blob, "/aliases");
- if (node >= 0) {
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- node = fdt_path_offset(blob, path);
- if (node >= 0) {
- map = fdt_getprop_w(blob, node, "interrupt-map", &len);
- }
- /* Each item in "interrupt-map" property is translated with
- * following cells:
- * PCI #address-cells, PCI #interrupt-cells,
- * PIC address, PIC #address-cells, PIC #interrupt-cells.
- */
- cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1);
- cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1);
- off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells)));
- if (off <= 0)
- return;
- cells += 1;
- piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL);
- if (piccells == NULL)
- return;
- cells += *piccells;
- piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL);
- if (piccells == NULL)
- return;
- cells += *piccells;
- }
- }
-
- if (map) {
- len /= sizeof(u32);
-
- slot = get_pci_slot();
-
- for (i=0;i<len;i+=cells) {
- /* We rotate the interrupt pins so that the mapping
- * changes depending on the slot the carrier card is in.
- */
- map[3] = ((map[3] + slot - 2) % 4) + 1;
- map+=cells;
- }
- }
-}
-#endif
-
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
- ft_pci_setup(blob, bd);
- cds_pci_fixup(blob);
-#endif
return 0;
}
diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile
index 29c9d544ae5..ce156018a06 100644
--- a/board/freescale/common/p_corenet/Makefile
+++ b/board/freescale/common/p_corenet/Makefile
@@ -4,5 +4,4 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += law.o
-obj-$(CONFIG_PCI) += pci.o
obj-y += tlb.o
diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c
deleted file mode 100644
index 636334863e1..00000000000
--- a/board/freescale/common/p_corenet/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index a1a9742bfa4..cfb5b0b38bb 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -168,113 +168,6 @@ void lbc_sdram_init(void)
#endif /* enable SDRAM init */
}
-#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI */
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr, io_sel;
- u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
- int first_free_busno = 0;
- char buf[32];
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- porpllsr = in_be32(&gur->porpllsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-#ifdef CONFIG_PCI1
- pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
- pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
- pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
- (pci_32) ? 32 : 64,
- strmhz(buf, pci_speed),
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter",
- pci_info.regs);
-
- pci1_hose.config_table = pci_mpc85xxcds_config_table;
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
-
-#ifdef CONFIG_PCIX_CHECK
- if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
- /* PCI-X init */
- if (CONFIG_SYS_CLK_FREQ < 66000000)
- printf("PCI-X will only work at 66 MHz\n");
-
- reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
- | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
- }
-#endif
- } else {
- printf("PCI1: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-
-#ifdef CONFIG_PCI2
-{
- uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- if (pci_dual) {
- printf("PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf("PCI2: disabled\n");
- }
-}
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
-#endif /* CONFIG_PCI2 */
-
- fsl_pcie_init_board(first_free_busno);
-}
-#endif
-
void configure_rgmii(void)
{
unsigned short temp;
@@ -354,10 +247,3 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
-
-#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
-void ft_pci_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 90436337df1..84fc891b67c 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -129,13 +129,6 @@ int board_early_init_r(void)
return 0;
}
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
int config_board_mux(int ctrl_type)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -617,10 +610,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
base = env_get_bootm_low();
size = env_get_bootm_size();
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
- FT_FSL_PCI_SETUP;
-#endif
-
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 8273384f2d5..fb9bf795e30 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -239,13 +239,6 @@ int checkboard(void)
return 0;
}
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@@ -363,10 +356,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
-#if !defined(CONFIG_DM_PCI)
- FT_FSL_PCI_SETUP;
-#endif
-
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
sizeof("okay"), 0);
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index ddeb44f36e2..e597486c940 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -10,7 +10,6 @@ else
obj-y += t102xrdb.o
obj-$(CONFIG_TARGET_T1024RDB) += cpld.o
obj-y += eth_t102xrdb.o
-obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
deleted file mode 100644
index 45ab9223ae1..00000000000
--- a/board/freescale/t102xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
index 31abbd9aca0..d67e9412ecd 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -8,7 +8,6 @@ else
obj-y += t104xrdb.o
obj-y += cpld.o
obj-y += eth.o
-obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_FSL_DIU_FB)+= diu.o
endif
obj-y += ddr.o
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
deleted file mode 100644
index 1fd24027000..00000000000
--- a/board/freescale/t104xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index 55b1e7390a0..de8613058de 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
deleted file mode 100644
index a03b11ccb50..00000000000
--- a/board/freescale/t208xqds/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index 25ea66a0248..7af3cd0ac4c 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
-obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
deleted file mode 100644
index 45ab9223ae1..00000000000
--- a/board/freescale/t208xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index f1fd623339c..3106848639c 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -10,7 +10,6 @@ else
obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
obj-y += cpld.o
obj-y += eth.o
-obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
deleted file mode 100644
index c2bc05164dd..00000000000
--- a/board/freescale/t4rdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 10/32] pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci()
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (8 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 09/32] pci: freescale: " Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 11/32] ppc: Drop DM_PCI from config files Simon Glass
` (22 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass, Marek Vasut, Pavel Herrmann
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/core/fdtaddr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index b9874c743d1..4ffbd6b2ebc 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -200,8 +200,7 @@ fdt_addr_t devfdt_get_addr_pci(const struct udevice *dev)
ulong addr;
addr = devfdt_get_addr(dev);
- if (CONFIG_IS_ENABLED(PCI) && IS_ENABLED(CONFIG_DM_PCI) &&
- addr == FDT_ADDR_T_NONE) {
+ if (CONFIG_IS_ENABLED(PCI) && addr == FDT_ADDR_T_NONE) {
struct fdt_pci_addr pci_addr;
u32 bar;
int ret;
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 10/32] pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci()
2021-08-02 0:54 ` [PATCH v2 10/32] pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci() Simon Glass
@ 2021-08-06 21:20 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:20 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Marek Vasut, Pavel Herrmann
[-- Attachment #1: Type: text/plain, Size: 261 bytes --]
On Sun, Aug 01, 2021 at 06:54:23PM -0600, Simon Glass wrote:
> We don't need this check anymore since when PCI is enabled, driver model
> is always used.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 11/32] ppc: Drop DM_PCI from config files
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (9 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 10/32] pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci() Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:20 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 12/32] pci: acpi: Drop DM_PCI check from ahci Simon Glass
` (21 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
include/configs/MPC8548CDS.h | 16 ----------------
include/configs/P1010RDB.h | 28 ----------------------------
include/configs/P2041RDB.h | 17 -----------------
include/configs/T102xRDB.h | 17 -----------------
include/configs/T104xRDB.h | 20 --------------------
include/configs/T208xQDS.h | 20 --------------------
include/configs/T208xRDB.h | 20 --------------------
include/configs/T4240RDB.h | 21 ---------------------
include/configs/corenet_ds.h | 21 ---------------------
include/configs/p1_p2_rdb_pc.h | 24 ------------------------
10 files changed, 204 deletions(-)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 2046bf215b2..d8e57fd0997 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -371,23 +371,7 @@ extern unsigned long get_clock_freq(void);
#endif
#if defined(CONFIG_PCI)
-
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1
-#define CONFIG_SYS_PCIE1_NAME "Slot"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f5209e17964..b7e44d17373 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -150,34 +150,6 @@
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
-#endif
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b5b159406a4..4ef061343c1 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -417,23 +417,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 1b4720db5c8..187304419e6 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -487,23 +487,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#endif
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 57a0bf5287e..fb215bb05fb 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -537,26 +537,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#endif
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b8d1693017e..f61b40fb3bd 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -486,26 +486,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index a04a49d0339..63cc5af2c6d 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -435,26 +435,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index aa185be7411..57a39fa970f 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -196,27 +196,6 @@
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 924093e6b05..c877f3c725e 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -430,27 +430,6 @@
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ba5b649b971..54c82b4f335 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -529,30 +529,6 @@
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
#endif
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 11/32] ppc: Drop DM_PCI from config files
2021-08-02 0:54 ` [PATCH v2 11/32] ppc: Drop DM_PCI from config files Simon Glass
@ 2021-08-06 21:20 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:20 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 253 bytes --]
On Sun, Aug 01, 2021 at 06:54:24PM -0600, Simon Glass wrote:
> Now that DM_PCI is always enabled we don't need to check it. Drop this
> old code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 12/32] pci: acpi: Drop DM_PCI check from ahci
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (10 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 11/32] ppc: Drop DM_PCI from config files Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-09-14 1:03 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 13/32] pci: usb: Drop DM_PCI from ohci Simon Glass
` (20 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
We don't need these checks anymore since when PCI is enabled, driver model
is always used.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/ata/ahci.c | 55 ----------------------------------------------
include/ahci.h | 4 ----
2 files changed, 59 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index d4047c04f5d..2062197afcd 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -170,13 +170,8 @@ int ahci_reset(void __iomem *base)
static int ahci_host_init(struct ahci_uc_priv *uc_priv)
{
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
-# ifdef CONFIG_DM_PCI
struct udevice *dev = uc_priv->dev;
struct pci_child_plat *pplat = dev_get_parent_plat(dev);
-# else
- pci_dev_t pdev = uc_priv->dev;
- unsigned short vendor;
-# endif
u16 tmp16;
#endif
void __iomem *mmio = uc_priv->mmio_base;
@@ -200,23 +195,12 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
-# ifdef CONFIG_DM_PCI
if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
u16 tmp16;
dm_pci_read_config16(dev, 0x92, &tmp16);
dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
}
-# else
- pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
-
- if (vendor == PCI_VENDOR_ID_INTEL) {
- u16 tmp16;
- pci_read_config_word(pdev, 0x92, &tmp16);
- tmp16 |= 0xf;
- pci_write_config_word(pdev, 0x92, tmp16);
- }
-# endif
#endif
uc_priv->cap = readl(mmio + HOST_CAP);
uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
@@ -331,15 +315,9 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
debug("HOST_CTL 0x%x\n", tmp);
#if !defined(CONFIG_DM_SCSI)
#ifndef CONFIG_SCSI_AHCI_PLAT
-# ifdef CONFIG_DM_PCI
dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
tmp |= PCI_COMMAND_MASTER;
dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
-# else
- pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
- tmp |= PCI_COMMAND_MASTER;
- pci_write_config_word(pdev, PCI_COMMAND, tmp16);
-# endif
#endif
#endif
return 0;
@@ -349,11 +327,7 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
static void ahci_print_info(struct ahci_uc_priv *uc_priv)
{
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
-# if defined(CONFIG_DM_PCI)
struct udevice *dev = uc_priv->dev;
-# else
- pci_dev_t pdev = uc_priv->dev;
-# endif
u16 cc;
#endif
void __iomem *mmio = uc_priv->mmio_base;
@@ -379,11 +353,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv)
#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
scc_s = "SATA";
#else
-# ifdef CONFIG_DM_PCI
dm_pci_read_config16(dev, 0x0a, &cc);
-# else
- pci_read_config_word(pdev, 0x0a, &cc);
-# endif
if (cc == 0x0101)
scc_s = "IDE";
else if (cc == 0x0106)
@@ -428,11 +398,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv)
}
#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
-# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
-# else
-static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
-# endif
{
#if !defined(CONFIG_DM_SCSI)
u16 vendor;
@@ -450,7 +416,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
#if !defined(CONFIG_DM_SCSI)
-#ifdef CONFIG_DM_PCI
uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
@@ -461,18 +426,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
if (vendor == 0x197b)
dm_pci_write_config8(dev, 0x41, 0xa1);
-#else
- uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
- PCI_REGION_MEM);
-
- /* Take from kernel:
- * JMicron-specific fixup:
- * make sure we're in AHCI mode
- */
- pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
- if (vendor == 0x197b)
- pci_write_config_byte(dev, 0x41, 0xa1);
-#endif
#else
struct scsi_plat *plat = dev_get_uclass_plat(dev);
uc_priv->mmio_base = (void *)plat->base;
@@ -1006,7 +959,6 @@ void scsi_low_level_init(int busdevfunc)
return;
}
uc_priv = probe_ent;
-# if defined(CONFIG_DM_PCI)
struct udevice *dev;
int ret;
@@ -1014,9 +966,6 @@ void scsi_low_level_init(int busdevfunc)
if (ret)
return;
ahci_init_one(uc_priv, dev);
-# else
- ahci_init_one(uc_priv, busdevfunc);
-# endif
#else
uc_priv = probe_ent;
#endif
@@ -1026,7 +975,6 @@ void scsi_low_level_init(int busdevfunc)
#endif
#ifndef CONFIG_SCSI_AHCI_PLAT
-# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
int ahci_init_one_dm(struct udevice *dev)
{
struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -1034,7 +982,6 @@ int ahci_init_one_dm(struct udevice *dev)
return ahci_init_one(uc_priv, dev);
}
#endif
-#endif
int ahci_start_ports_dm(struct udevice *dev)
{
@@ -1196,7 +1143,6 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
return 0;
}
-#ifdef CONFIG_DM_PCI
int ahci_probe_scsi_pci(struct udevice *ahci_dev)
{
ulong base;
@@ -1221,7 +1167,6 @@ int ahci_probe_scsi_pci(struct udevice *ahci_dev)
PCI_REGION_MEM);
return ahci_probe_scsi(ahci_dev, base);
}
-#endif
struct scsi_ops scsi_ops = {
.exec = ahci_scsi_exec,
diff --git a/include/ahci.h b/include/ahci.h
index fb96dd88611..d5453042d15 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -148,16 +148,12 @@ struct ahci_ioports {
* where dev is the controller (although at present it sometimes stands alone).
*/
struct ahci_uc_priv {
-#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
/*
* TODO(sjg@chromium.org): Drop this once this structure is only used
* in a driver-model context (i.e. attached to a device with
* dev_get_uclass_priv()
*/
struct udevice *dev;
-#else
- pci_dev_t dev;
-#endif
struct ahci_ioports port[AHCI_MAX_PORTS];
u16 *ataid[AHCI_MAX_PORTS];
u32 n_ports;
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 13/32] pci: usb: Drop DM_PCI from ohci
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (11 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 12/32] pci: acpi: Drop DM_PCI check from ahci Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-05 23:44 ` Tom Rini
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 14/32] ppc: malta: Drop use of DM_PCI Simon Glass
` (19 subsequent siblings)
32 siblings, 2 replies; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass, Marek Vasut
Now that DM_PCI is always enabled we don't need to check it. Drop this
old condition and update the comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/usb/host/ohci-hcd.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index c62d8feecce..7fa84f8bbe4 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -52,13 +52,6 @@
#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
#endif
-#if defined(CONFIG_CPU_ARM920T) || \
- defined(CONFIG_PCI_OHCI) || \
- defined(CONFIG_DM_PCI) || \
- defined(CONFIG_SYS_OHCI_USE_NPS)
-# define OHCI_USE_NPS /* force NoPowerSwitching mode */
-#endif
-
#undef OHCI_VERBOSE_DEBUG /* not always helpful */
#undef DEBUG
#undef SHOW_INFO
@@ -1885,12 +1878,14 @@ static int hc_start(ohci_t *ohci)
mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
ohci_writel(mask, &ohci->regs->intrenable);
-#ifdef OHCI_USE_NPS
- /* required for AMD-756 and some Mac platforms */
+ /*
+ * required for AMD-756 and some Mac platforms
+ * Note: this is always enabled at present, since driver model is used
+ * for PCI
+ */
ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
&ohci->regs->roothub.a);
ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
/* connect the virtual root hub */
ohci->rh.devnum = 0;
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 13/32] pci: usb: Drop DM_PCI from ohci
2021-08-02 0:54 ` [PATCH v2 13/32] pci: usb: Drop DM_PCI from ohci Simon Glass
@ 2021-08-05 23:44 ` Tom Rini
2021-08-06 21:21 ` Tom Rini
1 sibling, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-05 23:44 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Marek Vasut
[-- Attachment #1: Type: text/plain, Size: 1827 bytes --]
On Sun, Aug 01, 2021 at 06:54:26PM -0600, Simon Glass wrote:
> Now that DM_PCI is always enabled we don't need to check it. Drop this
> old condition and update the comment.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
> drivers/usb/host/ohci-hcd.c | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
> index c62d8feecce..7fa84f8bbe4 100644
> --- a/drivers/usb/host/ohci-hcd.c
> +++ b/drivers/usb/host/ohci-hcd.c
> @@ -52,13 +52,6 @@
> #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
> #endif
>
> -#if defined(CONFIG_CPU_ARM920T) || \
> - defined(CONFIG_PCI_OHCI) || \
> - defined(CONFIG_DM_PCI) || \
> - defined(CONFIG_SYS_OHCI_USE_NPS)
> -# define OHCI_USE_NPS /* force NoPowerSwitching mode */
> -#endif
> -
> #undef OHCI_VERBOSE_DEBUG /* not always helpful */
> #undef DEBUG
> #undef SHOW_INFO
> @@ -1885,12 +1878,14 @@ static int hc_start(ohci_t *ohci)
> mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
> ohci_writel(mask, &ohci->regs->intrenable);
>
> -#ifdef OHCI_USE_NPS
> - /* required for AMD-756 and some Mac platforms */
> + /*
> + * required for AMD-756 and some Mac platforms
> + * Note: this is always enabled at present, since driver model is used
> + * for PCI
> + */
> ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
> &ohci->regs->roothub.a);
> ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
> -#endif /* OHCI_USE_NPS */
>
> /* connect the virtual root hub */
> ohci->rh.devnum = 0;
This is slightly wrong. We have non-PCI OHCI users, so the check needs
to change from CONFIG_DM_PCI to CONFIG_PCI. I'll fix this up.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 13/32] pci: usb: Drop DM_PCI from ohci
2021-08-02 0:54 ` [PATCH v2 13/32] pci: usb: Drop DM_PCI from ohci Simon Glass
2021-08-05 23:44 ` Tom Rini
@ 2021-08-06 21:21 ` Tom Rini
1 sibling, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:21 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Marek Vasut
[-- Attachment #1: Type: text/plain, Size: 303 bytes --]
On Sun, Aug 01, 2021 at 06:54:26PM -0600, Simon Glass wrote:
> Now that DM_PCI is always enabled we don't need to check it. Drop this
> old condition and update the comment.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
With the fix I noted, applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 14/32] ppc: malta: Drop use of DM_PCI
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (12 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 13/32] pci: usb: Drop DM_PCI from ohci Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 15/32] ppc: socrates: " Simon Glass
` (18 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Fix tag to 'mips' from 'ppc'
board/imgtec/malta/malta.c | 67 --------------------------------------
1 file changed, 67 deletions(-)
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 9af1f92e5db..d2e2e4ae209 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -196,7 +196,6 @@ int board_fix_fdt(void *rw_fdt_blob)
}
#endif
-#if IS_ENABLED(CONFIG_DM_PCI)
int board_early_init_r(void)
{
struct udevice *dev;
@@ -243,69 +242,3 @@ int board_early_init_r(void)
return 0;
}
-#else
-void pci_init_board(void)
-{
- pci_dev_t bdf;
- u32 val32;
- u8 val8;
-
- switch (malta_sys_con()) {
- case SYSCON_GT64120:
- gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- 0x10000000, 0x10000000, 128 * 1024 * 1024,
- 0x00000000, 0x00000000, 0x20000);
- break;
-
- default:
- case SYSCON_MSC01:
- msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- MALTA_MSC01_PCIMEM_MAP,
- CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
- MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
- 0x00000000, MALTA_MSC01_PCIIO_SIZE);
- break;
- }
-
- bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82371AB_0, 0);
- if (bdf == -1)
- panic("Failed to find PIIX4 PCI bridge\n");
-
- /* setup PCI interrupt routing */
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
-
- /* mux SERIRQ onto SERIRQ pin */
- pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
- val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
-
- /* enable SERIRQ - Linux currently depends upon this */
- pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
- val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
-
- bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82371AB, 0);
- if (bdf == -1)
- panic("Failed to find PIIX4 IDE controller\n");
-
- /* enable bus master & IO access */
- val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
- pci_write_config_dword(bdf, PCI_COMMAND, val32);
-
- /* set latency */
- pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
-
- /* enable IDE/ATA */
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
- PCI_CFG_PIIX4_IDETIM_IDE);
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
- PCI_CFG_PIIX4_IDETIM_IDE);
-}
-#endif
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 14/32] ppc: malta: Drop use of DM_PCI
2021-08-02 0:54 ` [PATCH v2 14/32] ppc: malta: Drop use of DM_PCI Simon Glass
@ 2021-08-06 21:21 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:21 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 253 bytes --]
On Sun, Aug 01, 2021 at 06:54:27PM -0600, Simon Glass wrote:
> Now that DM_PCI is always enabled we don't need to check it. Drop this
> old code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 15/32] ppc: socrates: Drop use of DM_PCI
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (13 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 14/32] ppc: malta: Drop use of DM_PCI Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 16/32] pci: gt64120: " Simon Glass
` (17 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
board/socrates/socrates.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 3444af6a8c7..3ba2fbbd560 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -53,7 +53,7 @@ int checkboard (void)
}
putc('\n');
-#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
+#if defined(CONFIG_PCI)
/* Check the PCI_clk sel bit */
if (in_be32(&gur->porpllsr) & (1<<15)) {
src = "SYSCLK";
@@ -130,9 +130,7 @@ int misc_init_r (void)
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
}
-#if defined(CONFIG_DM_PCI)
pci_init();
-#endif
return 0;
}
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 15/32] ppc: socrates: Drop use of DM_PCI
2021-08-02 0:54 ` [PATCH v2 15/32] ppc: socrates: " Simon Glass
@ 2021-08-06 21:21 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:21 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 253 bytes --]
On Sun, Aug 01, 2021 at 06:54:28PM -0600, Simon Glass wrote:
> Now that DM_PCI is always enabled we don't need to check it. Drop this
> old code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 16/32] pci: gt64120: Drop use of DM_PCI
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (14 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 15/32] ppc: socrates: " Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 17/32] pci: msc01: " Simon Glass
` (16 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/pci/pci_gt64120.c | 64 ---------------------------------------
1 file changed, 64 deletions(-)
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index e57fedf036e..153c65b119a 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -114,69 +114,6 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
return 0;
}
-#if !IS_ENABLED(CONFIG_DM_PCI)
-static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 *value)
-{
- struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
-
- *value = 0xffffffff;
- return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
-}
-
-static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 value)
-{
- struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
- u32 data = value;
-
- return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
-}
-
-void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
- unsigned long sys_size, unsigned long mem_bus,
- unsigned long mem_phys, unsigned long mem_size,
- unsigned long io_bus, unsigned long io_phys,
- unsigned long io_size)
-{
- static struct gt64120_pci_controller global_gt;
- struct gt64120_pci_controller *gt;
- struct pci_controller *hose;
-
- gt = &global_gt;
- gt->regs = regs;
-
- hose = >->hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* System memory space */
- pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-}
-#else
static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint where, ulong *val,
enum pci_size_t size)
@@ -246,4 +183,3 @@ U_BOOT_DRIVER(gt64120_pci) = {
.probe = gt64120_pci_probe,
.priv_auto = sizeof(struct gt64120_pci_controller),
};
-#endif
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 17/32] pci: msc01: Drop use of DM_PCI
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (15 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 16/32] pci: gt64120: " Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 18/32] pci: imx: " Simon Glass
` (15 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/pci/pci_msc01.c | 64 -----------------------------------------
1 file changed, 64 deletions(-)
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index c17da475d01..2f1b688fc32 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -62,69 +62,6 @@ static int msc01_config_access(struct msc01_pci_controller *msc01,
return 0;
}
-#if !IS_ENABLED(CONFIG_DM_PCI)
-static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 *value)
-{
- struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
-
- *value = 0xffffffff;
- return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
-}
-
-static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 value)
-{
- struct msc01_pci_controller *gt = hose_to_msc01(hose);
- u32 data = value;
-
- return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
-}
-
-void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
- unsigned long sys_size, unsigned long mem_bus,
- unsigned long mem_phys, unsigned long mem_size,
- unsigned long io_bus, unsigned long io_phys,
- unsigned long io_size)
-{
- static struct msc01_pci_controller global_msc01;
- struct msc01_pci_controller *msc01;
- struct pci_controller *hose;
-
- msc01 = &global_msc01;
- msc01->base = base;
-
- hose = &msc01->hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* System memory space */
- pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- msc01_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- msc01_write_config_dword);
-
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-}
-#else
static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint where, ulong *val, enum pci_size_t size)
{
@@ -192,4 +129,3 @@ U_BOOT_DRIVER(msc01_pci) = {
.probe = msc01_pci_probe,
.priv_auto = sizeof(struct msc01_pci_controller),
};
-#endif
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 18/32] pci: imx: Drop use of DM_PCI
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (16 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 17/32] pci: msc01: " Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 19/32] pci: scsi: pci: Drop DM_PCI check from scsi Simon Glass
` (14 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass, Stefano Babic
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/pci/pcie_imx.c | 81 ------------------------------------------
1 file changed, 81 deletions(-)
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 7b46fdb89a3..756166fd3ea 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -681,86 +681,6 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv)
return 0;
}
-#if !CONFIG_IS_ENABLED(DM_PCI)
-static struct imx_pcie_priv imx_pcie_priv = {
- .dbi_base = (void __iomem *)MX6_DBI_ADDR,
- .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
-};
-
-static struct imx_pcie_priv *priv = &imx_pcie_priv;
-
-static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
- int where, u32 *val)
-{
- struct imx_pcie_priv *priv = hose->priv_data;
-
- return imx_pcie_read_cfg(priv, d, where, val);
-}
-
-static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
- int where, u32 val)
-{
- struct imx_pcie_priv *priv = hose->priv_data;
-
- return imx_pcie_write_cfg(priv, d, where, val);
-}
-
-void imx_pcie_init(void)
-{
- /* Static instance of the controller. */
- static struct pci_controller pcc;
- struct pci_controller *hose = &pcc;
- int ret;
-
- memset(&pcc, 0, sizeof(pcc));
-
- hose->priv_data = priv;
-
- /* PCI I/O space */
- pci_set_region(&hose->regions[0],
- MX6_IO_ADDR, MX6_IO_ADDR,
- MX6_IO_SIZE, PCI_REGION_IO);
-
- /* PCI memory space */
- pci_set_region(&hose->regions[1],
- MX6_MEM_ADDR, MX6_MEM_ADDR,
- MX6_MEM_SIZE, PCI_REGION_MEM);
-
- /* System memory space */
- pci_set_region(&hose->regions[2],
- MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
- 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 3;
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- imx_pcie_read_config,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- imx_pcie_write_config);
-
- /* Start the controller. */
- ret = imx_pcie_link_up(priv);
-
- if (!ret) {
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
- }
-}
-
-void imx_pcie_remove(void)
-{
- imx6_pcie_assert_core_reset(priv, true);
-}
-
-/* Probe function. */
-void pci_init_board(void)
-{
- imx_pcie_init();
-}
-#else
static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
uint offset, ulong *value,
enum pci_size_t size)
@@ -852,4 +772,3 @@ U_BOOT_DRIVER(imx_pcie) = {
.priv_auto = sizeof(struct imx_pcie_priv),
.flags = DM_FLAG_OS_PREPARE,
};
-#endif
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 19/32] pci: scsi: pci: Drop DM_PCI check from scsi
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (17 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 18/32] pci: imx: " Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 20/32] pci: Drop DM_PCI check from bios_emul Simon Glass
` (13 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass, Rob Herring
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/scsi/scsi.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index ce69750c7ff..d93d2419285 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -284,7 +284,6 @@ void scsi_init(void)
*/
for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
/* get PCI Device ID */
-#ifdef CONFIG_DM_PCI
struct udevice *dev;
int ret;
@@ -294,11 +293,6 @@ void scsi_init(void)
busdevfunc = dm_pci_get_bdf(dev);
break;
}
-#else
- busdevfunc = pci_find_device(scsi_device_list[i].vendor,
- scsi_device_list[i].device,
- 0);
-#endif
if (busdevfunc != -1)
break;
}
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 20/32] pci: Drop DM_PCI check from bios_emul
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (18 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 19/32] pci: scsi: pci: Drop DM_PCI check from scsi Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 21/32] net: Drop DM_PCI check from designware driver Simon Glass
` (12 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
We don't need these checks anymore since when PCI is enabled, driver model
is always used.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/bios_emulator/atibios.c | 98 ---------------------------------
drivers/bios_emulator/bios.c | 39 -------------
include/bios_emul.h | 16 ------
3 files changed, 153 deletions(-)
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 6c7cc24cbd9..9547470a2f7 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -230,19 +230,12 @@ This function executes the BIOS POST code on the controller. We assume that
at this stage the controller has its I/O and memory space enabled and
that all other controllers are in a disabled state.
****************************************************************************/
-#ifdef CONFIG_DM_PCI
static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info,
int vesa_mode, struct vbe_mode_info *mode_info)
-#else
-static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
- int vesa_mode, struct vbe_mode_info *mode_info)
-#endif
{
RMREGS regs;
RMSREGS sregs;
-#ifdef CONFIG_DM_PCI
pci_dev_t bdf;
-#endif
/* Determine the value to store in AX for BIOS POST. Per the PCI specs,
AH must contain the bus and AL must contain the devfn, encoded as
@@ -250,14 +243,9 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
*/
memset(®s, 0, sizeof(regs));
memset(&sregs, 0, sizeof(sregs));
-#ifdef CONFIG_DM_PCI
bdf = dm_pci_get_bdf(pcidev);
regs.x.ax = (int)PCI_BUS(bdf) << 8 |
(int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf);
-#else
- regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
- ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
-#endif
/*Setup the X86 emulator for the VGA BIOS*/
BE_setVGA(vga_info);
@@ -300,28 +288,15 @@ NOTE: This function leaves the original memory aperture disabled by leaving
it programmed to all 1's. It must be restored to the correct value
later.
****************************************************************************/
-#ifdef CONFIG_DM_PCI
static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar)
-#else
-static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
-#endif
{
u32 base, size;
for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
-#ifdef CONFIG_DM_PCI
dm_pci_read_config32(pcidev, *bar, &base);
-#else
- pci_read_config_dword(pcidev, *bar, &base);
-#endif
if (!(base & 0x1)) {
-#ifdef CONFIG_DM_PCI
dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF);
dm_pci_read_config32(pcidev, *bar, &size);
-#else
- pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF);
- pci_read_config_dword(pcidev, *bar, &size);
-#endif
size = ~(size & ~0xFF) + 1;
if (size >= MAX_BIOSLEN)
return base & ~0xFF;
@@ -344,19 +319,11 @@ necessary).
Anyway to fix this we change all I/O mapped base registers and
chop off the top bits.
****************************************************************************/
-#ifdef CONFIG_DM_PCI
static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base)
-#else
-static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
-#endif
{
if ((*base & 0x1) && (*base > 0xFFFE)) {
*base &= 0xFFFF;
-#ifdef CONFIG_DM_PCI
dm_pci_write_config32(pcidev, reg, *base);
-#else
- pci_write_config_dword(pcidev, reg, *base);
-#endif
}
}
@@ -371,30 +338,18 @@ Pointers to the mapped BIOS image
REMARKS:
Maps a pointer to the BIOS image on the graphics card on the PCI bus.
****************************************************************************/
-#ifdef CONFIG_DM_PCI
void *PCI_mapBIOSImage(struct udevice *pcidev)
-#else
-void *PCI_mapBIOSImage(pci_dev_t pcidev)
-#endif
{
u32 BIOSImageBus;
int BIOSImageBAR;
u8 *BIOSImage;
/*Save PCI BAR registers that might get changed*/
-#ifdef CONFIG_DM_PCI
dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-#else
- pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-#endif
/*Fix up I/O base registers to less than 64K */
if(saveBaseAddress14 != 0)
@@ -413,21 +368,12 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev)
return NULL;
}
-#ifdef CONFIG_DM_PCI
BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus,
PCI_REGION_MEM, 0, MAP_NOCACHE);
/*Change the PCI BAR registers to map it onto the bus.*/
dm_pci_write_config32(pcidev, BIOSImageBAR, 0);
dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
-#else
- BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus,
- PCI_REGION_MEM, 0, MAP_NOCACHE);
-
- /*Change the PCI BAR registers to map it onto the bus.*/
- pci_write_config_dword(pcidev, BIOSImageBAR, 0);
- pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
-#endif
udelay(1);
/*Check that the BIOS image is valid. If not fail, or return the
@@ -447,7 +393,6 @@ pcidev - PCI device info for the video card on the bus
REMARKS:
Unmaps the BIOS image for the device and restores framebuffer mappings
****************************************************************************/
-#ifdef CONFIG_DM_PCI
void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
{
dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
@@ -456,16 +401,6 @@ void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
}
-#else
-void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
-{
- pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
-}
-#endif
/****************************************************************************
PARAMETERS:
@@ -479,22 +414,14 @@ REMARKS:
Loads and POST's the display controllers BIOS, directly from the BIOS
image we can extract over the PCI bus.
****************************************************************************/
-#ifdef CONFIG_DM_PCI
static int PCI_postController(struct udevice *pcidev, uchar *bios_rom,
int bios_len, BE_VGAInfo *vga_info,
int vesa_mode, struct vbe_mode_info *mode_info)
-#else
-static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
- BE_VGAInfo *vga_info, int vesa_mode,
- struct vbe_mode_info *mode_info)
-#endif
{
u32 bios_image_len;
uchar *mapped_bios;
uchar *copy_of_bios;
-#ifdef CONFIG_DM_PCI
pci_dev_t bdf;
-#endif
if (bios_rom) {
copy_of_bios = bios_rom;
@@ -522,16 +449,10 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
}
/*Save information in vga_info structure*/
-#ifdef CONFIG_DM_PCI
bdf = dm_pci_get_bdf(pcidev);
vga_info->function = PCI_FUNC(bdf);
vga_info->device = PCI_DEV(bdf);
vga_info->bus = PCI_BUS(bdf);
-#else
- vga_info->function = PCI_FUNC(pcidev);
- vga_info->device = PCI_DEV(pcidev);
- vga_info->bus = PCI_BUS(pcidev);
-#endif
vga_info->pcidev = pcidev;
vga_info->BIOSImage = copy_of_bios;
vga_info->BIOSImageLen = bios_image_len;
@@ -549,22 +470,13 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
return true;
}
-#ifdef CONFIG_DM_PCI
int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **vga_infop)
-#else
-int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
-#endif
{
BE_VGAInfo *VGAInfo;
-#ifdef CONFIG_DM_PCI
pci_dev_t bdf = dm_pci_get_bdf(pcidev);
printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
PCI_BUS(bdf), PCI_FUNC(bdf), PCI_DEV(bdf));
-#else
- printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
- PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
-#endif
/*Initialise the x86 BIOS emulator*/
if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
printf("videoboot: Out of memory!\n");
@@ -582,15 +494,9 @@ void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void))
X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
}
-#ifdef CONFIG_DM_PCI
int biosemu_run(struct udevice *pcidev, uchar *bios_rom, int bios_len,
BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
struct vbe_mode_info *mode_info)
-#else
-int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
- BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
- struct vbe_mode_info *mode_info)
-#endif
{
/*Post all the display controller BIOS'es*/
if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
@@ -623,12 +529,8 @@ REMARKS:
Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
and the X86 BIOS emulator module.
****************************************************************************/
-#ifdef CONFIG_DM_PCI
int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
int clean_up)
-#else
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
-#endif
{
BE_VGAInfo *VGAInfo;
int ret;
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index 77c7f94bc63..9596a1fdd3e 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -185,21 +185,12 @@ static void X86API int1A(int unused)
case 0xB103: /* Find PCI class code */
M.x86.R_AH = DEVICE_NOT_FOUND;
#ifdef __KERNEL__
-#ifdef CONFIG_DM_PCI
dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
&interface);
dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
&subclass);
dm_pci_read_config8(_BE_env.vgaInfo.pcidev,
PCI_CLASS_DEVICE + 1, &baseclass);
-#else
- pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
- &interface);
- pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
- &subclass);
- pci_read_config_byte(_BE_env.vgaInfo.pcidev,
- PCI_CLASS_DEVICE + 1, &baseclass);
-#endif
if (M.x86.R_CL == interface && M.x86.R_CH == subclass
&& (u8) (M.x86.R_ECX >> 16) == baseclass) {
#else
@@ -218,13 +209,8 @@ static void X86API int1A(int unused)
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
dm_pci_read_config8(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
&M.x86.R_CL);
-# else
- pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
- &M.x86.R_CL);
-# endif
#else
M.x86.R_CL =
(u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE,
@@ -238,13 +224,8 @@ static void X86API int1A(int unused)
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
dm_pci_read_config16(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
&M.x86.R_CX);
-# else
- pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
- &M.x86.R_CX);
-# endif
#else
M.x86.R_CX =
(u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD,
@@ -258,13 +239,8 @@ static void X86API int1A(int unused)
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
dm_pci_read_config32(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, &M.x86.R_ECX);
-# else
- pci_read_config_dword(_BE_env.vgaInfo.pcidev,
- M.x86.R_DI, &M.x86.R_ECX);
-# endif
#else
M.x86.R_ECX =
(u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD,
@@ -278,13 +254,8 @@ static void X86API int1A(int unused)
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
dm_pci_write_config8(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_CL);
-# else
- pci_write_config_byte(_BE_env.vgaInfo.pcidev,
- M.x86.R_DI, M.x86.R_CL);
-# endif
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE,
_BE_env.vgaInfo.pciInfo);
@@ -297,13 +268,8 @@ static void X86API int1A(int unused)
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_CX);
-# else
- pci_write_config_word(_BE_env.vgaInfo.pcidev,
- M.x86.R_DI, M.x86.R_CX);
-# endif
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD,
_BE_env.vgaInfo.pciInfo);
@@ -316,13 +282,8 @@ static void X86API int1A(int unused)
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_ECX);
-# else
- pci_write_config_dword(_BE_env.vgaInfo.pcidev,
- M.x86.R_DI, M.x86.R_ECX);
-# endif
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD,
_BE_env.vgaInfo.pciInfo);
diff --git a/include/bios_emul.h b/include/bios_emul.h
index 158e0f223d8..72410dc7948 100644
--- a/include/bios_emul.h
+++ b/include/bios_emul.h
@@ -30,11 +30,7 @@ typedef struct {
int bus;
u32 VendorID;
u32 DeviceID;
-#ifdef CONFIG_DM_PCI
struct udevice *pcidev;
-#else
- pci_dev_t pcidev;
-#endif
void *BIOSImage;
u32 BIOSImageLen;
u8 LowMem[1536];
@@ -42,12 +38,8 @@ typedef struct {
struct vbe_mode_info;
-#ifdef CONFIG_DM_PCI
int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
int clean_up);
-#else
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up);
-#endif
/* Run a BIOS ROM natively (only supported on x86 machines) */
void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
@@ -65,18 +57,10 @@ void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
-#ifdef CONFIG_DM_PCI
int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo);
int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len,
BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
struct vbe_mode_info *mode_info);
-#else
-int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
-
-int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
- BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
- struct vbe_mode_info *mode_info);
-#endif
#endif
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 21/32] net: Drop DM_PCI check from designware driver
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (19 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 20/32] pci: Drop DM_PCI check from bios_emul Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-09-14 1:03 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 22/32] pci: imx: Drop DM_PCI check from cpu driver Simon Glass
` (11 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass, Joe Hershberger
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/net/designware.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 5d92257e74d..5aaac603a0e 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -756,16 +756,16 @@ int designware_eth_write_hwaddr(struct udevice *dev)
static int designware_eth_bind(struct udevice *dev)
{
-#ifdef CONFIG_DM_PCI
- static int num_cards;
- char name[20];
-
- /* Create a unique device name for PCI type devices */
- if (device_is_on_pci_bus(dev)) {
- sprintf(name, "eth_designware#%u", num_cards++);
- device_set_name(dev, name);
+ if (IS_ENABLED(CONFIG_PCI)) {
+ static int num_cards;
+ char name[20];
+
+ /* Create a unique device name for PCI type devices */
+ if (device_is_on_pci_bus(dev)) {
+ sprintf(name, "eth_designware#%u", num_cards++);
+ device_set_name(dev, name);
+ }
}
-#endif
return 0;
}
@@ -831,12 +831,11 @@ int designware_eth_probe(struct udevice *dev)
else
reset_deassert_bulk(&reset_bulk);
-#ifdef CONFIG_DM_PCI
/*
* If we are on PCI bus, either directly attached to a PCI root port,
* or via a PCI bridge, fill in plat before we probe the hardware.
*/
- if (device_is_on_pci_bus(dev)) {
+ if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) {
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
iobase = dm_pci_mem_to_phys(dev, iobase);
@@ -844,7 +843,6 @@ int designware_eth_probe(struct udevice *dev)
pdata->iobase = iobase;
pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
}
-#endif
debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
ioaddr = iobase;
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 22/32] pci: imx: Drop DM_PCI check from cpu driver
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (20 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 21/32] net: Drop DM_PCI check from designware driver Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 23/32] pci: arm: mvebu: Drop DM_PCI check from Simon Glass
` (10 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass, Stefano Babic
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/mach-imx/cpu.c | 4 ----
include/pci.h | 4 ----
2 files changed, 8 deletions(-)
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 423b7153522..8eb05c8dd67 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -283,10 +283,6 @@ u32 get_ahb_clk(void)
void arch_preboot_os(void)
{
-#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
- imx_pcie_remove();
-#endif
-
#if defined(CONFIG_IMX_AHCI)
struct udevice *dev;
int rc;
diff --git a/include/pci.h b/include/pci.h
index ca086420ff2..2c2930e7a74 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -785,10 +785,6 @@ int pci_last_busno(void);
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
-#ifdef CONFIG_PCIE_IMX
-extern void imx_pcie_remove(void);
-#endif
-
/**
* pci_write_bar32() - Write the address of a BAR including control bits
*
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 23/32] pci: arm: mvebu: Drop DM_PCI check from
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (21 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 22/32] pci: imx: Drop DM_PCI check from cpu driver Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 12:46 ` Tom Rini
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 24/32] pci: sata_sil: Drop DM_PCI checks Simon Glass
` (9 subsequent siblings)
32 siblings, 2 replies; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass, Albert Aribaud
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Use CONFIG_PCI instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/mach-mvebu/arm64-common.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index fa687d8abbb..06c4994e065 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -104,10 +104,9 @@ int arch_early_init_r(void)
/* Cause the SATA device to do its early init */
uclass_first_device(UCLASS_AHCI, &dev);
-#ifdef CONFIG_DM_PCI
/* Trigger PCIe devices detection */
- pci_init();
-#endif
+ if (IS_ENABLED(PCI))
+ pci_init();
return 0;
}
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 23/32] pci: arm: mvebu: Drop DM_PCI check from
2021-08-02 0:54 ` [PATCH v2 23/32] pci: arm: mvebu: Drop DM_PCI check from Simon Glass
@ 2021-08-06 12:46 ` Tom Rini
2021-08-06 21:21 ` Tom Rini
1 sibling, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 12:46 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Albert Aribaud
[-- Attachment #1: Type: text/plain, Size: 1005 bytes --]
On Sun, Aug 01, 2021 at 06:54:36PM -0600, Simon Glass wrote:
> We don't need this check anymore since when PCI is enabled, driver model
> is always used.
>
> Use CONFIG_PCI instead.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
> arch/arm/mach-mvebu/arm64-common.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
> index fa687d8abbb..06c4994e065 100644
> --- a/arch/arm/mach-mvebu/arm64-common.c
> +++ b/arch/arm/mach-mvebu/arm64-common.c
> @@ -104,10 +104,9 @@ int arch_early_init_r(void)
> /* Cause the SATA device to do its early init */
> uclass_first_device(UCLASS_AHCI, &dev);
>
> -#ifdef CONFIG_DM_PCI
> /* Trigger PCIe devices detection */
> - pci_init();
> -#endif
> + if (IS_ENABLED(PCI))
> + pci_init();
>
> return 0;
> }
This needs to be IS_ENABLED(CONFIG_PCI), I've fixed it locally.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 23/32] pci: arm: mvebu: Drop DM_PCI check from
2021-08-02 0:54 ` [PATCH v2 23/32] pci: arm: mvebu: Drop DM_PCI check from Simon Glass
2021-08-06 12:46 ` Tom Rini
@ 2021-08-06 21:21 ` Tom Rini
1 sibling, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:21 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Albert Aribaud
[-- Attachment #1: Type: text/plain, Size: 326 bytes --]
On Sun, Aug 01, 2021 at 06:54:36PM -0600, Simon Glass wrote:
> We don't need this check anymore since when PCI is enabled, driver model
> is always used.
>
> Use CONFIG_PCI instead.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reworded and fixed as I noted and applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 24/32] pci: sata_sil: Drop DM_PCI checks
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (22 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 23/32] pci: arm: mvebu: Drop DM_PCI check from Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 25/32] distro_bootcmd: Drop DM_PCI check Simon Glass
` (8 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
We don't need these checks anymore since when PCI is enabled, driver model
is always used.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/ata/sata_sil.c | 8 --------
drivers/ata/sata_sil.h | 4 ----
2 files changed, 12 deletions(-)
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 7e4e97d803e..dda712f42cb 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -27,11 +27,7 @@
#include "sata_sil.h"
-#ifdef CONFIG_DM_PCI
#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
-#else
-#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
-#endif
/* just compatible ahci_ops */
struct sil_ops {
@@ -616,11 +612,7 @@ static int sil_init_sata(struct udevice *uc_dev, int dev)
#else
priv->sil_sata_desc[dev] = sata;
priv->port_num = dev;
-#ifdef CONFIG_DM_PCI
sata->devno = uc_dev->parent;
-#else
- sata->devno = sata_info.devno;
-#endif /* CONFIG_DM_PCI */
#endif
sata->id = dev;
sata->port = port;
diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h
index a300c0c3887..bea4322c919 100644
--- a/drivers/ata/sata_sil.h
+++ b/drivers/ata/sata_sil.h
@@ -21,11 +21,7 @@ struct sil_sata {
u16 pio;
u16 mwdma;
u16 udma;
-#ifdef CONFIG_DM_PCI
struct udevice *devno;
-#else
- pci_dev_t devno;
-#endif
int wcache;
int flush;
int flush_ext;
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 25/32] distro_bootcmd: Drop DM_PCI check
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (23 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 24/32] pci: sata_sil: Drop DM_PCI checks Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 12:46 ` Tom Rini
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 26/32] pci: Drop pci_init_board() Simon Glass
` (7 subsequent siblings)
32 siblings, 2 replies; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
include/config_distro_bootcmd.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index e70423f25dd..9b9dd308e68 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -265,14 +265,9 @@
BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
#endif
-#if defined(CONFIG_DM_PCI)
#define BOOTENV_RUN_PCI_ENUM "run boot_pci_enum; "
#define BOOTENV_SHARED_PCI \
"boot_pci_enum=pci enum\0"
-#else
-#define BOOTENV_RUN_PCI_ENUM
-#define BOOTENV_SHARED_PCI
-#endif
#ifdef CONFIG_CMD_USB
#define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; "
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 25/32] distro_bootcmd: Drop DM_PCI check
2021-08-02 0:54 ` [PATCH v2 25/32] distro_bootcmd: Drop DM_PCI check Simon Glass
@ 2021-08-06 12:46 ` Tom Rini
2021-08-06 21:21 ` Tom Rini
1 sibling, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 12:46 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List
[-- Attachment #1: Type: text/plain, Size: 1066 bytes --]
On Sun, Aug 01, 2021 at 06:54:38PM -0600, Simon Glass wrote:
> We don't need this check anymore since when PCI is enabled, driver model
> is always used.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
> include/config_distro_bootcmd.h | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
> index e70423f25dd..9b9dd308e68 100644
> --- a/include/config_distro_bootcmd.h
> +++ b/include/config_distro_bootcmd.h
> @@ -265,14 +265,9 @@
> BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
> #endif
>
> -#if defined(CONFIG_DM_PCI)
> #define BOOTENV_RUN_PCI_ENUM "run boot_pci_enum; "
> #define BOOTENV_SHARED_PCI \
> "boot_pci_enum=pci enum\0"
> -#else
> -#define BOOTENV_RUN_PCI_ENUM
> -#define BOOTENV_SHARED_PCI
> -#endif
>
> #ifdef CONFIG_CMD_USB
> #define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; "
This check needs to stay and be for CONFIG_PCI now, I've fixed this
locally.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 25/32] distro_bootcmd: Drop DM_PCI check
2021-08-02 0:54 ` [PATCH v2 25/32] distro_bootcmd: Drop DM_PCI check Simon Glass
2021-08-06 12:46 ` Tom Rini
@ 2021-08-06 21:21 ` Tom Rini
1 sibling, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:21 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List
[-- Attachment #1: Type: text/plain, Size: 282 bytes --]
On Sun, Aug 01, 2021 at 06:54:38PM -0600, Simon Glass wrote:
> We don't need this check anymore since when PCI is enabled, driver model
> is always used.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Fixed as I noted and applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 26/32] pci: Drop pci_init_board()
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (24 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 25/32] distro_bootcmd: Drop DM_PCI check Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:21 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 27/32] pci: ppc: Drop ftpci100 driver Simon Glass
` (6 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
With the conversion to driver model, this is not needed now. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
board/cavium/thunderx/thunderx.c | 7 --
board/freescale/mpc8349emds/pci.c | 73 ------------------
board/freescale/mpc837xerdb/Makefile | 1 -
board/freescale/mpc837xerdb/pci.c | 109 ---------------------------
board/xes/common/fsl_8xxx_pci.c | 50 ------------
include/init.h | 3 -
6 files changed, 243 deletions(-)
delete mode 100644 board/freescale/mpc837xerdb/pci.c
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index a7dc5c6aeb6..a8f8c785584 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -123,10 +123,3 @@ int board_eth_init(struct bd_info *bis)
return rc;
}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- printf("DEBUG: PCI Init TODO *****\n");
-}
-#endif
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 3ddbe717756..8c76c46d420 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -115,77 +115,4 @@ void pib_init(void)
i2c_set_bus_num(orig_i2c_bus);
}
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
- /* Enable all 8 PCI_CLK_OUTPUTS */
- clk->occr = 0xff000000;
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-
-#else
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- mpc83xx_pci_init(1, reg);
-
- /* Configure PCI Inbound Translation Windows (3 1MB windows) */
- pci_ctrl->pitar0 = 0x0;
- pci_ctrl->pibar0 = 0x0;
- pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
- pci_ctrl->pitar1 = 0x0;
- pci_ctrl->pibar1 = 0x0;
- pci_ctrl->piebar1 = 0x0;
- pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
- pci_ctrl->pitar2 = 0x0;
- pci_ctrl->pibar2 = 0x0;
- pci_ctrl->piebar2 = 0x0;
- pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile
index c683b017b55..4661e4cf232 100644
--- a/board/freescale/mpc837xerdb/Makefile
+++ b/board/freescale/mpc837xerdb/Makefile
@@ -4,4 +4,3 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += mpc837xerdb.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
deleted file mode 100644
index dccf8c5551b..00000000000
--- a/board/freescale/mpc837xerdb/pci.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI_MEM_BASE,
- phys_start: CONFIG_SYS_PCI_MEM_PHYS,
- size: CONFIG_SYS_PCI_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
- size: CONFIG_SYS_PCI_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI_IO_BASE,
- phys_start: CONFIG_SYS_PCI_IO_PHYS,
- size: CONFIG_SYS_PCI_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-static struct pci_region pcie_regions_1[] = {
- {
- .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
- .size = CONFIG_SYS_PCIE2_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
- .size = CONFIG_SYS_PCIE2_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile sysconf83xx_t *sysconf = &immr->sysconf;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *reg[] = { pci_regions };
- struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
- u32 spridr = in_be32(&immr->sysconf.spridr);
-
- /* Enable all 5 PCI_CLK_OUTPUTS */
- clk->occr |= 0xf8000000;
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-
- /* There is no PEX in MPC8379 parts. */
- if (PARTID_NO_E(spridr) == SPR_8379)
- return;
-
- /* Configure the clock for PCIE controller */
- clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
- SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- out_be32(&sysconf->pecr2, 0xE0008000);
- udelay(2000);
-
- /* Configure PCI Express Local Access Windows */
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(2, pcie_reg);
-}
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 157aa32826a..c1fce7d3313 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -14,56 +14,6 @@
#include <linux/libfdt.h>
#include <fdt_support.h>
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-void pci_init_board(void)
-{
- int first_free_busno = 0;
-
-#ifdef CONFIG_PCI1
- int pcie_ep;
- struct fsl_pci_info pci_info;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 devdisr = in_be32(&gur->devdisr);
- uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
- uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
- uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
- uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
- uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
- pci_32 ? 32 : 64,
- pcix ? "PCIX" : "PCI",
- pci_spd_norm ? ">=" : "<=",
- pcix ? freq * 2 : freq,
- pcie_ep ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter");
-
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI1: disabled\n");
- }
-#elif defined CONFIG_ARCH_MPC8548
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- /* PCI1 not present on MPC8572 */
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
-#endif
-
- fsl_pcie_init_board(first_free_busno);
-}
-
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_pci_setup(void *blob, struct bd_info *bd)
{
diff --git a/include/init.h b/include/init.h
index fd51d7f9667..c781789e367 100644
--- a/include/init.h
+++ b/include/init.h
@@ -297,9 +297,6 @@ int board_late_init(void);
int board_postclk_init(void); /* after clocks/timebase, before env/serial */
int board_early_init_r(void);
-/* TODO(sjg@chromium.org): Drop this when DM_PCI migration is completed */
-void pci_init_board(void);
-
/**
* arch_initr_trap() - Init traps
*
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 27/32] pci: ppc: Drop ftpci100 driver
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (25 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 26/32] pci: Drop pci_init_board() Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:22 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 28/32] ppc: Drop idt8t49n222a_serdes_clk driver Simon Glass
` (5 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
This is not used in U-Boot at present. Drop it and related config options.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/nds32/include/asm/arch-ag102/ag102.h | 2 -
drivers/pci/Makefile | 1 -
drivers/pci/pci_ftpci100.c | 319 ----------------------
scripts/config_whitelist.txt | 4 -
4 files changed, 326 deletions(-)
delete mode 100644 drivers/pci/pci_ftpci100.c
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
index d1f4b02e10e..3255db6592e 100644
--- a/arch/nds32/include/asm/arch-ag102/ag102.h
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -11,8 +11,6 @@
* Hardware register bases
*/
-/* PCI Controller */
-#define CONFIG_FTPCI100_BASE 0x90000000
/* LPC Controller */
#define CONFIG_LPC_IO_BASE 0x90100000
/* LPC Controller */
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 83d7a4e403c..bdfdec98a08 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
-obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o
diff --git a/drivers/pci/pci_ftpci100.c b/drivers/pci/pci_ftpci100.c
deleted file mode 100644
index 32fac878a67..00000000000
--- a/drivers/pci/pci_ftpci100.c
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <malloc.h>
-#include <pci.h>
-
-#include <faraday/ftpci100.h>
-
-#include <asm/io.h>
-#include <asm/types.h> /* u32, u16.... used by pci.h */
-
-struct ftpci100_data {
- unsigned int reg_base;
- unsigned int io_base;
- unsigned int mem_base;
- unsigned int mmio_base;
- unsigned int ndevs;
-};
-
-static struct pci_config devs[FTPCI100_MAX_FUNCTIONS];
-static struct pci_controller local_hose;
-
-static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
- unsigned char header, struct ftpci100_data *priv)
-{
- struct pci_controller *hose = (struct pci_controller *)&local_hose;
- unsigned int i, tmp32, bar_no, iovsmem = 1;
- pci_dev_t dev_nu;
-
- /* A device is present, add an entry to the array */
- devs[priv->ndevs].bus = bus;
- devs[priv->ndevs].dev = dev;
- devs[priv->ndevs].func = func;
-
- dev_nu = PCI_BDF(bus, dev, func);
-
- if ((header & 0x7f) == 0x01)
- /* PCI-PCI Bridge */
- bar_no = 2;
- else
- bar_no = 6;
-
- /* Allocate address spaces by configuring BARs */
- for (i = 0; i < bar_no; i++) {
- pci_hose_write_config_dword(hose, dev_nu,
- PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
- pci_hose_read_config_dword(hose, dev_nu,
- PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
-
- if (tmp32 == 0x0)
- continue;
-
- /* IO space */
- if (tmp32 & 0x1) {
- iovsmem = 0;
- unsigned int size_mask = ~(tmp32 & 0xfffffffc);
-
- if (priv->io_base & size_mask)
- priv->io_base = (priv->io_base & ~size_mask) + \
- size_mask + 1;
-
- devs[priv->ndevs].bar[i].addr = priv->io_base;
- devs[priv->ndevs].bar[i].size = size_mask + 1;
-
- pci_hose_write_config_dword(hose, dev_nu,
- PCI_BASE_ADDRESS_0 + i * 4,
- priv->io_base);
-
- debug("Allocated IO address 0x%X-" \
- "0x%X for Bus %d, Device %d, Function %d\n",
- priv->io_base,
- priv->io_base + size_mask, bus, dev, func);
-
- priv->io_base += size_mask + 1;
- } else {
- /* Memory space */
- unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
- unsigned int is_pref = tmp32 & 0x8;
- unsigned int size_mask = ~(tmp32 & 0xfffffff0);
- unsigned int alloc_base;
- unsigned int *addr_mem_base;
-
- if (is_pref)
- addr_mem_base = &priv->mem_base;
- else
- addr_mem_base = &priv->mmio_base;
-
- alloc_base = *addr_mem_base;
-
- if (alloc_base & size_mask)
- alloc_base = (alloc_base & ~size_mask) \
- + size_mask + 1;
-
- pci_hose_write_config_dword(hose, dev_nu,
- PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
-
- debug("Allocated %s address 0x%X-" \
- "0x%X for Bus %d, Device %d, Function %d\n",
- is_pref ? "MEM" : "MMIO", alloc_base,
- alloc_base + size_mask, bus, dev, func);
-
- devs[priv->ndevs].bar[i].addr = alloc_base;
- devs[priv->ndevs].bar[i].size = size_mask + 1;
-
- debug("BAR address BAR size\n");
- debug("%010x %08d\n",
- devs[priv->ndevs].bar[0].addr,
- devs[priv->ndevs].bar[0].size);
-
- alloc_base += size_mask + 1;
- *addr_mem_base = alloc_base;
-
- if (is_64bit) {
- i++;
- pci_hose_write_config_dword(hose, dev_nu,
- PCI_BASE_ADDRESS_0 + i * 4, 0x0);
- }
- }
- }
-
- /* Enable Bus Master, Memory Space, and IO Space */
- pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
- pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
- pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
-
- pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
-
- tmp32 &= 0xffff;
-
- if (iovsmem == 0)
- tmp32 |= 0x5;
- else
- tmp32 |= 0x6;
-
- pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
-}
-
-static void pci_bus_scan(struct ftpci100_data *priv)
-{
- struct pci_controller *hose = (struct pci_controller *)&local_hose;
- unsigned int bus, dev, func;
- pci_dev_t dev_nu;
- unsigned int data32;
- unsigned int tmp;
- unsigned char header;
- unsigned char int_pin;
- unsigned int niobars;
- unsigned int nmbars;
-
- priv->ndevs = 1;
-
- nmbars = 0;
- niobars = 0;
-
- for (bus = 0; bus < MAX_BUS_NUM; bus++)
- for (dev = 0; dev < MAX_DEV_NUM; dev++)
- for (func = 0; func < MAX_FUN_NUM; func++) {
- dev_nu = PCI_BDF(bus, dev, func);
- pci_hose_read_config_dword(hose, dev_nu,
- PCI_VENDOR_ID, &data32);
-
- /*
- * some broken boards return 0 or ~0,
- * if a slot is empty.
- */
- if (data32 == 0xffffffff ||
- data32 == 0x00000000 ||
- data32 == 0x0000ffff ||
- data32 == 0xffff0000)
- continue;
-
- pci_hose_read_config_dword(hose, dev_nu,
- PCI_HEADER_TYPE, &tmp);
- header = (unsigned char)tmp;
- setup_pci_bar(bus, dev, func, header, priv);
-
- devs[priv->ndevs].v_id = (u16)(data32 & \
- 0x0000ffff);
-
- devs[priv->ndevs].d_id = (u16)((data32 & \
- 0xffff0000) >> 16);
-
- /* Figure out what INTX# line the card uses */
- pci_hose_read_config_byte(hose, dev_nu,
- PCI_INTERRUPT_PIN, &int_pin);
-
- /* assign the appropriate irq line */
- if (int_pin > PCI_IRQ_LINES) {
- printf("more irq lines than expect\n");
- } else if (int_pin != 0) {
- /* This device uses an interrupt line */
- devs[priv->ndevs].pin = int_pin;
- }
-
- pci_hose_read_config_dword(hose, dev_nu,
- PCI_CLASS_DEVICE, &data32);
-
- debug("%06d %03d %03d " \
- "%04d %08x %08x " \
- "%03d %08x %06d %08x\n",
- priv->ndevs, devs[priv->ndevs].bus,
- devs[priv->ndevs].dev,
- devs[priv->ndevs].func,
- devs[priv->ndevs].d_id,
- devs[priv->ndevs].v_id,
- devs[priv->ndevs].pin,
- devs[priv->ndevs].bar[0].addr,
- devs[priv->ndevs].bar[0].size,
- data32 >> 8);
-
- priv->ndevs++;
- }
-}
-
-static void ftpci_preinit(struct ftpci100_data *priv)
-{
- struct ftpci100_ahbc *ftpci100;
- struct pci_controller *hose = (struct pci_controller *)&local_hose;
- u32 pci_config_addr;
- u32 pci_config_data;
-
- priv->reg_base = CONFIG_FTPCI100_BASE;
- priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE;
- priv->mmio_base = CONFIG_FTPCI100_MEM_BASE;
- priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE;
-
- ftpci100 = (struct ftpci100_ahbc *)priv->reg_base;
-
- pci_config_addr = (u32) &ftpci100->conf;
- pci_config_data = (u32) &ftpci100->data;
-
- /* print device name */
- printf("FTPCI100\n");
-
- /* dump basic configuration */
- debug("%s: Config addr is %08X, data port is %08X\n",
- __func__, pci_config_addr, pci_config_data);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 0,
- CONFIG_PCI_MEM_BUS,
- CONFIG_PCI_MEM_PHYS,
- CONFIG_PCI_MEM_SIZE,
- PCI_REGION_MEM);
- hose->region_count++;
-
- /* PCI IO space */
- pci_set_region(hose->regions + 1,
- CONFIG_PCI_IO_BUS,
- CONFIG_PCI_IO_PHYS,
- CONFIG_PCI_IO_SIZE,
- PCI_REGION_IO);
- hose->region_count++;
-
-#if defined(CONFIG_PCI_SYS_BUS)
- /* PCI System Memory space */
- pci_set_region(hose->regions + 2,
- CONFIG_PCI_SYS_BUS,
- CONFIG_PCI_SYS_PHYS,
- CONFIG_PCI_SYS_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
- hose->region_count++;
-#endif
-
- /* setup indirect read/write function */
- pci_setup_indirect(hose, pci_config_addr, pci_config_data);
-
- /* register hose */
- pci_register_hose(hose);
-}
-
-void pci_ftpci_init(void)
-{
- struct ftpci100_data *priv = NULL;
- struct pci_controller *hose = (struct pci_controller *)&local_hose;
- pci_dev_t bridge_num;
-
- struct pci_device_id bridge_ids[] = {
- {FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
- {0, 0}
- };
-
- priv = malloc(sizeof(struct ftpci100_data));
-
- if (!priv) {
- printf("%s(): failed to malloc priv\n", __func__);
- return;
- }
-
- memset(priv, 0, sizeof(struct ftpci100_data));
-
- ftpci_preinit(priv);
-
- debug("Device bus dev func deviceID vendorID pin address" \
- " size class\n");
-
- pci_bus_scan(priv);
-
- /*
- * Setup the PCI Bridge Window to 1GB,
- * it will cause USB OHCI Host controller Unrecoverable Error
- * if it is not set.
- */
- bridge_num = pci_find_devices(bridge_ids, 0);
- if (bridge_num == -1) {
- printf("PCI Bridge not found\n");
- return;
- }
- pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
- FTPCI100_BASE_ADR_SIZE(1024));
-}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 17615226d5b..e6bddf15b88 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -505,10 +505,6 @@ CONFIG_FTINTC010_BASE
CONFIG_FTLCDC100_BASE
CONFIG_FTMAC100_BASE
CONFIG_FTMAC110_BASE
-CONFIG_FTPCI100_BASE
-CONFIG_FTPCI100_IO_SIZE
-CONFIG_FTPCI100_MEM_BASE
-CONFIG_FTPCI100_MEM_SIZE
CONFIG_FTPMU010
CONFIG_FTPMU010_BASE
CONFIG_FTPMU010_POWER
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 27/32] pci: ppc: Drop ftpci100 driver
2021-08-02 0:54 ` [PATCH v2 27/32] pci: ppc: Drop ftpci100 driver Simon Glass
@ 2021-08-06 21:22 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:22 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 244 bytes --]
On Sun, Aug 01, 2021 at 06:54:40PM -0600, Simon Glass wrote:
> This is not used in U-Boot at present. Drop it and related config options.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 28/32] ppc: Drop idt8t49n222a_serdes_clk driver
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (26 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 27/32] pci: ppc: Drop ftpci100 driver Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:22 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 29/32] ppc: Drop t4qds and b4860qds references Simon Glass
` (4 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
This is not used. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
board/freescale/common/Makefile | 1 -
.../common/idt8t49n222a_serdes_clk.c | 208 ------------------
.../common/idt8t49n222a_serdes_clk.h | 106 ---------
3 files changed, 315 deletions(-)
delete mode 100644 board/freescale/common/idt8t49n222a_serdes_clk.c
delete mode 100644 board/freescale/common/idt8t49n222a_serdes_clk.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 116c1e71cc1..3a171688c3f 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -63,7 +63,6 @@ obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
-obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c
deleted file mode 100644
index bb3cdac8418..00000000000
--- a/board/freescale/common/idt8t49n222a_serdes_clk.c
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Author: Shaveta Leekha <shaveta@freescale.com>
- */
-
-#include "idt8t49n222a_serdes_clk.h"
-#include <log.h>
-#include <linux/delay.h>
-
-#define DEVICE_ID_REG 0x00
-
-static int check_pll_status(u8 idt_addr)
-{
- u8 val = 0;
- int ret;
-
- ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
- if (ret < 0) {
- printf("IDT:0x%x could not read status register from device.\n",
- idt_addr);
- return ret;
- }
-
- if (val & 0x04) {
- debug("idt8t49n222a PLL is LOCKED: %x\n", val);
- } else {
- printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
- return -1;
- }
-
- return 0;
-}
-
-int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
- enum serdes_refclk refclk1,
- enum serdes_refclk refclk2, u8 feedback)
-{
- u8 dev_id = 0;
- int i, ret;
-
- debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
- idt_addr);
-
- ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
- if (ret < 0) {
- debug("IDT:0x%x could not read DEV_ID from device.\n",
- idt_addr);
- return ret;
- }
-
- if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
- debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
- idt_addr);
- }
-
- if (serdes_num != 1 && serdes_num != 2) {
- debug("serdes_num should be 1 for SerDes1 and"
- " 2 for SerDes2.\n");
- return -1;
- }
-
- if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
- || (refclk1 != SERDES_REFCLK_122_88
- && refclk2 == SERDES_REFCLK_122_88)) {
- debug("Only one refclk at 122.88MHz is not supported."
- " Please set both refclk1 & refclk2 to 122.88MHz"
- " or both not to 122.88MHz.\n");
- return -1;
- }
-
- if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
- && refclk1 != SERDES_REFCLK_125
- && refclk1 != SERDES_REFCLK_156_25) {
- debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
- " or 156.25MHz.\n");
- return -1;
- }
-
- if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
- && refclk2 != SERDES_REFCLK_125
- && refclk2 != SERDES_REFCLK_156_25) {
- debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
- " or 156.25MHz.\n");
- return -1;
- }
-
- if (feedback != 0 && feedback != 1) {
- debug("valid values for feedback are 0(default) or 1.\n");
- return -1;
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- */
- if (refclk1 == SERDES_REFCLK_122_88 &&
- refclk2 == SERDES_REFCLK_122_88) {
- printf("Setting refclk1:122.88 and refclk2:122.88\n");
- for (i = 0; i < NUM_IDT_REGS; i++)
- i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
- idt_conf_122_88[i][1]);
-
- if (feedback) {
- for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
- i2c_reg_write(idt_addr,
- idt_conf_122_88_feedback[i][0],
- idt_conf_122_88_feedback[i][1]);
- }
- }
-
- if (refclk1 != SERDES_REFCLK_122_88 &&
- refclk2 != SERDES_REFCLK_122_88) {
- for (i = 0; i < NUM_IDT_REGS; i++)
- i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
- idt_conf_not_122_88[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 100MHz Refclk2 = 125MHz
- */
- if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
- printf("Setting refclk1:100 and refclk2:125\n");
- i2c_reg_write(idt_addr, 0x11, 0x10);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 125MHz Refclk2 = 125MHz
- */
- if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
- printf("Setting refclk1:125 and refclk2:125\n");
- i2c_reg_write(idt_addr, 0x10, 0x10);
- i2c_reg_write(idt_addr, 0x11, 0x10);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 125MHz Refclk2 = 100MHz
- */
- if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
- printf("Setting refclk1:125 and refclk2:100\n");
- i2c_reg_write(idt_addr, 0x10, 0x10);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 156.25MHz Refclk2 = 156.25MHz
- */
- if (refclk1 == SERDES_REFCLK_156_25 &&
- refclk2 == SERDES_REFCLK_156_25) {
- printf("Setting refclk1:156.25 and refclk2:156.25\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
- idt_conf_156_25[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 100MHz Refclk2 = 156.25MHz
- */
- if (refclk1 == SERDES_REFCLK_100 &&
- refclk2 == SERDES_REFCLK_156_25) {
- printf("Setting refclk1:100 and refclk2:156.25\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
- idt_conf_100_156_25[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 125MHz Refclk2 = 156.25MHz
- */
- if (refclk1 == SERDES_REFCLK_125 &&
- refclk2 == SERDES_REFCLK_156_25) {
- printf("Setting refclk1:125 and refclk2:156.25\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
- idt_conf_125_156_25[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 156.25MHz Refclk2 = 100MHz
- */
- if (refclk1 == SERDES_REFCLK_156_25 &&
- refclk2 == SERDES_REFCLK_100) {
- printf("Setting refclk1:156.25 and refclk2:100\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
- idt_conf_156_25_100[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 156.25MHz Refclk2 = 125MHz
- */
- if (refclk1 == SERDES_REFCLK_156_25 &&
- refclk2 == SERDES_REFCLK_125) {
- printf("Setting refclk1:156.25 and refclk2:125\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
- idt_conf_156_25_125[i][1]);
- }
-
- /* waiting for maximum of 1 second if PLL doesn'r get locked
- * initially. then check the status again.
- */
- if (check_pll_status(idt_addr)) {
- mdelay(1000);
- if (check_pll_status(idt_addr))
- return -1;
- }
-
- return 0;
-}
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h
deleted file mode 100644
index b1528e32669..00000000000
--- a/board/freescale/common/idt8t49n222a_serdes_clk.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Author: Shaveta Leekha <shaveta@freescale.com>
- */
-
-#ifndef __IDT8T49N222A_SERDES_CLK_H_
-#define __IDT8T49N222A_SERDES_CLK_H_ 1
-
-#include <common.h>
-#include <i2c.h>
-#include "qixis.h"
-#include "../b4860qds/b4860qds_qixis.h"
-#include <errno.h>
-
-#define NUM_IDT_REGS 23
-#define NUM_IDT_REGS_FEEDBACK 12
-#define NUM_IDT_REGS_156_25 11
-
-/* CLK */
-enum serdes_refclk {
- SERDES_REFCLK_100, /* refclk 100Mhz */
- SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
- SERDES_REFCLK_125, /* refclk 125Mhz */
- SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
- SERDES_REFCLK_NONE = -1,
-};
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- */
-static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
- {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
- {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
- {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
- {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
- {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
- {0x16, 0xA0} };
-
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
- */
-static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
- {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
- {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
- {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
- {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
- {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
- {0x16, 0xA0} };
-
-/* Reconfiguration values for some of IDT registers for
- * Output Refclks:
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- * and with feedback as 1
- */
-static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
- {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
- {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
- {0x14, 0x00}, {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 100MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 125MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 100MHz
- */
-static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 125MHz
- */
-static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
- enum serdes_refclk refclk1,
- enum serdes_refclk refclk2, u8 feedback);
-
-#endif /*__IDT8T49N222A_SERDES_CLK_H_ */
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 28/32] ppc: Drop idt8t49n222a_serdes_clk driver
2021-08-02 0:54 ` [PATCH v2 28/32] ppc: Drop idt8t49n222a_serdes_clk driver Simon Glass
@ 2021-08-06 21:22 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:22 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 196 bytes --]
On Sun, Aug 01, 2021 at 06:54:41PM -0600, Simon Glass wrote:
> This is not used. Drop it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 29/32] ppc: Drop t4qds and b4860qds references
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (27 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 28/32] ppc: Drop idt8t49n222a_serdes_clk driver Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:22 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 30/32] pci: Drop PCI_INDIRECT_BRIDGE Simon Glass
` (3 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Simon Glass, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
These boards have been removed. Drop the config file and other references.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
.azure-pipelines.yml | 4 +-
doc/board/freescale/b4860qds.rst | 453 -------------------------------
doc/board/freescale/index.rst | 1 -
include/configs/t4qds.h | 240 ----------------
4 files changed, 2 insertions(+), 696 deletions(-)
delete mode 100644 doc/board/freescale/b4860qds.rst
delete mode 100644 include/configs/t4qds.h
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index c088e1ac99b..6c7f1a0db03 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -413,11 +413,11 @@ jobs:
non_fsl_ppc:
BUILDMAN: "powerpc -x freescale"
mpc85xx_freescale:
- BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+ BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*"
t208xrdb_corenet_ds:
BUILDMAN: "t208xrdb corenet_ds"
fsl_ppc:
- BUILDMAN: "t4qds b4860qds mpc83xx&freescale"
+ BUILDMAN: "mpc83xx&freescale"
t102x:
BUILDMAN: "t102*"
p1_p2_rdb_pc:
diff --git a/doc/board/freescale/b4860qds.rst b/doc/board/freescale/b4860qds.rst
deleted file mode 100644
index de14d857b91..00000000000
--- a/doc/board/freescale/b4860qds.rst
+++ /dev/null
@@ -1,453 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-
-B4860QDS
-========
-
-The B4860QDS is a Freescale reference board that hosts the B4860 SoC
-(and variants).
-
-B4860 Overview
---------------
-The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
-StarCore and Power Architecture® cores. It targets the broadband wireless
-infrastructure and builds upon the proven success of the existing multicore
-DSPs and Power CPUs. It is designed to bolster the rapidly changing and
-expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
-
-The B4860 is a highly-integrated StarCore and Power Architecture processor that
-contains:
-
-* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
- clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
- for wireless base station applications
-* Four dual-thread e6500 Power Architecture processors organized in one
- cluster-each core runs up to 1.8 GHz
-* Two DDR3/3L controllers for high-speed, industry-standard memory interface
- each runs at up to 1866.67 MHz
-* MAPLE-B3 hardware acceleration-for forward error correction schemes including
- Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
- equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
- FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
- acceleration
-* CoreNet fabric that fully supports coherency using MESI protocol between the
- e6500 cores, SC3900 FVP cores, memories and external interfaces.
- CoreNet fabric interconnect runs at 667 MHz and supports coherent and
- non-coherent out of order transactions with prioritization and bandwidth
- allocation amongst CoreNet endpoints.
-* Data Path Acceleration Architecture, which includes the following:
-
- * Frame Manager (FMan), which supports in-line packet parsing and general
- classification to enable policing and QoS-based packet distribution
- * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
- of queue management, task management, load distribution, flow ordering,
- buffer management, and allocation tasks from the cores
- * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
- IPsec, SSL, and 802.16
- * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
- and outbound). Supports types 5, 6 (outbound only)
-
-* Large internal cache memory with snooping and stashing capabilities for
- bandwidth saving and high utilization of processor elements. The 9856-Kbyte
- internal memory space includes the following:
-
- * 32 Kbyte L1 ICache per e6500/SC3900 core
- * 32 Kbyte L1 DCache per e6500/SC3900 core
- * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
- * 2048 Kbyte unified L2 cache for the e6500 cluster
- * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
-
-* Sixteen 10-GHz SerDes lanes serving:
-
- * Two Serial RapidIO interfaces
- * Each supports up to 4 lanes and a total of up to 8 lanes
-
-* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
- glue-less antenna connection
-* Two 10-Gbit Ethernet controllers (10GEC)
-* Six 1G/2.5-Gbit Ethernet controllers for network communications
-* PCI Express controller
-* Debug (Aurora)
-* Two OCeaN DMAs
-* Various system peripherals
-* 182 32-bit timers
-
-B4860QDS Overview
------------------
-- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
- ECC, 4 GB of memory in two ranks of 2 GB.
-- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
- ECC, 2 GB of memory. Single rank.
-- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
- 16x16 switch VSC3316
-- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
- 8x8 switch VSC3308
-- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
- RS232 flat cable.
-- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
- copper connectors for Stand-alone mode and to the 1000Base-X over AMC
- MicroTCA connector ports 0 and 2 for AMC mode.
-- The B4860 configuration may be loaded from nine bits coded reset configuration
- reset source. The RCW source is set by appropriate DIP-switches.
-- 16-bit NOR Flash / PROMJet
-- QIXIS 8-bit NOR Flash Emulator
-- 8-bit NAND Flash
-- 24-bit SPI Flash
-- Long address I2C EEPROM
-- Available debug interfaces are:
-
- - On-board eCWTAP controller with ETH and USB I/F
- - JTAG/COP 16-pin header for any external TAP controller
- - External JTAG source over AMC to support B2B configuration
- - 70-pin Aurora debug connector
-
-- QIXIS (FPGA) logic:
- - 2 KB internal memory space including
-
-- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
- DDRCLK1,2 and RTCCLK.
-- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
- frequency - total four refclk, including CPRI clock scheme.
-
-
-B4420 Personality
------------------
-
-B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
-and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
-and reduced target frequencies.
-
-Key differences between B4860 and B4420
----------------------------------------
-
-B4420 has:
-
-1. Less e6500 cores: 1 cluster with 2 e6500 cores
-2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
-3. Single DDRC
-4. 2X 4 lane serdes
-5. 3 SGMII interfaces
-6. no sRIO
-7. no 10G
-
-B4860QDS Default Settings
--------------------------
-
-Switch Settings
-^^^^^^^^^^^^^^^
-
-.. code-block:: none
-
- SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
- SW2 ON ON ON ON ON ON OFF OFF
- SW3 OFF OFF OFF ON OFF OFF ON OFF
- SW5 OFF OFF OFF OFF OFF OFF ON ON
-
-Note:
-
-- PCIe slots modes: All the PCIe devices work as Root Complex.
-- Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-NAND boot::
-
- SW1 [1.1] = 0
- SW2 [1.1] = 1
- SW3 [1:4] = 0001
-
-NOR boot::
-
- SW1 [1.1] = 1
- SW2 [1.1] = 0
- SW3 [1:4] = 1000
-
-B4420QDS Default Settings
--------------------------
-
-Switch Settings
-^^^^^^^^^^^^^^^
-
-.. code-block:: none
-
- SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
- SW2 ON OFF ON OFF ON ON OFF OFF
- SW3 OFF OFF OFF ON OFF OFF ON OFF
- SW5 OFF OFF OFF OFF OFF OFF ON ON
-
-Note:
-
-- PCIe slots modes: All the PCIe devices work as Root Complex.
-- Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-NAND boot::
-
- SW1 [1.1] = 0
- SW2 [1.1] = 1
- SW3 [1:4] = 0001
-
-NOR boot::
-
- SW1 [1.1] = 1
- SW2 [1.1] = 0
- SW3 [1:4] = 1000
-
-Memory map on B4860QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-============= ============= =============== =======
-Start Address End Address Description Size
-============= ============= =============== =======
-0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
-0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
-0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
-0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
-0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
-0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
-0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
-0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
-0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
-0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
-0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
-0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
-0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
-0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
-0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
-0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
-0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
-0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
-0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
-0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
-============= ============= =============== =======
-
-Memory map on B4420QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-============= ============= =============== =======
-Start Address End Address Description Size
-============= ============= =============== =======
-0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
-0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
-0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
-0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
-0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
-0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
-0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
-0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
-0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
-0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
-0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
-0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
-0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
-0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
-0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
-0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
-0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
-0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
-0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
-============= ============= =============== =======
-
-NOR Flash memory Map on B4860 and B4420QDS
-------------------------------------------
-
-============= ============= ============================== =========
- Start End Definition Size
-============= ============= ============================== =========
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
-0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
-0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
-0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
-0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
-0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
-0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
-0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
-0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
-0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
-0xEC000000 0xEC01FFFF RCW (current bank) 128KB
-============= ============= ============================== =========
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to both B4860QDS and B4420QDS.
-
-U-Boot environment variable hwconfig
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The default hwconfig is:
-
-.. code-block:: none
-
- hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
-
-Note: For USB gadget set "dr_mode=peripheral"
-
-FMAN Ucode versions
-^^^^^^^^^^^^^^^^^^^
-
-fsl_fman_ucode_B4860_106_3_6.bin
-
-Switching to alternate bank
-^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Commands for switching to alternate bank.
-
-1. To change from vbank0 to vbank2
-
-.. code-block:: none
-
- => qixis_reset altbank (it will boot using vbank2)
-
-2. To change from vbank2 to vbank0
-
-.. code-block:: none
-
- => qixis reset (it will boot using vbank0)
-
-To change personality of board
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-For changing personality from B4860 to B4420
-
-1. Boot from vbank0
-2. Flash vbank2 with b4420 rcw and U-Boot
-3. Give following commands to uboot prompt
-
-.. code-block:: none
-
- => mw.b ffdf0040 0x30;
- => mw.b ffdf0010 0x00;
- => mw.b ffdf0062 0x02;
- => mw.b ffdf0050 0x02;
- => mw.b ffdf0010 0x30;
- => reset
-
-Note:
-
-- Power off cycle will lead to default switch settings.
-- 0xffdf0000 is the address of the QIXIS FPGA.
-
-Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-To change from NOR to NAND boot give following command on uboot prompt
-
-.. code-block:: none
-
- => mw.b ffdf0040 0x30
- => mw.b ffdf0010 0x00
- => mw.b 0xffdf0050 0x08
- => mw.b 0xffdf0060 0x82
- => mw.b ffdf0061 0x00
- => mw.b ffdf0010 0x30
- => reset
-
-To change from NAND to NOR boot give following command on uboot prompt:
-
-.. code-block:: none
-
- => mw.b ffdf0040 0x30
- => mw.b ffdf0010 0x00
- => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
- => mw.b 0xffdf0060 0x12
- => mw.b ffdf0061 0x01
- => mw.b ffdf0010 0x30
- => reset
-
-Note:
-
-- Power off cycle will lead to default switch settings.
-- 0xffdf0000 is the address of the QIXIS FPGA.
-
-Ethernet interfaces for B4860QDS
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Serdes protocosl tested:
-* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
-* 0x2a, 0xb2 (serdes1, serdes2)
-
-When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
-SGMII on SGMII riser card.
-
-Under U-Boot these network interfaces are recognized as::
-
- FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
-
-On Linux the interfaces are renamed as::
-
- eth2 -> fm1-gb2
- eth3 -> fm1-gb3
- eth4 -> fm1-gb4
- eth5 -> fm1-gb5
-
-RCW and Ethernet interfaces for B4420QDS
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Serdes protocosl tested:
-* 0x18, 0x9e (serdes1, serdes2)
-
-Under U-Boot these network interfaces are recognized as::
-
- FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
-
-On Linux the interfaces are renamed as::
-
- eth2 -> fm1-gb2
- eth3 -> fm1-gb3
-
-NAND boot with 2 Stage boot loader
-----------------------------------
-PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
-SPL further initialise DDR using SPD and environment variables and copy
-U-Boot(768 KB) from flash to DDR.
-Finally SPL transer control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework during boot:
-
-+----------------------------------------------+
-|Area | Address |
-+----------------------------------------------+
-|Secure boot | 0xFFFC0000 (32KB) |
-|headers | |
-+----------------------------------------------+
-|GD, BD | 0xFFFC8000 (4KB) |
-+----------------------------------------------+
-|ENV | 0xFFFC9000 (8KB) |
-+----------------------------------------------+
-|HEAP | 0xFFFCB000 (30KB) |
-+----------------------------------------------+
-|STACK | 0xFFFD8000 (22KB) |
-+----------------------------------------------+
-|U-Boot SPL | 0xFFFD8000 (160KB) |
-+----------------------------------------------+
-
-NAND Flash memory Map on B4860 and B4420QDS
--------------------------------------------
-
-============= ============= ============================= =====
-Start End Definition Size
-============= ============= ============================= =====
-0x000000 0x0FFFFF U-Boot 1MB
-0x140000 0x15FFFF U-Boot env 128KB
-0x1A0000 0x1BFFFF FMAN Ucode 128KB
-============= ============= ============================= =====
diff --git a/doc/board/freescale/index.rst b/doc/board/freescale/index.rst
index 313cf409a69..bddc6c6c2c7 100644
--- a/doc/board/freescale/index.rst
+++ b/doc/board/freescale/index.rst
@@ -6,7 +6,6 @@ Freescale
.. toctree::
:maxdepth: 2
- b4860qds
imx8mm_evk
imx8mn_evk
imx8mp_evk
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
deleted file mode 100644
index b62ddc7075b..00000000000
--- a/include/configs/t4qds.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * Corenet DS style board configuration file
- */
-#ifndef __T4QDS_H
-#define __T4QDS_H
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-
-#define CONFIG_DDR_SPD
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#endif /* __CONFIG_H */
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 29/32] ppc: Drop t4qds and b4860qds references
2021-08-02 0:54 ` [PATCH v2 29/32] ppc: Drop t4qds and b4860qds references Simon Glass
@ 2021-08-06 21:22 ` Tom Rini
0 siblings, 0 replies; 73+ messages in thread
From: Tom Rini @ 2021-08-06 21:22 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Andy Fleming, Mario Six, Priyanka Jain,
Stefan Roese, Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 244 bytes --]
On Sun, Aug 01, 2021 at 06:54:42PM -0600, Simon Glass wrote:
> These boards have been removed. Drop the config file and other references.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 30/32] pci: Drop PCI_INDIRECT_BRIDGE
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (28 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 29/32] ppc: Drop t4qds and b4860qds references Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-09-14 1:03 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 31/32] pci: Drop DM_PCI Simon Glass
` (2 subsequent siblings)
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
This does not work with driver model so can be removed.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
README | 3 --
drivers/pci/Makefile | 1 -
drivers/pci/pci_indirect.c | 71 -----------------------------
include/configs/MPC8349EMDS.h | 4 --
include/configs/MPC8349EMDS_SDRAM.h | 4 --
include/configs/MPC837XERDB.h | 2 -
include/configs/MPC8540ADS.h | 1 -
include/configs/MPC8560ADS.h | 1 -
include/pci.h | 4 --
scripts/config_whitelist.txt | 1 -
10 files changed, 92 deletions(-)
delete mode 100644 drivers/pci/pci_indirect.c
diff --git a/README b/README
index 4fdc49fbb9c..daa274d0fc7 100644
--- a/README
+++ b/README
@@ -2776,9 +2776,6 @@ Low Level (hardware related) configuration options:
CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
-- CONFIG_PCI_INDIRECT_BRIDGE:
- Enable support for indirect PCI bridges.
-
- CONFIG_SYS_SRIO:
Chip has SRIO or not
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index bdfdec98a08..4a131bf5ca4 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c
deleted file mode 100644
index 6134c22d1bc..00000000000
--- a/drivers/pci/pci_indirect.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Support for indirect PCI bridges.
- *
- * Copyright (C) 1998 Gabriel Paubert.
- */
-
-#include <common.h>
-
-#if !defined(__I386__) && !defined(CONFIG_DM_PCI)
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#define cfg_read(val, addr, type, op) *val = op((type)(addr))
-#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
-
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
-static int \
-indirect_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, type val) \
-{ \
- u32 b, d,f; \
- b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
- b = b - hose->first_busno; \
- dev = PCI_BDF(b, d, f); \
- *(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \
- sync(); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
- return 0; \
-}
-#else
-#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
-static int \
-indirect_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, type val) \
-{ \
- u32 b, d,f; \
- b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
- b = b - hose->first_busno; \
- dev = PCI_BDF(b, d, f); \
- out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
- return 0; \
-}
-#endif
-
-INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
-INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
-INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
-INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
-INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
-INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
-
-void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
-{
- pci_set_ops(hose,
- indirect_read_config_byte,
- indirect_read_config_word,
- indirect_read_config_dword,
- indirect_write_config_byte,
- indirect_write_config_word,
- indirect_write_config_dword);
-
- hose->cfg_addr = (unsigned int *) cfg_addr;
- hose->cfg_data = (unsigned char *) cfg_data;
-}
-
-#endif /* !__I386__ */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index d6ae419456a..b4e1cae8938 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -303,10 +303,6 @@
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 8ebca99d98b..7924cbc8a3e 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -360,10 +360,6 @@
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 0a136b4f92f..a13b178d6af 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -255,8 +255,6 @@
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index ac9afa179a5..549fbfa65c7 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -26,7 +26,6 @@
#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
#endif
-#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 02aeb6f3d53..5254936a4b2 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -27,7 +27,6 @@
* assume U-Boot is less than 0.5MB
*/
-#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
diff --git a/include/pci.h b/include/pci.h
index 2c2930e7a74..0fc22adffd0 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -656,10 +656,6 @@ struct pci_controller {
struct pci_region *pci_mem, *pci_io, *pci_prefetch;
};
-#ifdef CONFIG_PCI_INDIRECT_BRIDGE
-extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
-#endif
-
#if defined(CONFIG_DM_PCI_COMPAT)
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e6bddf15b88..33345358085 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1091,7 +1091,6 @@ CONFIG_PCI_CONFIG_HOST_BRIDGE
CONFIG_PCI_EHCI_DEVICE
CONFIG_PCI_EHCI_DEVNO
CONFIG_PCI_GT64120
-CONFIG_PCI_INDIRECT_BRIDGE
CONFIG_PCI_IO_BUS
CONFIG_PCI_IO_PHYS
CONFIG_PCI_IO_SIZE
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 31/32] pci: Drop DM_PCI
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (29 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 30/32] pci: Drop PCI_INDIRECT_BRIDGE Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-09-14 1:03 ` Tom Rini
2021-08-02 0:54 ` [PATCH v2 32/32] pci: Drop migration method Simon Glass
2021-08-07 14:14 ` [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
This option has not effect now. Drop it, using PCI instead where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/Kconfig | 1 -
arch/arm/Kconfig | 2 +-
arch/arm/mach-imx/mx6/Kconfig | 2 +-
arch/mips/Kconfig | 2 +-
board/emulation/qemu-riscv/Kconfig | 1 -
board/socionext/developerbox/Kconfig | 1 -
common/Kconfig | 1 -
drivers/gpio/Kconfig | 2 +-
drivers/i2c/Makefile | 2 +-
drivers/net/Kconfig | 6 ++---
drivers/net/mscc_eswitch/Kconfig | 2 +-
drivers/pci/Kconfig | 40 +++-------------------------
drivers/spi/Kconfig | 2 +-
drivers/virtio/Kconfig | 2 +-
test/dm/Makefile | 2 +-
15 files changed, 14 insertions(+), 54 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index b6f9e177b64..8f8daadcf92 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -182,7 +182,6 @@ config X86
select SUPPORT_TPL
select CREATE_ARCH_SYMLINK
select DM
- select DM_PCI
select HAVE_ARCH_IOMAP
select HAVE_PRIVATE_LIBGCC
select OF_CONTROL
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2b7b6257057..817f5fe4781 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1669,7 +1669,7 @@ config TARGET_SL28
select DM_SPI_FLASH
select DM_ETH
select DM_MDIO
- select DM_PCI
+ select PCI
select DM_RNG
select DM_RTC
select DM_SCSI
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 789a50d4e92..515c3020faa 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -237,7 +237,7 @@ config TARGET_KOSAGI_NOVENA
select DM_ETH
select DM_GPIO
select DM_MMC
- select DM_PCI
+ select PCI
select DM_SCSI
select DM_VIDEO
select OF_CONTROL
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 6b1f10d9a0e..a5cec387a04 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -17,7 +17,7 @@ config TARGET_MALTA
select BOARD_EARLY_INIT_R
select DM
select DM_SERIAL
- select DM_PCI
+ select PCI
select DM_ETH
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 0818048ba64..46b01c2049a 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -51,7 +51,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply E1000
imply NVME
imply PCI
- imply DM_PCI
imply PCIE_ECAM_GENERIC
imply SCSI
imply DM_SCSI
diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig
index 706b8dc0f1c..c181d26a44a 100644
--- a/board/socionext/developerbox/Kconfig
+++ b/board/socionext/developerbox/Kconfig
@@ -7,7 +7,6 @@ choice
config TARGET_DEVELOPERBOX
bool "Socionext DeveloperBox"
select PCI
- select DM_PCI
select PCIE_ECAM_SYNQUACER
select SYS_DISABLE_DCACHE_OPS
select OF_BOARD_SETUP
diff --git a/common/Kconfig b/common/Kconfig
index 2ab20a6c85b..ee14d3ad5bf 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -551,7 +551,6 @@ config MISC_INIT_R
config PCI_INIT_R
bool "Enumerate PCI buses during init"
depends on PCI
- default y if !DM_PCI
help
With this option U-Boot will call pci_init() soon after relocation,
which will enumerate PCI buses. This is needed, for instance, in the
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 09695f6c2b0..b2784915f19 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -348,7 +348,7 @@ config PIC32_GPIO
config OCTEON_GPIO
bool "Octeon II/III/TX/TX2 GPIO driver"
- depends on DM_GPIO && DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ depends on DM_GPIO && PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
default y
help
Add support for the Marvell Octeon GPIO driver. This is used with
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index c2eb24e0f7b..c16ebb24913 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
-ifdef CONFIG_DM_PCI
+ifdef CONFIG_PCI
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
endif
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 8b10148579e..0a5e0ac8744 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -222,7 +222,6 @@ config DWC_ETH_QOS_TEGRA186
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
- depends on (DM_ETH && DM_PCI) || !DM_ETH
help
This driver supports Intel(R) PRO/1000 gigabit ethernet family of
adapters. For more information on how to identify your adapter, go
@@ -506,7 +505,7 @@ config OCTEONTX2_CGX_INTF
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
- depends on DM_ETH && DM_PCI
+ depends on DM_ETH
select PHYLIB
help
This MAC is present in Intel Platform Controller Hub EG20T. It
@@ -606,7 +605,6 @@ source "drivers/net/ti/Kconfig"
config TULIP
bool "DEC Tulip DC2114x Ethernet support"
- depends on (DM_ETH && DM_PCI) || !DM_ETH
help
This driver supports DEC DC2114x Fast ethernet chips.
@@ -791,7 +789,7 @@ config HIGMACV300_ETH
config FSL_ENETC
bool "NXP ENETC Ethernet controller"
- depends on DM_PCI && DM_ETH && DM_MDIO
+ depends on DM_ETH && DM_MDIO
help
This driver supports the NXP ENETC Ethernet controller found on some
of the NXP SoCs.
diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig
index ccf7822dbe7..930d2ef1130 100644
--- a/drivers/net/mscc_eswitch/Kconfig
+++ b/drivers/net/mscc_eswitch/Kconfig
@@ -39,7 +39,7 @@ config MSCC_SERVAL_SWITCH
config MSCC_FELIX_SWITCH
bool "Felix switch driver"
- depends on DM_DSA && DM_PCI
+ depends on DM_DSA
select FSL_ENETC
help
This driver supports the Ethernet switch integrated in the
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 2ef4d46797e..e4123ba820f 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -2,35 +2,26 @@ menuconfig PCI
bool "PCI support"
depends on DM
default y if PPC
- select DM_PCI
help
Enable support for PCI (Peripheral Interconnect Bus), a type of bus
used on some devices to allow the CPU to communicate with its
peripherals.
-config DM_PCI
- bool
- help
- Use driver model for PCI. Driver model is the new method for
- orgnising devices in U-Boot. For PCI, driver model keeps track of
- available PCI devices, allows scanning of PCI buses and provides
- device configuration support.
+ This subsystem requires driver model.
if PCI
config DM_PCI_COMPAT
bool "Enable compatible functions for PCI"
- depends on DM_PCI
help
Enable compatibility functions for PCI so that old code can be used
- with CONFIG_DM_PCI enabled. This should be used as an interim
+ with CONFIG_PCI enabled. This should be used as an interim
measure when porting a board to use driver model for PCI. Once the
board is fully supported, this option should be disabled.
config PCI_AARDVARK
bool "Enable Aardvark PCIe driver"
default n
- depends on DM_PCI
depends on DM_GPIO
depends on ARMADA_3700
help
@@ -40,14 +31,12 @@ config PCI_AARDVARK
config PCI_PNP
bool "Enable Plug & Play support for PCI"
- depends on PCI || DM_PCI
default y
help
Enable PCI memory and I/O space resource allocation and assignment.
config PCI_REGION_MULTI_ENTRY
bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
- depends on PCI || DM_PCI
default n
help
Enable PCI memory regions to be of multiple entry. Multiple entry
@@ -57,7 +46,6 @@ config PCI_REGION_MULTI_ENTRY
config PCI_MAP_SYSTEM_MEMORY
bool "Map local system memory from a virtual base address"
- depends on PCI || DM_PCI
depends on MIPS
default n
help
@@ -70,7 +58,6 @@ config PCI_MAP_SYSTEM_MEMORY
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
- depends on PCI || DM_PCI
default n
help
Say Y here if you want to enable PCI Single Root I/O Virtualization
@@ -80,7 +67,6 @@ config PCI_SRIOV
config PCI_ARID
bool "Enable Alternate Routing-ID support for PCI"
- depends on PCI || DM_PCI
default n
help
Say Y here if you want to enable Alternate Routing-ID capability
@@ -90,7 +76,6 @@ config PCI_ARID
config PCIE_ECAM_GENERIC
bool "Generic ECAM-based PCI host controller support"
default n
- depends on DM_PCI
help
Say Y here if you want to enable support for generic ECAM-based
PCIe host controllers, such as the one emulated by QEMU.
@@ -98,7 +83,6 @@ config PCIE_ECAM_GENERIC
config PCIE_ECAM_SYNQUACER
bool "SynQuacer ECAM-based PCI host controller support"
default n
- depends on DM_PCI
select PCI_INIT_R
select PCI_REGION_MULTI_ENTRY
help
@@ -109,14 +93,12 @@ config PCIE_ECAM_SYNQUACER
config PCI_PHYTIUM
bool "Phytium PCIe support"
- depends on DM_PCI
help
Say Y here if you want to enable PCIe controller support on
Phytium SoCs.
config PCIE_DW_MVEBU
bool "Enable Armada-8K PCIe driver (DesignWare core)"
- depends on DM_PCI
depends on ARMADA_8K
help
Say Y here if you want to enable PCIe controller support on
@@ -135,7 +117,6 @@ config PCIE_DW_SIFIVE
config PCIE_FSL
bool "FSL PowerPC PCIe support"
- depends on DM_PCI
help
Say Y here if you want to enable PCIe controller support on FSL
PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
@@ -143,14 +124,12 @@ config PCIE_FSL
config PCI_MPC85XX
bool "MPC85XX PowerPC PCI support"
- depends on DM_PCI
help
Say Y here if you want to enable PCI controller support on FSL
PowerPC MPC85xx SoC.
config PCI_RCAR_GEN2
bool "Renesas RCar Gen2 PCIe driver"
- depends on DM_PCI
depends on RCAR_32
help
Say Y here if you want to enable PCIe controller support on
@@ -159,7 +138,6 @@ config PCI_RCAR_GEN2
config PCI_RCAR_GEN3
bool "Renesas RCar Gen3 PCIe driver"
- depends on DM_PCI
depends on RCAR_GEN3
help
Say Y here if you want to enable PCIe controller support on
@@ -167,7 +145,7 @@ config PCI_RCAR_GEN3
config PCI_SANDBOX
bool "Sandbox PCI support"
- depends on SANDBOX && DM_PCI
+ depends on SANDBOX
help
Support PCI on sandbox, as an emulated bus. This permits testing of
PCI feature such as bus scanning, device configuration and device
@@ -202,7 +180,6 @@ config PCIE_OCTEON
config PCI_XILINX
bool "Xilinx AXI Bridge for PCI Express"
- depends on DM_PCI
help
Enable support for the Xilinx AXI bridge for PCI express, an IP block
which can be used on some generations of Xilinx FPGAs.
@@ -213,7 +190,6 @@ config PCIE_LAYERSCAPE
config PCIE_LAYERSCAPE_RC
bool "Layerscape PCIe Root Complex mode support"
- depends on DM_PCI
select PCIE_LAYERSCAPE
help
Enable Layerscape PCIe Root Complex mode driver support. The Layerscape
@@ -235,7 +211,6 @@ config PCI_IOMMU_EXTRA_MAPPINGS
config PCIE_LAYERSCAPE_EP
bool "Layerscape PCIe Endpoint mode support"
- depends on DM_PCI
select PCIE_LAYERSCAPE
select PCI_ENDPOINT
help
@@ -246,7 +221,6 @@ config PCIE_LAYERSCAPE_EP
config PCIE_LAYERSCAPE_GEN4
bool "Layerscape Gen4 PCIe support"
- depends on DM_PCI
help
Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or
several PCIe controllers. The PCIe controller can work in RC or
@@ -279,14 +253,12 @@ config FSL_PCIE_EP_COMPAT
config PCIE_INTEL_FPGA
bool "Intel FPGA PCIe support"
- depends on DM_PCI
help
Say Y here if you want to enable PCIe controller support on Intel
FPGA, example Stratix 10.
config PCIE_IPROC
bool "Iproc PCIe support"
- depends on DM_PCI
help
Broadcom iProc PCIe controller driver.
Say Y here if you want to enable Broadcom iProc PCIe controller,
@@ -294,7 +266,6 @@ config PCIE_IPROC
config PCI_MVEBU
bool "Enable Armada XP/38x PCIe driver"
depends on ARCH_MVEBU
- select DM_PCI
select MISC
help
Say Y here if you want to enable PCIe controller support on
@@ -302,7 +273,6 @@ config PCI_MVEBU
config PCIE_DW_COMMON
bool
- select DM_PCI
config PCI_KEYSTONE
bool "TI Keystone PCIe controller"
@@ -312,7 +282,6 @@ config PCI_KEYSTONE
config PCIE_MEDIATEK
bool "MediaTek PCIe Gen2 controller"
- depends on DM_PCI
depends on ARCH_MEDIATEK
help
Say Y here if you want to enable Gen2 PCIe controller,
@@ -329,7 +298,6 @@ config PCIE_DW_MESON
config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"
depends on ARCH_ROCKCHIP
- select DM_PCI
select PHY_ROCKCHIP_PCIE
default y if ROCKCHIP_RK3399
help
@@ -347,7 +315,6 @@ config PCIE_DW_ROCKCHIP
config PCI_BRCMSTB
bool "Broadcom STB PCIe controller"
- depends on DM_PCI
depends on ARCH_BCM283X
help
Say Y here if you want to enable support for PCIe controller
@@ -357,7 +324,6 @@ config PCI_BRCMSTB
config PCIE_UNIPHIER
bool "Socionext UniPhier PCIe driver"
- depends on DM_PCI
depends on ARCH_UNIPHIER
select PHY_UNIPHIER_PCIE
help
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5c2a60a2142..db236591f64 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -271,7 +271,7 @@ config NXP_FSPI
config OCTEON_SPI
bool "Octeon SPI driver"
- depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2
help
Enable the Octeon SPI driver. This driver can be used to
access the SPI NOR flash on Octeon II/III and OcteonTX/TX2
diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig
index 18356070833..863c3fbe029 100644
--- a/drivers/virtio/Kconfig
+++ b/drivers/virtio/Kconfig
@@ -31,7 +31,7 @@ config VIRTIO_MMIO
config VIRTIO_PCI
bool "PCI driver for virtio devices"
- depends on DM_PCI
+ depends on PCI
select VIRTIO
help
This driver provides support for virtio based paravirtual device
diff --git a/test/dm/Makefile b/test/dm/Makefile
index d5c42e7643e..958d7df94a4 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -64,7 +64,7 @@ obj-y += of_extra.o
obj-$(CONFIG_OSD) += osd.o
obj-$(CONFIG_DM_VIDEO) += panel.o
obj-$(CONFIG_EFI_PARTITION) += part.o
-obj-$(CONFIG_DM_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_P2SB) += p2sb.o
obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o
obj-$(CONFIG_PCH) += pch.o
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v2 32/32] pci: Drop migration method
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (30 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 31/32] pci: Drop DM_PCI Simon Glass
@ 2021-08-02 0:54 ` Simon Glass
2021-08-06 21:22 ` Tom Rini
2021-08-07 14:14 ` [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-02 0:54 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Tom Rini, Simon Glass
Migration is complete. Drop the message.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
doc/develop/driver-model/migration.rst | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index 8d0bb7635b5..8bb8601c582 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -75,15 +75,6 @@ Partially converted::
* Status: In progress
* Deadline: 2019.07
-CONFIG_DM_PCI
--------------
-Deadline: 2019.07
-
-The PCI subsystem has supported driver model since mid 2015. Maintainers should
-submit patches switching over to using CONFIG_DM_PCI and other base driver
-model options in time for inclusion in the 2019.07 release.
-
-
CONFIG_DM_VIDEO
---------------
Deadline: 2019.07
--
2.32.0.554.ge1b32706d8-goog
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [PATCH v2 00/32] pci: Drop all pre-driver model code
2021-08-02 0:54 [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
` (31 preceding siblings ...)
2021-08-02 0:54 ` [PATCH v2 32/32] pci: Drop migration method Simon Glass
@ 2021-08-07 14:14 ` Simon Glass
2021-08-07 14:32 ` Tom Rini
32 siblings, 1 reply; 73+ messages in thread
From: Simon Glass @ 2021-08-07 14:14 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Tom Rini, Albert Aribaud, Andy Fleming, Joe Hershberger,
Marek Vasut, Mario Six, Oleksandr Zhadan and Michael Durrant,
Pavel Herrmann, Priyanka Jain, Rob Herring, Stefan Roese,
Stefano Babic, Wolfgang Denk
Hi Tom,
On Sun, 1 Aug 2021 at 18:54, Simon Glass <sjg@chromium.org> wrote:
>
> The hard work to actually enable DM_PCI everywhere was done recently. This
> series attempts to drop most of the code that it no-longer needed now that
> PCI has been converted to driver model.
>
> It also drops the UCP1020 board since it has various unique build issues.
> It doesn't even support driver model so it seems reasonable to just remove
> it.
>
> The DM_PCI option disappears and only PCI is left.
>
> We can drop about 50 ad-hoc CONFIGs also, but this series doesn't do that
> since it is probably best done when the CONFIGs are resynced. It does
> include a CONFIG resync patch which can be dropped if that is done
> separately.
>
> Changes in v2:
> - Update to mention DM_PCI instead
> - Fix tag to 'mips' from 'ppc'
>
> Simon Glass (32):
> pci: Drop old code from pci command
> ppc: Remove UCP1020 board
> pci: Drop old code from header file
> pci: Remove guard around compatibility functions
> pci: Drop DM_PCI check from fdtdec
> pci: Drop DM_PCI check from pci_common
> ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID
> pci: powerpc: Drop old code
> pci: freescale: Drop old code
> pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci()
> ppc: Drop DM_PCI from config files
> pci: acpi: Drop DM_PCI check from ahci
> pci: usb: Drop DM_PCI from ohci
> ppc: malta: Drop use of DM_PCI
> ppc: socrates: Drop use of DM_PCI
> pci: gt64120: Drop use of DM_PCI
> pci: msc01: Drop use of DM_PCI
> pci: imx: Drop use of DM_PCI
> pci: scsi: pci: Drop DM_PCI check from scsi
> pci: Drop DM_PCI check from bios_emul
> net: Drop DM_PCI check from designware driver
> pci: imx: Drop DM_PCI check from cpu driver
> pci: arm: mvebu: Drop DM_PCI check from
> pci: sata_sil: Drop DM_PCI checks
> distro_bootcmd: Drop DM_PCI check
> pci: Drop pci_init_board()
> pci: ppc: Drop ftpci100 driver
> ppc: Drop idt8t49n222a_serdes_clk driver
> ppc: Drop t4qds and b4860qds references
> pci: Drop PCI_INDIRECT_BRIDGE
> pci: Drop DM_PCI
> pci: Drop migration method
>
Thanks for fixing up and applying most of this.
Shall I rebase and send the remaining patches as a new series?
Regards,
Simon
^ permalink raw reply [flat|nested] 73+ messages in thread* Re: [PATCH v2 00/32] pci: Drop all pre-driver model code
2021-08-07 14:14 ` [PATCH v2 00/32] pci: Drop all pre-driver model code Simon Glass
@ 2021-08-07 14:32 ` Tom Rini
2021-08-07 14:39 ` Simon Glass
0 siblings, 1 reply; 73+ messages in thread
From: Tom Rini @ 2021-08-07 14:32 UTC (permalink / raw)
To: Simon Glass, Oleksandr G Zhadan
Cc: U-Boot Mailing List, Albert Aribaud, Andy Fleming,
Joe Hershberger, Marek Vasut, Mario Six,
Oleksandr Zhadan and Michael Durrant, Pavel Herrmann,
Priyanka Jain, Rob Herring, Stefan Roese, Stefano Babic,
Wolfgang Denk
[-- Attachment #1: Type: text/plain, Size: 2566 bytes --]
On Sat, Aug 07, 2021 at 08:14:31AM -0600, Simon Glass wrote:
> Hi Tom,
>
> On Sun, 1 Aug 2021 at 18:54, Simon Glass <sjg@chromium.org> wrote:
> >
> > The hard work to actually enable DM_PCI everywhere was done recently. This
> > series attempts to drop most of the code that it no-longer needed now that
> > PCI has been converted to driver model.
> >
> > It also drops the UCP1020 board since it has various unique build issues.
> > It doesn't even support driver model so it seems reasonable to just remove
> > it.
> >
> > The DM_PCI option disappears and only PCI is left.
> >
> > We can drop about 50 ad-hoc CONFIGs also, but this series doesn't do that
> > since it is probably best done when the CONFIGs are resynced. It does
> > include a CONFIG resync patch which can be dropped if that is done
> > separately.
> >
> > Changes in v2:
> > - Update to mention DM_PCI instead
> > - Fix tag to 'mips' from 'ppc'
> >
> > Simon Glass (32):
> > pci: Drop old code from pci command
> > ppc: Remove UCP1020 board
> > pci: Drop old code from header file
> > pci: Remove guard around compatibility functions
> > pci: Drop DM_PCI check from fdtdec
> > pci: Drop DM_PCI check from pci_common
> > ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID
> > pci: powerpc: Drop old code
> > pci: freescale: Drop old code
> > pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci()
> > ppc: Drop DM_PCI from config files
> > pci: acpi: Drop DM_PCI check from ahci
> > pci: usb: Drop DM_PCI from ohci
> > ppc: malta: Drop use of DM_PCI
> > ppc: socrates: Drop use of DM_PCI
> > pci: gt64120: Drop use of DM_PCI
> > pci: msc01: Drop use of DM_PCI
> > pci: imx: Drop use of DM_PCI
> > pci: scsi: pci: Drop DM_PCI check from scsi
> > pci: Drop DM_PCI check from bios_emul
> > net: Drop DM_PCI check from designware driver
> > pci: imx: Drop DM_PCI check from cpu driver
> > pci: arm: mvebu: Drop DM_PCI check from
> > pci: sata_sil: Drop DM_PCI checks
> > distro_bootcmd: Drop DM_PCI check
> > pci: Drop pci_init_board()
> > pci: ppc: Drop ftpci100 driver
> > ppc: Drop idt8t49n222a_serdes_clk driver
> > ppc: Drop t4qds and b4860qds references
> > pci: Drop PCI_INDIRECT_BRIDGE
> > pci: Drop DM_PCI
> > pci: Drop migration method
> >
>
> Thanks for fixing up and applying most of this.
>
> Shall I rebase and send the remaining patches as a new series?
No need. I'll pick up the rest of the series when I get the UCP1020
update patch as well.
--
Tom
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* Re: [PATCH v2 00/32] pci: Drop all pre-driver model code
2021-08-07 14:32 ` Tom Rini
@ 2021-08-07 14:39 ` Simon Glass
0 siblings, 0 replies; 73+ messages in thread
From: Simon Glass @ 2021-08-07 14:39 UTC (permalink / raw)
To: Tom Rini
Cc: Oleksandr G Zhadan, U-Boot Mailing List, Albert Aribaud,
Andy Fleming, Joe Hershberger, Marek Vasut, Mario Six,
Oleksandr Zhadan and Michael Durrant, Pavel Herrmann,
Priyanka Jain, Rob Herring, Stefan Roese, Stefano Babic,
Wolfgang Denk
On Sat, 7 Aug 2021 at 08:32, Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Aug 07, 2021 at 08:14:31AM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Sun, 1 Aug 2021 at 18:54, Simon Glass <sjg@chromium.org> wrote:
> > >
> > > The hard work to actually enable DM_PCI everywhere was done recently. This
> > > series attempts to drop most of the code that it no-longer needed now that
> > > PCI has been converted to driver model.
> > >
> > > It also drops the UCP1020 board since it has various unique build issues.
> > > It doesn't even support driver model so it seems reasonable to just remove
> > > it.
> > >
> > > The DM_PCI option disappears and only PCI is left.
> > >
> > > We can drop about 50 ad-hoc CONFIGs also, but this series doesn't do that
> > > since it is probably best done when the CONFIGs are resynced. It does
> > > include a CONFIG resync patch which can be dropped if that is done
> > > separately.
> > >
> > > Changes in v2:
> > > - Update to mention DM_PCI instead
> > > - Fix tag to 'mips' from 'ppc'
> > >
> > > Simon Glass (32):
> > > pci: Drop old code from pci command
> > > ppc: Remove UCP1020 board
> > > pci: Drop old code from header file
> > > pci: Remove guard around compatibility functions
> > > pci: Drop DM_PCI check from fdtdec
> > > pci: Drop DM_PCI check from pci_common
> > > ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID
> > > pci: powerpc: Drop old code
> > > pci: freescale: Drop old code
> > > pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci()
> > > ppc: Drop DM_PCI from config files
> > > pci: acpi: Drop DM_PCI check from ahci
> > > pci: usb: Drop DM_PCI from ohci
> > > ppc: malta: Drop use of DM_PCI
> > > ppc: socrates: Drop use of DM_PCI
> > > pci: gt64120: Drop use of DM_PCI
> > > pci: msc01: Drop use of DM_PCI
> > > pci: imx: Drop use of DM_PCI
> > > pci: scsi: pci: Drop DM_PCI check from scsi
> > > pci: Drop DM_PCI check from bios_emul
> > > net: Drop DM_PCI check from designware driver
> > > pci: imx: Drop DM_PCI check from cpu driver
> > > pci: arm: mvebu: Drop DM_PCI check from
> > > pci: sata_sil: Drop DM_PCI checks
> > > distro_bootcmd: Drop DM_PCI check
> > > pci: Drop pci_init_board()
> > > pci: ppc: Drop ftpci100 driver
> > > ppc: Drop idt8t49n222a_serdes_clk driver
> > > ppc: Drop t4qds and b4860qds references
> > > pci: Drop PCI_INDIRECT_BRIDGE
> > > pci: Drop DM_PCI
> > > pci: Drop migration method
> > >
> >
> > Thanks for fixing up and applying most of this.
> >
> > Shall I rebase and send the remaining patches as a new series?
>
> No need. I'll pick up the rest of the series when I get the UCP1020
> update patch as well.
OK, got it.
- Simon
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