* [PATCH v3 00/15] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v3:
- modify for reviewer's comment in v2.
- add vdosys1 2 pixels align limit.
- add mixer odd offset support.
Changes in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=531695
[6] [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller header file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210806023606.16867-2-Christine.Zhu@mediatek.com/
Nancy.Lin (15):
dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: mediatek: Add #reset-cells to mmsys system controller
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195
vdosys1
soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add display MDP RDMA support for MT8195
drm/mediatek: add ovl_adaptor support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +
.../display/mediatek/mediatek,ethdr.yaml | 144 +++++
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++
.../display/mediatek/mediatek,merge.yaml | 2 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 28 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 375 +++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 440 +++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 275 +++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 39 ++
drivers/soc/mediatek/mt8195-mmsys.h | 199 +++++++
drivers/soc/mediatek/mtk-mmsys.c | 137 +++++
drivers/soc/mediatek/mtk-mmsys.h | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 +++++----
include/dt-bindings/reset/mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 22 +
25 files changed, 2677 insertions(+), 183 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 78+ messages in thread* [PATCH v3 00/15] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v3:
- modify for reviewer's comment in v2.
- add vdosys1 2 pixels align limit.
- add mixer odd offset support.
Changes in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=531695
[6] [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller header file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210806023606.16867-2-Christine.Zhu@mediatek.com/
Nancy.Lin (15):
dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: mediatek: Add #reset-cells to mmsys system controller
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195
vdosys1
soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add display MDP RDMA support for MT8195
drm/mediatek: add ovl_adaptor support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +
.../display/mediatek/mediatek,ethdr.yaml | 144 +++++
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++
.../display/mediatek/mediatek,merge.yaml | 2 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 28 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 375 +++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 440 +++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 275 +++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 39 ++
drivers/soc/mediatek/mt8195-mmsys.h | 199 +++++++
drivers/soc/mediatek/mtk-mmsys.c | 137 +++++
drivers/soc/mediatek/mtk-mmsys.h | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 +++++----
include/dt-bindings/reset/mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 22 +
25 files changed, 2677 insertions(+), 183 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread* [PATCH v3 01/15] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 000000000000..3610093848e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display MDP RDMA
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display MDP RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 01/15] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 000000000000..3610093848e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display MDP RDMA
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display MDP RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 01/15] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 000000000000..3610093848e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display MDP RDMA
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display MDP RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 MERGE definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 1a27b037086b..ba1e0c837988 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -23,6 +23,8 @@ properties:
- const: mediatek,mt8173-disp-merge
- items:
- const: mediatek,mt8195-disp-merge
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
reg:
maxItems: 1
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 MERGE definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 1a27b037086b..ba1e0c837988 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -23,6 +23,8 @@ properties:
- const: mediatek,mt8173-disp-merge
- items:
- const: mediatek,mt8195-disp-merge
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
reg:
maxItems: 1
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 MERGE definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 1a27b037086b..ba1e0c837988 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -23,6 +23,8 @@ properties:
- const: mediatek,mt8173-disp-merge
- items:
- const: mediatek,mt8195-disp-merge
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
reg:
maxItems: 1
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
2021-08-18 9:18 ` Nancy.Lin
(?)
(?)
@ 2021-08-19 23:25 ` Chun-Kuang Hu
-1 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 23:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add vdosys1 MERGE definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 1a27b037086b..ba1e0c837988 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,8 @@ properties:
> - const: mediatek,mt8173-disp-merge
> - items:
> - const: mediatek,mt8195-disp-merge
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
I don't know why create a new merge for mt8195. Provide more
information about the difference of these two merge.
Regards,
Chun-Kuang.
>
> reg:
> maxItems: 1
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
@ 2021-08-19 23:25 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 23:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add vdosys1 MERGE definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 1a27b037086b..ba1e0c837988 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,8 @@ properties:
> - const: mediatek,mt8173-disp-merge
> - items:
> - const: mediatek,mt8195-disp-merge
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
I don't know why create a new merge for mt8195. Provide more
information about the difference of these two merge.
Regards,
Chun-Kuang.
>
> reg:
> maxItems: 1
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
@ 2021-08-19 23:25 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 23:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add vdosys1 MERGE definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 1a27b037086b..ba1e0c837988 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,8 @@ properties:
> - const: mediatek,mt8173-disp-merge
> - items:
> - const: mediatek,mt8195-disp-merge
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
I don't know why create a new merge for mt8195. Provide more
information about the difference of these two merge.
Regards,
Chun-Kuang.
>
> reg:
> maxItems: 1
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
@ 2021-08-19 23:25 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 23:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add vdosys1 MERGE definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 1a27b037086b..ba1e0c837988 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,8 @@ properties:
> - const: mediatek,mt8173-disp-merge
> - items:
> - const: mediatek,mt8195-disp-merge
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
I don't know why create a new merge for mt8195. Provide more
information about the difference of these two merge.
Regards,
Chun-Kuang.
>
> reg:
> maxItems: 1
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
2021-08-19 23:25 ` Chun-Kuang Hu
(?)
@ 2021-08-24 5:07 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 5:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Fri, 2021-08-20 at 07:25 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add vdosys1 MERGE definition.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../devicetree/bindings/display/mediatek/mediatek,merge.yaml |
> > 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > index 1a27b037086b..ba1e0c837988 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > @@ -23,6 +23,8 @@ properties:
> > - const: mediatek,mt8173-disp-merge
> > - items:
> > - const: mediatek,mt8195-disp-merge
> > + - items:
> > + - const: mediatek,mt8195-vdo1-merge
>
> I don't know why create a new merge for mt8195. Provide more
> information about the difference of these two merge.
>
Compared with MT8195 merge0 and merge5, merge1~4 has more mute
function. I will remove this new compatible, move ovl_adaptor merge to
merge common driver, and add new merge binding property to increase
mute function.
> Regards,
> Chun-Kuang.
>
> >
> > reg:
> > maxItems: 1
> > --
> > 2.18.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
@ 2021-08-24 5:07 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 5:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Fri, 2021-08-20 at 07:25 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add vdosys1 MERGE definition.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../devicetree/bindings/display/mediatek/mediatek,merge.yaml |
> > 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > index 1a27b037086b..ba1e0c837988 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > @@ -23,6 +23,8 @@ properties:
> > - const: mediatek,mt8173-disp-merge
> > - items:
> > - const: mediatek,mt8195-disp-merge
> > + - items:
> > + - const: mediatek,mt8195-vdo1-merge
>
> I don't know why create a new merge for mt8195. Provide more
> information about the difference of these two merge.
>
Compared with MT8195 merge0 and merge5, merge1~4 has more mute
function. I will remove this new compatible, move ovl_adaptor merge to
merge common driver, and add new merge binding property to increase
mute function.
> Regards,
> Chun-Kuang.
>
> >
> > reg:
> > maxItems: 1
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 02/15] dt-bindings: mediatek: add vdosys1 MERGE definition for mt8195
@ 2021-08-24 5:07 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 5:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Fri, 2021-08-20 at 07:25 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add vdosys1 MERGE definition.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../devicetree/bindings/display/mediatek/mediatek,merge.yaml |
> > 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > index 1a27b037086b..ba1e0c837988 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge
> > .yaml
> > @@ -23,6 +23,8 @@ properties:
> > - const: mediatek,mt8173-disp-merge
> > - items:
> > - const: mediatek,mt8195-disp-merge
> > + - items:
> > + - const: mediatek,mt8195-vdo1-merge
>
> I don't know why create a new merge for mt8195. Provide more
> information about the difference of these two merge.
>
Compared with MT8195 merge0 and merge5, merge1~4 has more mute
function. I will remove this new compatible, move ovl_adaptor merge to
merge common driver, and add new merge binding property to increase
mute function.
> Regards,
> Chun-Kuang.
>
> >
> > reg:
> > maxItems: 1
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v3 03/15] dt-bindings: mediatek: add ethdr definition for mt8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..64d5349cdf8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 03/15] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..64d5349cdf8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 03/15] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..64d5349cdf8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 04/15] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 68cb330d7595..5678d55b032a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -50,6 +50,9 @@ properties:
"#clock-cells":
const: 1
+ "#reset-cells":
+ const: 1
+
required:
- compatible
- reg
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 04/15] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 68cb330d7595..5678d55b032a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -50,6 +50,9 @@ properties:
"#clock-cells":
const: 1
+ "#reset-cells":
+ const: 1
+
required:
- compatible
- reg
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 04/15] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 68cb330d7595..5678d55b032a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -50,6 +50,9 @@ properties:
"#clock-cells":
const: 1
+ "#reset-cells":
+ const: 1
+
required:
- compatible
- reg
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 05/15] dt-bindings: reset: mt8195: add vdosys1 reset control bit
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..eaaa882c09bd 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 05/15] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..eaaa882c09bd 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 05/15] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..eaaa882c09bd 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 06/15] arm64: dts: mt8195: add display node for vdosys1
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,7 +1291,208 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 06/15] arm64: dts: mt8195: add display node for vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,7 +1291,208 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 06/15] arm64: dts: mt8195: add display node for vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,7 +1291,208 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 07/15] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 148 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 39a2b125494d..3c2b1d43dcc4 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -59,6 +59,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -108,6 +172,78 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
DDP_COMPONENT_MERGE0 , DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index ce6cc2f49e7d..7365731c9fd7 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -66,6 +66,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -182,6 +188,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 6d6ece48b61e..619392221a52 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -18,6 +18,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_DSC0,
@@ -38,6 +39,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_ADAPTOR,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 07/15] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 148 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 39a2b125494d..3c2b1d43dcc4 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -59,6 +59,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -108,6 +172,78 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
DDP_COMPONENT_MERGE0 , DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index ce6cc2f49e7d..7365731c9fd7 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -66,6 +66,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -182,6 +188,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 6d6ece48b61e..619392221a52 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -18,6 +18,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_DSC0,
@@ -38,6 +39,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_ADAPTOR,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 07/15] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 148 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 39a2b125494d..3c2b1d43dcc4 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -59,6 +59,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -108,6 +172,78 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
DDP_COMPONENT_MERGE0 , DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index ce6cc2f49e7d..7365731c9fd7 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -66,6 +66,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -182,6 +188,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 6d6ece48b61e..619392221a52 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -18,6 +18,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_DSC0,
@@ -38,6 +39,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_ADAPTOR,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 08/15] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 62 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 33 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 +++++
include/linux/soc/mediatek/mtk-mmsys.h | 16 +++++++
4 files changed, 121 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 3c2b1d43dcc4..0b079cba443f 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,21 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8195_VDO1_MIXER_IN2_PAD 0xd44
+#define MT8195_VDO1_MIXER_IN3_PAD 0xd48
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -247,4 +262,51 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+/*
+ * mtk_mmsys_config table is used for config mmsys reg in runtime.
+ * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width
+ * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height
+ * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width
+ * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap
+ * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source
+ * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode)
+ * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1
+ */
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 7365731c9fd7..cd59a4157731 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -70,6 +70,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
struct mtk_mmsys {
@@ -114,6 +116,37 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 5f3e2bf0c40b..825857d8d7f4 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -86,10 +86,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 619392221a52..ef2a6d9a834b 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -53,6 +53,19 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+ MMSYS_CONFIG_MIXER_IN_MODE,
+ MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -61,4 +74,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 08/15] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 62 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 33 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 +++++
include/linux/soc/mediatek/mtk-mmsys.h | 16 +++++++
4 files changed, 121 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 3c2b1d43dcc4..0b079cba443f 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,21 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8195_VDO1_MIXER_IN2_PAD 0xd44
+#define MT8195_VDO1_MIXER_IN3_PAD 0xd48
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -247,4 +262,51 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+/*
+ * mtk_mmsys_config table is used for config mmsys reg in runtime.
+ * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width
+ * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height
+ * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width
+ * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap
+ * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source
+ * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode)
+ * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1
+ */
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 7365731c9fd7..cd59a4157731 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -70,6 +70,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
struct mtk_mmsys {
@@ -114,6 +116,37 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 5f3e2bf0c40b..825857d8d7f4 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -86,10 +86,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 619392221a52..ef2a6d9a834b 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -53,6 +53,19 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+ MMSYS_CONFIG_MIXER_IN_MODE,
+ MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -61,4 +74,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
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^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 08/15] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 62 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 33 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 +++++
include/linux/soc/mediatek/mtk-mmsys.h | 16 +++++++
4 files changed, 121 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 3c2b1d43dcc4..0b079cba443f 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,21 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8195_VDO1_MIXER_IN2_PAD 0xd44
+#define MT8195_VDO1_MIXER_IN3_PAD 0xd48
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -247,4 +262,51 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+/*
+ * mtk_mmsys_config table is used for config mmsys reg in runtime.
+ * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width
+ * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height
+ * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width
+ * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap
+ * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source
+ * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode)
+ * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1
+ */
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 7365731c9fd7..cd59a4157731 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -70,6 +70,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
struct mtk_mmsys {
@@ -114,6 +116,37 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 5f3e2bf0c40b..825857d8d7f4 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -86,10 +86,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 619392221a52..ef2a6d9a834b 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -53,6 +53,19 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+ MMSYS_CONFIG_MIXER_IN_MODE,
+ MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -61,4 +74,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 09/15] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet. The first command in the packet is "wait stream done",
and then following with all the HW settings. After the cmdq packet is
flush to GCE HW. The GCE waits for the "stream done event" to coming
and then starts flushing all the HW settings. This can guarantee all
the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 28 +++++++++++++++++++++-----
include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++-
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cd59a4157731..e2bcd701ceb0 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -77,6 +77,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ struct cmdq_client_reg cmdq_base;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -117,7 +118,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val)
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
@@ -140,10 +141,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
mask = mmsys_config[i].mask;
reg_val = val << mmsys_config[i].shift;
- u32 tmp = readl(mmsys->regs + offset);
-
- tmp = (tmp & ~mask) | reg_val;
- writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
@@ -167,6 +178,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index ef2a6d9a834b..9705d242849a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -75,6 +79,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val);
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 09/15] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet. The first command in the packet is "wait stream done",
and then following with all the HW settings. After the cmdq packet is
flush to GCE HW. The GCE waits for the "stream done event" to coming
and then starts flushing all the HW settings. This can guarantee all
the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 28 +++++++++++++++++++++-----
include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++-
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cd59a4157731..e2bcd701ceb0 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -77,6 +77,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ struct cmdq_client_reg cmdq_base;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -117,7 +118,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val)
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
@@ -140,10 +141,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
mask = mmsys_config[i].mask;
reg_val = val << mmsys_config[i].shift;
- u32 tmp = readl(mmsys->regs + offset);
-
- tmp = (tmp & ~mask) | reg_val;
- writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
@@ -167,6 +178,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index ef2a6d9a834b..9705d242849a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -75,6 +79,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val);
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 09/15] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet. The first command in the packet is "wait stream done",
and then following with all the HW settings. After the cmdq packet is
flush to GCE HW. The GCE waits for the "stream done event" to coming
and then starts flushing all the HW settings. This can guarantee all
the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 28 +++++++++++++++++++++-----
include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++-
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cd59a4157731..e2bcd701ceb0 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -77,6 +77,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ struct cmdq_client_reg cmdq_base;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -117,7 +118,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val)
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
@@ -140,10 +141,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
mask = mmsys_config[i].mask;
reg_val = val << mmsys_config[i].shift;
- u32 tmp = readl(mmsys->regs + offset);
-
- tmp = (tmp & ~mask) | reg_val;
- writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
@@ -167,6 +178,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index ef2a6d9a834b..9705d242849a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -75,6 +79,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val);
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 10/15] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
For MT8195 vdosys1, many async modules need to reset after
the display pipe stops and restart.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 76 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
3 files changed, 78 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0b079cba443f..0b08ac0cf2bf 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,7 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index e2bcd701ceb0..5e6c116e589a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,10 +4,12 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include "mtk-mmsys.h"
@@ -16,6 +18,8 @@
#include "mt8365-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -72,12 +76,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
};
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
struct cmdq_client_reg cmdq_base;
+ spinlock_t lock; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -158,6 +165,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
+ bool assert)
+{
+ struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
+ unsigned long flags;
+ u32 reg;
+ int i;
+ u32 offset;
+
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = id % MMSYS_SW_RESET_PER_REG;
+
+ spin_lock_irqsave(&mmsys->lock, flags);
+
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ if (assert)
+ reg &= ~BIT(id);
+ else
+ reg |= BIT(id);
+
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ spin_unlock_irqrestore(&mmsys->lock, flags);
+
+ return 0;
+}
+
+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, true);
+}
+
+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, false);
+}
+
+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ int ret;
+
+ ret = mtk_mmsys_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ usleep_range(1000, 1100);
+
+ return mtk_mmsys_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_mmsys_reset_ops = {
+ .assert = mtk_mmsys_reset_assert,
+ .deassert = mtk_mmsys_reset_deassert,
+ .reset = mtk_mmsys_reset,
+};
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -185,6 +249,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
#endif
+ spin_lock_init(&mmsys->lock);
+
+ mmsys->rcdev.owner = THIS_MODULE;
+ mmsys->rcdev.nr_resets = 64;
+ mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+ mmsys->rcdev.of_node = pdev->dev.of_node;
+ ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+ return ret;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 825857d8d7f4..d84f5cb78f8c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -100,6 +100,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
};
/*
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 10/15] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
For MT8195 vdosys1, many async modules need to reset after
the display pipe stops and restart.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 76 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
3 files changed, 78 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0b079cba443f..0b08ac0cf2bf 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,7 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index e2bcd701ceb0..5e6c116e589a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,10 +4,12 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include "mtk-mmsys.h"
@@ -16,6 +18,8 @@
#include "mt8365-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -72,12 +76,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
};
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
struct cmdq_client_reg cmdq_base;
+ spinlock_t lock; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -158,6 +165,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
+ bool assert)
+{
+ struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
+ unsigned long flags;
+ u32 reg;
+ int i;
+ u32 offset;
+
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = id % MMSYS_SW_RESET_PER_REG;
+
+ spin_lock_irqsave(&mmsys->lock, flags);
+
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ if (assert)
+ reg &= ~BIT(id);
+ else
+ reg |= BIT(id);
+
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ spin_unlock_irqrestore(&mmsys->lock, flags);
+
+ return 0;
+}
+
+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, true);
+}
+
+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, false);
+}
+
+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ int ret;
+
+ ret = mtk_mmsys_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ usleep_range(1000, 1100);
+
+ return mtk_mmsys_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_mmsys_reset_ops = {
+ .assert = mtk_mmsys_reset_assert,
+ .deassert = mtk_mmsys_reset_deassert,
+ .reset = mtk_mmsys_reset,
+};
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -185,6 +249,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
#endif
+ spin_lock_init(&mmsys->lock);
+
+ mmsys->rcdev.owner = THIS_MODULE;
+ mmsys->rcdev.nr_resets = 64;
+ mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+ mmsys->rcdev.of_node = pdev->dev.of_node;
+ ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+ return ret;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 825857d8d7f4..d84f5cb78f8c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -100,6 +100,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
};
/*
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 10/15] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
For MT8195 vdosys1, many async modules need to reset after
the display pipe stops and restart.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 76 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
3 files changed, 78 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0b079cba443f..0b08ac0cf2bf 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,7 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index e2bcd701ceb0..5e6c116e589a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,10 +4,12 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include "mtk-mmsys.h"
@@ -16,6 +18,8 @@
#include "mt8365-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -72,12 +76,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
};
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
struct cmdq_client_reg cmdq_base;
+ spinlock_t lock; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -158,6 +165,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
+ bool assert)
+{
+ struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
+ unsigned long flags;
+ u32 reg;
+ int i;
+ u32 offset;
+
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = id % MMSYS_SW_RESET_PER_REG;
+
+ spin_lock_irqsave(&mmsys->lock, flags);
+
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ if (assert)
+ reg &= ~BIT(id);
+ else
+ reg |= BIT(id);
+
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ spin_unlock_irqrestore(&mmsys->lock, flags);
+
+ return 0;
+}
+
+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, true);
+}
+
+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, false);
+}
+
+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ int ret;
+
+ ret = mtk_mmsys_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ usleep_range(1000, 1100);
+
+ return mtk_mmsys_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_mmsys_reset_ops = {
+ .assert = mtk_mmsys_reset_assert,
+ .deassert = mtk_mmsys_reset_deassert,
+ .reset = mtk_mmsys_reset,
+};
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -185,6 +249,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
#endif
+ spin_lock_init(&mmsys->lock);
+
+ mmsys->rcdev.owner = THIS_MODULE;
+ mmsys->rcdev.nr_resets = 64;
+ mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+ mmsys->rcdev.of_node = pdev->dev.of_node;
+ ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+ return ret;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 825857d8d7f4..d84f5cb78f8c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -100,6 +100,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
};
/*
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 11/15] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c177156ee2fa..588e378d1855 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -279,6 +308,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -436,17 +486,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -476,22 +529,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 11/15] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c177156ee2fa..588e378d1855 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -279,6 +308,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -436,17 +486,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -476,22 +529,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
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^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 11/15] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c177156ee2fa..588e378d1855 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -279,6 +308,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -436,17 +486,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -476,22 +529,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 12/15] drm/mediatek: add display MDP RDMA support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 ++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 275 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 39 ++++
4 files changed, 328 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 538e0087a44c..38ec2354a894 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,7 +12,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index f407cd9d873e..7129ba061ecb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -8,6 +8,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_plane.h"
+#include "mtk_mdp_rdma.h"
void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
int mtk_ccorr_clk_enable(struct device *dev);
@@ -97,4 +98,15 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..95e762eda4a8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_rdma.h"
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define FLD_PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int pre_ultra_h = 156;
+ unsigned int pre_ultra_l = 104;
+ unsigned int reg_mask;
+ unsigned int reg_val;
+ unsigned int reg;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, 1) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |
+ REG_FLD_VAL(FLD_ULTRA_EN, 0) |
+ REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(FLD_PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, pre_ultra_h);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, pre_ultra_l);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET);
+ mtk_ddp_write(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
+ unsigned int src_pitch_y = cfg->pitch;
+ unsigned int bpp_y = fmt_info->cpp[0] * 8;
+ unsigned int offset_y = 0;
+
+ mtk_mdp_rdma_fifo_config(base, cmdq_pkt, cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && fmt_info->has_alpha)
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..50fa6e18d244
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum mtk_mdp_rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum mtk_mdp_rdma_profile profile;
+ unsigned int source_width;
+ unsigned int pitch;
+ unsigned int addr0;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+#endif // __MTK_MDP_RDMA_H__
+
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 12/15] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 ++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 275 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 39 ++++
4 files changed, 328 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 538e0087a44c..38ec2354a894 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,7 +12,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index f407cd9d873e..7129ba061ecb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -8,6 +8,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_plane.h"
+#include "mtk_mdp_rdma.h"
void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
int mtk_ccorr_clk_enable(struct device *dev);
@@ -97,4 +98,15 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..95e762eda4a8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_rdma.h"
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define FLD_PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int pre_ultra_h = 156;
+ unsigned int pre_ultra_l = 104;
+ unsigned int reg_mask;
+ unsigned int reg_val;
+ unsigned int reg;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, 1) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |
+ REG_FLD_VAL(FLD_ULTRA_EN, 0) |
+ REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(FLD_PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, pre_ultra_h);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, pre_ultra_l);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET);
+ mtk_ddp_write(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
+ unsigned int src_pitch_y = cfg->pitch;
+ unsigned int bpp_y = fmt_info->cpp[0] * 8;
+ unsigned int offset_y = 0;
+
+ mtk_mdp_rdma_fifo_config(base, cmdq_pkt, cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && fmt_info->has_alpha)
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..50fa6e18d244
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum mtk_mdp_rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum mtk_mdp_rdma_profile profile;
+ unsigned int source_width;
+ unsigned int pitch;
+ unsigned int addr0;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+#endif // __MTK_MDP_RDMA_H__
+
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 12/15] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 ++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 275 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 39 ++++
4 files changed, 328 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 538e0087a44c..38ec2354a894 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,7 +12,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index f407cd9d873e..7129ba061ecb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -8,6 +8,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_plane.h"
+#include "mtk_mdp_rdma.h"
void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
int mtk_ccorr_clk_enable(struct device *dev);
@@ -97,4 +98,15 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..95e762eda4a8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_rdma.h"
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define FLD_PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int pre_ultra_h = 156;
+ unsigned int pre_ultra_l = 104;
+ unsigned int reg_mask;
+ unsigned int reg_val;
+ unsigned int reg;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, 1) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |
+ REG_FLD_VAL(FLD_ULTRA_EN, 0) |
+ REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(FLD_PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, pre_ultra_h);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, pre_ultra_l);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET);
+ mtk_ddp_write(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
+ unsigned int src_pitch_y = cfg->pitch;
+ unsigned int bpp_y = fmt_info->cpp[0] * 8;
+ unsigned int offset_y = 0;
+
+ mtk_mdp_rdma_fifo_config(base, cmdq_pkt, cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && fmt_info->has_alpha)
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..50fa6e18d244
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum mtk_mdp_rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum mtk_mdp_rdma_profile profile;
+ unsigned int source_width;
+ unsigned int pitch;
+ unsigned int addr0;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+#endif // __MTK_MDP_RDMA_H__
+
--
2.18.0
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^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v3 12/15] drm/mediatek: add display MDP RDMA support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-20 10:25 ` CK Hu
-1 siblings, 0 replies; 78+ messages in thread
From: CK Hu @ 2021-08-20 10:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Wed, 2021-08-18 at 17:18 +0800, Nancy.Lin wrote:
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
[snip]
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
I would like the bitwise definition has one more indent than the byte
definition.
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define FLD_PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +
[snip]
> +
> +static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int pre_ultra_h = 156;
> + unsigned int pre_ultra_l = 104;
Give the reason why this value. You could refer to merge [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210819022327.13040-13-jason-jh.lin@mediatek.com/
> + unsigned int reg_mask;
> + unsigned int reg_val;
> + unsigned int reg;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, 1) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_ULTRA_EN, 0) |
> + REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(FLD_PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
#define FLD_COMMAND_DIV BIT(0)
#define FLD_EXT_PREULTRA_EN BIT(3)
#define FLD_RD_REQ_TYPE GENMASK(7, 4)
#define FLD_ULTRA_EN GENMASK(13, 12)
#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
#define FLD_PRE_ULTRA_EN_ENABLE 1
#define FLD_EXT_ULTRA_EN BIT(18)
mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | FLD_PRE_ULTRA_EN_ENABLE
<< 16 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | FLD_EXT_PREULTRA_EN |
FLD_COMMAND_DIV, cmdq_base, base, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE | FLD_EXT_PREULTRA_EN
| FLD_COMMAND_DIV);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, pre_ultra_h);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, pre_ultra_l);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
[snip]
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..50fa6e18d244
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum mtk_mdp_rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum mtk_mdp_rdma_profile profile;
> + unsigned int source_width;
source_width is useless, so remove.
Regards,
CK.
> + unsigned int pitch;
> + unsigned int addr0;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 12/15] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-08-20 10:25 ` CK Hu
0 siblings, 0 replies; 78+ messages in thread
From: CK Hu @ 2021-08-20 10:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Wed, 2021-08-18 at 17:18 +0800, Nancy.Lin wrote:
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
[snip]
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
I would like the bitwise definition has one more indent than the byte
definition.
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define FLD_PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +
[snip]
> +
> +static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int pre_ultra_h = 156;
> + unsigned int pre_ultra_l = 104;
Give the reason why this value. You could refer to merge [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210819022327.13040-13-jason-jh.lin@mediatek.com/
> + unsigned int reg_mask;
> + unsigned int reg_val;
> + unsigned int reg;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, 1) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_ULTRA_EN, 0) |
> + REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(FLD_PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
#define FLD_COMMAND_DIV BIT(0)
#define FLD_EXT_PREULTRA_EN BIT(3)
#define FLD_RD_REQ_TYPE GENMASK(7, 4)
#define FLD_ULTRA_EN GENMASK(13, 12)
#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
#define FLD_PRE_ULTRA_EN_ENABLE 1
#define FLD_EXT_ULTRA_EN BIT(18)
mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | FLD_PRE_ULTRA_EN_ENABLE
<< 16 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | FLD_EXT_PREULTRA_EN |
FLD_COMMAND_DIV, cmdq_base, base, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE | FLD_EXT_PREULTRA_EN
| FLD_COMMAND_DIV);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, pre_ultra_h);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, pre_ultra_l);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
[snip]
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..50fa6e18d244
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum mtk_mdp_rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum mtk_mdp_rdma_profile profile;
> + unsigned int source_width;
source_width is useless, so remove.
Regards,
CK.
> + unsigned int pitch;
> + unsigned int addr0;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 12/15] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-08-20 10:25 ` CK Hu
0 siblings, 0 replies; 78+ messages in thread
From: CK Hu @ 2021-08-20 10:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Wed, 2021-08-18 at 17:18 +0800, Nancy.Lin wrote:
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
[snip]
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
I would like the bitwise definition has one more indent than the byte
definition.
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define FLD_PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +
[snip]
> +
> +static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int pre_ultra_h = 156;
> + unsigned int pre_ultra_l = 104;
Give the reason why this value. You could refer to merge [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210819022327.13040-13-jason-jh.lin@mediatek.com/
> + unsigned int reg_mask;
> + unsigned int reg_val;
> + unsigned int reg;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, 1) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_ULTRA_EN, 0) |
> + REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(FLD_PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
#define FLD_COMMAND_DIV BIT(0)
#define FLD_EXT_PREULTRA_EN BIT(3)
#define FLD_RD_REQ_TYPE GENMASK(7, 4)
#define FLD_ULTRA_EN GENMASK(13, 12)
#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
#define FLD_PRE_ULTRA_EN_ENABLE 1
#define FLD_EXT_ULTRA_EN BIT(18)
mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | FLD_PRE_ULTRA_EN_ENABLE
<< 16 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | FLD_EXT_PREULTRA_EN |
FLD_COMMAND_DIV, cmdq_base, base, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE | FLD_EXT_PREULTRA_EN
| FLD_COMMAND_DIV);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, pre_ultra_h);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, pre_ultra_l);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
[snip]
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..50fa6e18d244
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum mtk_mdp_rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum mtk_mdp_rdma_profile profile;
> + unsigned int source_width;
source_width is useless, so remove.
Regards,
CK.
> + unsigned int pitch;
> + unsigned int addr0;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
3 files changed, 549 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 38ec2354a894..f04ac86c9593 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_disp_ovl_adaptor.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
new file mode 100644
index 000000000000..8222ec5ff799
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_disp_ovl_adaptor.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
+#define MTK_OVL_ADAPTOR_LAYER_NUM 4
+
+enum mtk_ovl_adaptor_comp_type {
+ OVL_ADAPTOR_TYPE_RDMA = 0,
+ OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_NUM,
+};
+
+enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_MDP_RDMA0,
+ OVL_ADAPTOR_MDP_RDMA1,
+ OVL_ADAPTOR_MDP_RDMA2,
+ OVL_ADAPTOR_MDP_RDMA3,
+ OVL_ADAPTOR_MDP_RDMA4,
+ OVL_ADAPTOR_MDP_RDMA5,
+ OVL_ADAPTOR_MDP_RDMA6,
+ OVL_ADAPTOR_MDP_RDMA7,
+ OVL_ADAPTOR_MERGE0,
+ OVL_ADAPTOR_MERGE1,
+ OVL_ADAPTOR_MERGE2,
+ OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_ID_MAX
+};
+
+struct ovl_adaptor_comp_match {
+ enum mtk_ovl_adaptor_comp_type type;
+ int alias_id;
+};
+
+struct ovl_adaptor_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_ovl_adaptor_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_ovl_adaptor {
+ struct mtk_ovl_adaptor_comp ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
+ struct device *mmsys_dev;
+};
+
+static const char * const ovl_adaptor_comp_str[] = {
+ "OVL_ADAPTOR_MDP_RDMA0",
+ "OVL_ADAPTOR_MDP_RDMA1",
+ "OVL_ADAPTOR_MDP_RDMA2",
+ "OVL_ADAPTOR_MDP_RDMA3",
+ "OVL_ADAPTOR_MDP_RDMA4",
+ "OVL_ADAPTOR_MDP_RDMA5",
+ "OVL_ADAPTOR_MDP_RDMA6",
+ "OVL_ADAPTOR_MDP_RDMA7",
+ "OVL_ADAPTOR_MERGE0",
+ "OVL_ADAPTOR_MERGE1",
+ "OVL_ADAPTOR_MERGE2",
+ "OVL_ADAPTOR_MERGE3",
+ "OVL_ADAPTOR_ID_MAX"
+};
+
+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+ [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
+};
+
+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+};
+
+static void mtk_ovl_adaptor_merge_config(struct mtk_ovl_adaptor_comp *comp,
+ struct ovl_adaptor_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ break;
+ case 18:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
+ break;
+ default:
+ break;
+ }
+
+ mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12);
+ mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+}
+
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct ovl_adaptor_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_ovl_adaptor_comp *rdma_l;
+ struct mtk_ovl_adaptor_comp *rdma_r;
+ struct mtk_ovl_adaptor_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
+ rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
+ merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+
+ if (!pending->enable) {
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+ mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
+
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.pitch = pending->pitch;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+}
+
+void mtk_ovl_adaptor_stop(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *rdma_l;
+ struct mtk_ovl_adaptor_comp *rdma_r;
+ struct mtk_ovl_adaptor_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
+ rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
+ rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
+ merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ device_reset_optional(merge->dev);
+ }
+}
+
+int mtk_ovl_adaptor_clk_enable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = &ovl_adaptor->ovl_adaptor_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < OVL_ADAPTOR_MERGE0) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, ovl_adaptor_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, ovl_adaptor_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_ovl_adaptor_clk_disable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = &ovl_adaptor->ovl_adaptor_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < OVL_ADAPTOR_MERGE0) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, ovl_adaptor_comp_str[i]);
+ }
+ }
+}
+
+static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_ovl_adaptor_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_ovl_adaptor_comp *comp,
+ enum mtk_ovl_adaptor_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < OVL_ADAPTOR_MERGE0)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, ovl_adaptor_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
+ .probe = mtk_disp_ovl_adaptor_comp_probe,
+ .remove = mtk_disp_ovl_adaptor_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
+
+static int ovl_adaptor_comp_init(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_ovl_adaptor_comp_type type;
+ struct mtk_ovl_adaptor_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->ovl_adaptor_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
+
+static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ of_id = of_match_node(ovl_adaptor_driver_dt_match, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = ovl_adaptor_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "ovl_adaptor comp init fail\n");
+ return ret;
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0; i++)
+ pm_runtime_disable(ovl_adaptor->ovl_adaptor_comp[i].dev);
+
+ return 0;
+}
+
+struct platform_driver mtk_disp_ovl_adaptor_driver = {
+ .probe = mtk_disp_ovl_adaptor_probe,
+ .remove = mtk_disp_ovl_adaptor_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor",
+ .owner = THIS_MODULE,
+ },
+};
+module_platform_driver(mtk_disp_ovl_adaptor_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
new file mode 100644
index 000000000000..7d757be1f491
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_OVL_ADAPTOR_H__
+#define __MTK_DISP_OVL_ADAPTOR_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_ovl_adaptor_stop(struct device *dev);
+int mtk_ovl_adaptor_clk_enable(struct device *dev);
+void mtk_ovl_adaptor_clk_disable(struct device *dev);
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+
+#endif
+
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
3 files changed, 549 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 38ec2354a894..f04ac86c9593 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_disp_ovl_adaptor.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
new file mode 100644
index 000000000000..8222ec5ff799
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_disp_ovl_adaptor.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
+#define MTK_OVL_ADAPTOR_LAYER_NUM 4
+
+enum mtk_ovl_adaptor_comp_type {
+ OVL_ADAPTOR_TYPE_RDMA = 0,
+ OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_NUM,
+};
+
+enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_MDP_RDMA0,
+ OVL_ADAPTOR_MDP_RDMA1,
+ OVL_ADAPTOR_MDP_RDMA2,
+ OVL_ADAPTOR_MDP_RDMA3,
+ OVL_ADAPTOR_MDP_RDMA4,
+ OVL_ADAPTOR_MDP_RDMA5,
+ OVL_ADAPTOR_MDP_RDMA6,
+ OVL_ADAPTOR_MDP_RDMA7,
+ OVL_ADAPTOR_MERGE0,
+ OVL_ADAPTOR_MERGE1,
+ OVL_ADAPTOR_MERGE2,
+ OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_ID_MAX
+};
+
+struct ovl_adaptor_comp_match {
+ enum mtk_ovl_adaptor_comp_type type;
+ int alias_id;
+};
+
+struct ovl_adaptor_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_ovl_adaptor_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_ovl_adaptor {
+ struct mtk_ovl_adaptor_comp ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
+ struct device *mmsys_dev;
+};
+
+static const char * const ovl_adaptor_comp_str[] = {
+ "OVL_ADAPTOR_MDP_RDMA0",
+ "OVL_ADAPTOR_MDP_RDMA1",
+ "OVL_ADAPTOR_MDP_RDMA2",
+ "OVL_ADAPTOR_MDP_RDMA3",
+ "OVL_ADAPTOR_MDP_RDMA4",
+ "OVL_ADAPTOR_MDP_RDMA5",
+ "OVL_ADAPTOR_MDP_RDMA6",
+ "OVL_ADAPTOR_MDP_RDMA7",
+ "OVL_ADAPTOR_MERGE0",
+ "OVL_ADAPTOR_MERGE1",
+ "OVL_ADAPTOR_MERGE2",
+ "OVL_ADAPTOR_MERGE3",
+ "OVL_ADAPTOR_ID_MAX"
+};
+
+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+ [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
+};
+
+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+};
+
+static void mtk_ovl_adaptor_merge_config(struct mtk_ovl_adaptor_comp *comp,
+ struct ovl_adaptor_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ break;
+ case 18:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
+ break;
+ default:
+ break;
+ }
+
+ mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12);
+ mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+}
+
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct ovl_adaptor_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_ovl_adaptor_comp *rdma_l;
+ struct mtk_ovl_adaptor_comp *rdma_r;
+ struct mtk_ovl_adaptor_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
+ rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
+ merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+
+ if (!pending->enable) {
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+ mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
+
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.pitch = pending->pitch;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+}
+
+void mtk_ovl_adaptor_stop(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *rdma_l;
+ struct mtk_ovl_adaptor_comp *rdma_r;
+ struct mtk_ovl_adaptor_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
+ rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
+ rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
+ merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ device_reset_optional(merge->dev);
+ }
+}
+
+int mtk_ovl_adaptor_clk_enable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = &ovl_adaptor->ovl_adaptor_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < OVL_ADAPTOR_MERGE0) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, ovl_adaptor_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, ovl_adaptor_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_ovl_adaptor_clk_disable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = &ovl_adaptor->ovl_adaptor_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < OVL_ADAPTOR_MERGE0) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, ovl_adaptor_comp_str[i]);
+ }
+ }
+}
+
+static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_ovl_adaptor_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_ovl_adaptor_comp *comp,
+ enum mtk_ovl_adaptor_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < OVL_ADAPTOR_MERGE0)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, ovl_adaptor_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
+ .probe = mtk_disp_ovl_adaptor_comp_probe,
+ .remove = mtk_disp_ovl_adaptor_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
+
+static int ovl_adaptor_comp_init(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_ovl_adaptor_comp_type type;
+ struct mtk_ovl_adaptor_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->ovl_adaptor_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
+
+static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ of_id = of_match_node(ovl_adaptor_driver_dt_match, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = ovl_adaptor_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "ovl_adaptor comp init fail\n");
+ return ret;
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0; i++)
+ pm_runtime_disable(ovl_adaptor->ovl_adaptor_comp[i].dev);
+
+ return 0;
+}
+
+struct platform_driver mtk_disp_ovl_adaptor_driver = {
+ .probe = mtk_disp_ovl_adaptor_probe,
+ .remove = mtk_disp_ovl_adaptor_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor",
+ .owner = THIS_MODULE,
+ },
+};
+module_platform_driver(mtk_disp_ovl_adaptor_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
new file mode 100644
index 000000000000..7d757be1f491
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_OVL_ADAPTOR_H__
+#define __MTK_DISP_OVL_ADAPTOR_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_ovl_adaptor_stop(struct device *dev);
+int mtk_ovl_adaptor_clk_enable(struct device *dev);
+void mtk_ovl_adaptor_clk_disable(struct device *dev);
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+
+#endif
+
--
2.18.0
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^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
3 files changed, 549 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 38ec2354a894..f04ac86c9593 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_disp_ovl_adaptor.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
new file mode 100644
index 000000000000..8222ec5ff799
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_disp_ovl_adaptor.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
+#define MTK_OVL_ADAPTOR_LAYER_NUM 4
+
+enum mtk_ovl_adaptor_comp_type {
+ OVL_ADAPTOR_TYPE_RDMA = 0,
+ OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_NUM,
+};
+
+enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_MDP_RDMA0,
+ OVL_ADAPTOR_MDP_RDMA1,
+ OVL_ADAPTOR_MDP_RDMA2,
+ OVL_ADAPTOR_MDP_RDMA3,
+ OVL_ADAPTOR_MDP_RDMA4,
+ OVL_ADAPTOR_MDP_RDMA5,
+ OVL_ADAPTOR_MDP_RDMA6,
+ OVL_ADAPTOR_MDP_RDMA7,
+ OVL_ADAPTOR_MERGE0,
+ OVL_ADAPTOR_MERGE1,
+ OVL_ADAPTOR_MERGE2,
+ OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_ID_MAX
+};
+
+struct ovl_adaptor_comp_match {
+ enum mtk_ovl_adaptor_comp_type type;
+ int alias_id;
+};
+
+struct ovl_adaptor_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_ovl_adaptor_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_ovl_adaptor {
+ struct mtk_ovl_adaptor_comp ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
+ struct device *mmsys_dev;
+};
+
+static const char * const ovl_adaptor_comp_str[] = {
+ "OVL_ADAPTOR_MDP_RDMA0",
+ "OVL_ADAPTOR_MDP_RDMA1",
+ "OVL_ADAPTOR_MDP_RDMA2",
+ "OVL_ADAPTOR_MDP_RDMA3",
+ "OVL_ADAPTOR_MDP_RDMA4",
+ "OVL_ADAPTOR_MDP_RDMA5",
+ "OVL_ADAPTOR_MDP_RDMA6",
+ "OVL_ADAPTOR_MDP_RDMA7",
+ "OVL_ADAPTOR_MERGE0",
+ "OVL_ADAPTOR_MERGE1",
+ "OVL_ADAPTOR_MERGE2",
+ "OVL_ADAPTOR_MERGE3",
+ "OVL_ADAPTOR_ID_MAX"
+};
+
+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+ [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
+};
+
+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+};
+
+static void mtk_ovl_adaptor_merge_config(struct mtk_ovl_adaptor_comp *comp,
+ struct ovl_adaptor_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ break;
+ case 18:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
+ break;
+ default:
+ break;
+ }
+
+ mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12);
+ mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+}
+
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct ovl_adaptor_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_ovl_adaptor_comp *rdma_l;
+ struct mtk_ovl_adaptor_comp *rdma_r;
+ struct mtk_ovl_adaptor_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
+ rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
+ merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+
+ if (!pending->enable) {
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+ mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
+
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.pitch = pending->pitch;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+}
+
+void mtk_ovl_adaptor_stop(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *rdma_l;
+ struct mtk_ovl_adaptor_comp *rdma_r;
+ struct mtk_ovl_adaptor_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
+ rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
+ rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
+ merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ device_reset_optional(merge->dev);
+ }
+}
+
+int mtk_ovl_adaptor_clk_enable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = &ovl_adaptor->ovl_adaptor_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < OVL_ADAPTOR_MERGE0) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, ovl_adaptor_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, ovl_adaptor_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_ovl_adaptor_clk_disable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_ovl_adaptor_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = &ovl_adaptor->ovl_adaptor_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < OVL_ADAPTOR_MERGE0) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, ovl_adaptor_comp_str[i]);
+ }
+ }
+}
+
+static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_ovl_adaptor_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_ovl_adaptor_comp *comp,
+ enum mtk_ovl_adaptor_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < OVL_ADAPTOR_MERGE0)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, ovl_adaptor_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
+ .probe = mtk_disp_ovl_adaptor_comp_probe,
+ .remove = mtk_disp_ovl_adaptor_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
+
+static int ovl_adaptor_comp_init(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_ovl_adaptor_comp_type type;
+ struct mtk_ovl_adaptor_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->ovl_adaptor_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
+
+static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ of_id = of_match_node(ovl_adaptor_driver_dt_match, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = ovl_adaptor_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "ovl_adaptor comp init fail\n");
+ return ret;
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0; i++)
+ pm_runtime_disable(ovl_adaptor->ovl_adaptor_comp[i].dev);
+
+ return 0;
+}
+
+struct platform_driver mtk_disp_ovl_adaptor_driver = {
+ .probe = mtk_disp_ovl_adaptor_probe,
+ .remove = mtk_disp_ovl_adaptor_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor",
+ .owner = THIS_MODULE,
+ },
+};
+module_platform_driver(mtk_disp_ovl_adaptor_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
new file mode 100644
index 000000000000..7d757be1f491
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_OVL_ADAPTOR_H__
+#define __MTK_DISP_OVL_ADAPTOR_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_ovl_adaptor_stop(struct device *dev);
+int mtk_ovl_adaptor_clk_enable(struct device *dev);
+void mtk_ovl_adaptor_clk_disable(struct device *dev);
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+
+#endif
+
--
2.18.0
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^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-21 23:47 ` Chun-Kuang Hu
-1 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-21 23:47 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:19寫道：
>
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
> 3 files changed, 549 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 38ec2354a894..f04ac86c9593 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_disp_ovl_adaptor.o
Alphabetic order.
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..8222ec5ff799
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,528 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
Alphabetic order.
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
> +#include "mtk_disp_ovl_adaptor.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
I would like
#define DISP_MERGE_ENABLE 0x0
#define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct ovl_adaptor_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_ovl_adaptor_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
keep only dev, other value should be moved to dev private data.
> +
> +struct mtk_disp_ovl_adaptor {
> + struct mtk_ovl_adaptor_comp ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> +};
> +
> +static void mtk_ovl_adaptor_merge_config(struct mtk_ovl_adaptor_comp *comp,
> + struct ovl_adaptor_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + break;
> + case 18:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
> + break;
> + default:
> + break;
> + }
> +
> + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12);
> + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
Move this function to merge driver.
> +}
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct ovl_adaptor_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_ovl_adaptor_comp *rdma_l;
> + struct mtk_ovl_adaptor_comp *rdma_r;
> + struct mtk_ovl_adaptor_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> +
> + if (!pending->enable) {
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
Ditto.
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
merge_cfg.in_w[1] = pending->width - merge_cfg.in_w[0];
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> + mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
> +
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
Move this to merge driver.
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *rdma_l;
> + struct mtk_ovl_adaptor_comp *rdma_r;
> + struct mtk_ovl_adaptor_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
Ditto.
> +
> + device_reset_optional(merge->dev);
> + }
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < OVL_ADAPTOR_MERGE0) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, ovl_adaptor_comp_str[i]);
undo previos pm_runtime_get_sync() and return error.
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
undo and previous job and return error.
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < OVL_ADAPTOR_MERGE0) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, ovl_adaptor_comp_str[i]);
> + }
> + }
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_ovl_adaptor_comp *comp,
> + enum mtk_ovl_adaptor_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < OVL_ADAPTOR_MERGE0)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, ovl_adaptor_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
> + .probe = mtk_disp_ovl_adaptor_comp_probe,
> + .remove = mtk_disp_ovl_adaptor_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
> +
> +static int ovl_adaptor_comp_init(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + struct mtk_ovl_adaptor_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->ovl_adaptor_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr"},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + of_id = of_match_node(ovl_adaptor_driver_dt_match, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0; i++)
> + pm_runtime_disable(ovl_adaptor->ovl_adaptor_comp[i].dev);
> +
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
> +};
> +module_platform_driver(mtk_disp_ovl_adaptor_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> new file mode 100644
> index 000000000000..7d757be1f491
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_OVL_ADAPTOR_H__
> +#define __MTK_DISP_OVL_ADAPTOR_H__
> +
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +
> +#endif
> +
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-08-21 23:47 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-21 23:47 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:19寫道：
>
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
> 3 files changed, 549 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 38ec2354a894..f04ac86c9593 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_disp_ovl_adaptor.o
Alphabetic order.
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..8222ec5ff799
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,528 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
Alphabetic order.
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
> +#include "mtk_disp_ovl_adaptor.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
I would like
#define DISP_MERGE_ENABLE 0x0
#define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct ovl_adaptor_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_ovl_adaptor_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
keep only dev, other value should be moved to dev private data.
> +
> +struct mtk_disp_ovl_adaptor {
> + struct mtk_ovl_adaptor_comp ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> +};
> +
> +static void mtk_ovl_adaptor_merge_config(struct mtk_ovl_adaptor_comp *comp,
> + struct ovl_adaptor_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + break;
> + case 18:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
> + break;
> + default:
> + break;
> + }
> +
> + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12);
> + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
Move this function to merge driver.
> +}
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct ovl_adaptor_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_ovl_adaptor_comp *rdma_l;
> + struct mtk_ovl_adaptor_comp *rdma_r;
> + struct mtk_ovl_adaptor_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> +
> + if (!pending->enable) {
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
Ditto.
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
merge_cfg.in_w[1] = pending->width - merge_cfg.in_w[0];
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> + mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
> +
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
Move this to merge driver.
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *rdma_l;
> + struct mtk_ovl_adaptor_comp *rdma_r;
> + struct mtk_ovl_adaptor_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
Ditto.
> +
> + device_reset_optional(merge->dev);
> + }
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < OVL_ADAPTOR_MERGE0) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, ovl_adaptor_comp_str[i]);
undo previos pm_runtime_get_sync() and return error.
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
undo and previous job and return error.
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < OVL_ADAPTOR_MERGE0) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, ovl_adaptor_comp_str[i]);
> + }
> + }
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_ovl_adaptor_comp *comp,
> + enum mtk_ovl_adaptor_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < OVL_ADAPTOR_MERGE0)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, ovl_adaptor_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
> + .probe = mtk_disp_ovl_adaptor_comp_probe,
> + .remove = mtk_disp_ovl_adaptor_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
> +
> +static int ovl_adaptor_comp_init(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + struct mtk_ovl_adaptor_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->ovl_adaptor_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr"},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + of_id = of_match_node(ovl_adaptor_driver_dt_match, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0; i++)
> + pm_runtime_disable(ovl_adaptor->ovl_adaptor_comp[i].dev);
> +
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
> +};
> +module_platform_driver(mtk_disp_ovl_adaptor_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> new file mode 100644
> index 000000000000..7d757be1f491
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_OVL_ADAPTOR_H__
> +#define __MTK_DISP_OVL_ADAPTOR_H__
> +
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +
> +#endif
> +
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-08-21 23:47 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-21 23:47 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:19寫道：
>
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528 ++++++++++++++++++
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
> 3 files changed, 549 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 38ec2354a894..f04ac86c9593 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_disp_ovl_adaptor.o
Alphabetic order.
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..8222ec5ff799
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,528 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
Alphabetic order.
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
> +#include "mtk_disp_ovl_adaptor.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
I would like
#define DISP_MERGE_ENABLE 0x0
#define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct ovl_adaptor_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_ovl_adaptor_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
keep only dev, other value should be moved to dev private data.
> +
> +struct mtk_disp_ovl_adaptor {
> + struct mtk_ovl_adaptor_comp ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> +};
> +
> +static void mtk_ovl_adaptor_merge_config(struct mtk_ovl_adaptor_comp *comp,
> + struct ovl_adaptor_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + break;
> + case 18:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
> + break;
> + default:
> + break;
> + }
> +
> + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12);
> + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
Move this function to merge driver.
> +}
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct ovl_adaptor_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_ovl_adaptor_comp *rdma_l;
> + struct mtk_ovl_adaptor_comp *rdma_r;
> + struct mtk_ovl_adaptor_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> +
> + if (!pending->enable) {
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
Ditto.
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
merge_cfg.in_w[1] = pending->width - merge_cfg.in_w[0];
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> + mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
> +
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
Move this to merge driver.
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *rdma_l;
> + struct mtk_ovl_adaptor_comp *rdma_r;
> + struct mtk_ovl_adaptor_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
Ditto.
> +
> + device_reset_optional(merge->dev);
> + }
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < OVL_ADAPTOR_MERGE0) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, ovl_adaptor_comp_str[i]);
undo previos pm_runtime_get_sync() and return error.
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
undo and previous job and return error.
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_ovl_adaptor_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < OVL_ADAPTOR_MERGE0) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, ovl_adaptor_comp_str[i]);
> + }
> + }
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_ovl_adaptor_comp *comp,
> + enum mtk_ovl_adaptor_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < OVL_ADAPTOR_MERGE0)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, ovl_adaptor_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
> + .probe = mtk_disp_ovl_adaptor_comp_probe,
> + .remove = mtk_disp_ovl_adaptor_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
> +
> +static int ovl_adaptor_comp_init(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + struct mtk_ovl_adaptor_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->ovl_adaptor_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr"},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + of_id = of_match_node(ovl_adaptor_driver_dt_match, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0; i++)
> + pm_runtime_disable(ovl_adaptor->ovl_adaptor_comp[i].dev);
> +
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
> +};
> +module_platform_driver(mtk_disp_ovl_adaptor_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> new file mode 100644
> index 000000000000..7d757be1f491
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_OVL_ADAPTOR_H__
> +#define __MTK_DISP_OVL_ADAPTOR_H__
> +
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +
> +#endif
> +
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
2021-08-21 23:47 ` Chun-Kuang Hu
(?)
@ 2021-08-24 4:58 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:58 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 07:47 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:19寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528
> > ++++++++++++++++++
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
> > 3 files changed, 549 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 38ec2354a894..f04ac86c9593 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > - mtk_mdp_rdma.o
> > + mtk_mdp_rdma.o \
> > + mtk_disp_ovl_adaptor.o
>
> Alphabetic order.
>
OK.
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..8222ec5ff799
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,528 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
>
> Alphabetic order.
OK.
>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_disp_ovl_adaptor.h"
> > +
> > +#define DISP_MERGE_ENABLE 0x0
> > + #define MERGE_ENABLE BIT(0)
>
> I would like
>
> #define DISP_MERGE_ENABLE 0x0
> #define MERGE_ENABLE BIT(0)
>
I will use merge common driver instead of ovl merge driver. Will remove
merge related part.
> > +#define DISP_MERGE_CFG_0 0x10
> > +#define DISP_MERGE_CFG_1 0x14
> > +#define DISP_MERGE_CFG_4 0x20
> > +#define DISP_MERGE_CFG_5 0x24
> > +#define DISP_MERGE_CFG_10 0x38
> > + #define CFG_10_NO_SWAP 0
> > +#define DISP_MERGE_CFG_12 0x40
> > + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> > + #define CFG12_11_10_1PI_2PO_MERGE 18
> > +#define DISP_MERGE_CFG_24 0x70
> > +#define DISP_MERGE_CFG_25 0x74
> > +#define DISP_MERGE_CFG_26 0x78
> > +#define DISP_MERGE_CFG_27 0x7c
> > +#define DISP_MERGE_MUTE_0 0xf00
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct ovl_adaptor_merge_config {
> > + unsigned int fmt;
> > + unsigned int merge_mode;
> > + unsigned int in_w[2];
> > + unsigned int out_w[2];
> > + unsigned int in_h;
> > +};
> > +
> > +struct mtk_ovl_adaptor_comp {
> > + struct device *dev;
> > + struct clk *clks[2];
> > + struct cmdq_client_reg cmdq_base;
> > + void __iomem *regs;
> > +};
>
> keep only dev, other value should be moved to dev private data.
>
OK.
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct mtk_ovl_adaptor_comp
> > ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0
> > },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1
> > },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2
> > },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3
> > },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4
> > },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5
> > },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6
> > },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7
> > },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > +};
> > +
> > +static void mtk_ovl_adaptor_merge_config(struct
> > mtk_ovl_adaptor_comp *comp,
> > + struct
> > ovl_adaptor_merge_config *merge_cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + switch (merge_cfg->merge_mode) {
> > + case 6:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + break;
> > + case 18:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_27);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp-
> > >cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_12);
> > + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_10);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
>
> Move this function to merge driver.
>
OK.
> > +}
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct ovl_adaptor_merge_config merge_cfg = {0};
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct mtk_ovl_adaptor_comp *rdma_l;
> > + struct mtk_ovl_adaptor_comp *rdma_r;
> > + struct mtk_ovl_adaptor_comp *merge;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> > + rdma_r = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> > + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge-
> > >cmdq_base, merge->regs,
> > + DISP_MERGE_ENABLE,
> > MERGE_ENABLE);
>
> Ditto.
OK.
>
> > + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + return;
> > + }
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + merge_cfg.out_w[0] = pending->width;
> > + merge_cfg.in_h = pending->height;
> > + merge_cfg.fmt = pending->format;
> > + if (use_dual_pipe) {
> > + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> > + merge_cfg.in_w[0] = (pending->width / 2) +
> > ((pending->width / 2) % 2);
> > + merge_cfg.in_w[1] = (pending->width / 2) -
> > ((pending->width / 2) % 2);
>
> merge_cfg.in_w[1] = pending->width - merge_cfg.in_w[0];
>
> > + } else {
> > + merge_cfg.merge_mode =
> > CFG12_10_10_1PI_2PO_BUF_MODE;
> > + merge_cfg.in_w[0] = pending->width;
> > + }
> > + mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
> > +
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.source_width = pending->pitch / fmt_info-
> > >cpp[0];
> > + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> > + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> > + rdma_config.width = merge_cfg.in_w[0];
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt,
> > &rdma_l->cmdq_base);
> > +
> > + rdma_config.x_left = merge_cfg.in_w[0];
> > + rdma_config.width = merge_cfg.in_w[1];
> > + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt,
> > &rdma_r->cmdq_base);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_MUTE_0, 0x1);
>
> Move this to merge driver.
OK.
>
> > +
> > + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *rdma_l;
> > + struct mtk_ovl_adaptor_comp *rdma_r;
> > + struct mtk_ovl_adaptor_comp *merge;
> > + unsigned int reg;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r-
> > >cmdq_base);
> > +
> > + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> > + reg = reg & ~MERGE_ENABLE;
> > + writel_relaxed(reg, merge->regs +
> > DISP_MERGE_ENABLE);
>
> Ditto.
OK.
>
> > +
> > + device_reset_optional(merge->dev);
> > + }
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
> > + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + /* Need to power on for private rdma devices */
> > + if (i < OVL_ADAPTOR_MERGE0) {
> > + ret = pm_runtime_get_sync(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power on, err
> > %d-%s\n",
> > + ret,
> > ovl_adaptor_comp_str[i]);
>
> undo previos pm_runtime_get_sync() and return error.
OK, I will add error handling.
>
> > + }
> > +
> > + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > +
> > + ret = clk_prepare_enable(comp->clks[j]);
> > + if (ret)
> > + dev_err(dev,
> > + "Failed to enable clock %d,
> > err %d-%s\n",
> > + i, ret,
> > ovl_adaptor_comp_str[i]);
>
> undo and previous job and return error.
OK, I will add error handling.
>
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
> > + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > + clk_disable_unprepare(comp->clks[j]);
> > + }
> > +
> > + /* Need to power off for private rdma devices */
> > + if (i < OVL_ADAPTOR_MERGE0) {
> > + ret = pm_runtime_put(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power off, err-
> > %s\n",
> > + ret,
> > ovl_adaptor_comp_str[i]);
> > + }
> > + }
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static int private_comp_init(struct device *dev, struct
> > device_node *node,
> > + struct mtk_ovl_adaptor_comp *comp,
> > + enum mtk_ovl_adaptor_comp_id id)
> > +{
> > + struct platform_device *comp_pdev;
> > + int ret;
> > + int i;
> > +
> > + if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
> > + dev_err(dev, "Invalid component id %d\n", id);
> > + return -EINVAL;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + comp->dev = &comp_pdev->dev;
> > + comp->regs = of_iomap(node, 0);
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> > + comp->clks[i] = of_clk_get(node, i);
> > + if (IS_ERR(comp->clks[i]))
> > + break;
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base,
> > 0);
> > + if (ret)
> > + dev_info(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + if (id < OVL_ADAPTOR_MERGE0)
> > + pm_runtime_enable(comp->dev);
> > +
> > + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs,
> > ovl_adaptor_comp_str[id]);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-vdo1-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + },
> > + {},
> > +};
> > +
> > +static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
> > + .probe = mtk_disp_ovl_adaptor_comp_probe,
> > + .remove = mtk_disp_ovl_adaptor_comp_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor-comp",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + int i, ret;
> > +
> > + parent = dev->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + ret = private_comp_init(dev, node, &priv-
> > >ovl_adaptor_comp[id], id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr"},
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *phandle = dev->parent->of_node;
> > + const struct of_device_id *of_id;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + of_id = of_match_node(ovl_adaptor_driver_dt_match,
> > phandle);
> > + if (!of_id)
> > + return -ENODEV;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(&pdev->dev);
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0;
> > i++)
> > + pm_runtime_disable(ovl_adaptor-
> > >ovl_adaptor_comp[i].dev);
> > +
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_ovl_adaptor_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > new file mode 100644
> > index 000000000000..7d757be1f491
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_OVL_ADAPTOR_H__
> > +#define __MTK_DISP_OVL_ADAPTOR_H__
> > +
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +
> > +#endif
> > +
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-08-24 4:58 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:58 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 07:47 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:19寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528
> > ++++++++++++++++++
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
> > 3 files changed, 549 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 38ec2354a894..f04ac86c9593 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > - mtk_mdp_rdma.o
> > + mtk_mdp_rdma.o \
> > + mtk_disp_ovl_adaptor.o
>
> Alphabetic order.
>
OK.
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..8222ec5ff799
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,528 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
>
> Alphabetic order.
OK.
>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_disp_ovl_adaptor.h"
> > +
> > +#define DISP_MERGE_ENABLE 0x0
> > + #define MERGE_ENABLE BIT(0)
>
> I would like
>
> #define DISP_MERGE_ENABLE 0x0
> #define MERGE_ENABLE BIT(0)
>
I will use merge common driver instead of ovl merge driver. Will remove
merge related part.
> > +#define DISP_MERGE_CFG_0 0x10
> > +#define DISP_MERGE_CFG_1 0x14
> > +#define DISP_MERGE_CFG_4 0x20
> > +#define DISP_MERGE_CFG_5 0x24
> > +#define DISP_MERGE_CFG_10 0x38
> > + #define CFG_10_NO_SWAP 0
> > +#define DISP_MERGE_CFG_12 0x40
> > + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> > + #define CFG12_11_10_1PI_2PO_MERGE 18
> > +#define DISP_MERGE_CFG_24 0x70
> > +#define DISP_MERGE_CFG_25 0x74
> > +#define DISP_MERGE_CFG_26 0x78
> > +#define DISP_MERGE_CFG_27 0x7c
> > +#define DISP_MERGE_MUTE_0 0xf00
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct ovl_adaptor_merge_config {
> > + unsigned int fmt;
> > + unsigned int merge_mode;
> > + unsigned int in_w[2];
> > + unsigned int out_w[2];
> > + unsigned int in_h;
> > +};
> > +
> > +struct mtk_ovl_adaptor_comp {
> > + struct device *dev;
> > + struct clk *clks[2];
> > + struct cmdq_client_reg cmdq_base;
> > + void __iomem *regs;
> > +};
>
> keep only dev, other value should be moved to dev private data.
>
OK.
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct mtk_ovl_adaptor_comp
> > ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0
> > },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1
> > },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2
> > },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3
> > },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4
> > },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5
> > },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6
> > },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7
> > },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > +};
> > +
> > +static void mtk_ovl_adaptor_merge_config(struct
> > mtk_ovl_adaptor_comp *comp,
> > + struct
> > ovl_adaptor_merge_config *merge_cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + switch (merge_cfg->merge_mode) {
> > + case 6:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + break;
> > + case 18:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_27);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp-
> > >cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_12);
> > + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_10);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
>
> Move this function to merge driver.
>
OK.
> > +}
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct ovl_adaptor_merge_config merge_cfg = {0};
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct mtk_ovl_adaptor_comp *rdma_l;
> > + struct mtk_ovl_adaptor_comp *rdma_r;
> > + struct mtk_ovl_adaptor_comp *merge;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> > + rdma_r = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> > + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge-
> > >cmdq_base, merge->regs,
> > + DISP_MERGE_ENABLE,
> > MERGE_ENABLE);
>
> Ditto.
OK.
>
> > + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + return;
> > + }
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + merge_cfg.out_w[0] = pending->width;
> > + merge_cfg.in_h = pending->height;
> > + merge_cfg.fmt = pending->format;
> > + if (use_dual_pipe) {
> > + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> > + merge_cfg.in_w[0] = (pending->width / 2) +
> > ((pending->width / 2) % 2);
> > + merge_cfg.in_w[1] = (pending->width / 2) -
> > ((pending->width / 2) % 2);
>
> merge_cfg.in_w[1] = pending->width - merge_cfg.in_w[0];
>
> > + } else {
> > + merge_cfg.merge_mode =
> > CFG12_10_10_1PI_2PO_BUF_MODE;
> > + merge_cfg.in_w[0] = pending->width;
> > + }
> > + mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
> > +
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.source_width = pending->pitch / fmt_info-
> > >cpp[0];
> > + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> > + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> > + rdma_config.width = merge_cfg.in_w[0];
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt,
> > &rdma_l->cmdq_base);
> > +
> > + rdma_config.x_left = merge_cfg.in_w[0];
> > + rdma_config.width = merge_cfg.in_w[1];
> > + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt,
> > &rdma_r->cmdq_base);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_MUTE_0, 0x1);
>
> Move this to merge driver.
OK.
>
> > +
> > + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *rdma_l;
> > + struct mtk_ovl_adaptor_comp *rdma_r;
> > + struct mtk_ovl_adaptor_comp *merge;
> > + unsigned int reg;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r-
> > >cmdq_base);
> > +
> > + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> > + reg = reg & ~MERGE_ENABLE;
> > + writel_relaxed(reg, merge->regs +
> > DISP_MERGE_ENABLE);
>
> Ditto.
OK.
>
> > +
> > + device_reset_optional(merge->dev);
> > + }
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
> > + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + /* Need to power on for private rdma devices */
> > + if (i < OVL_ADAPTOR_MERGE0) {
> > + ret = pm_runtime_get_sync(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power on, err
> > %d-%s\n",
> > + ret,
> > ovl_adaptor_comp_str[i]);
>
> undo previos pm_runtime_get_sync() and return error.
OK, I will add error handling.
>
> > + }
> > +
> > + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > +
> > + ret = clk_prepare_enable(comp->clks[j]);
> > + if (ret)
> > + dev_err(dev,
> > + "Failed to enable clock %d,
> > err %d-%s\n",
> > + i, ret,
> > ovl_adaptor_comp_str[i]);
>
> undo and previous job and return error.
OK, I will add error handling.
>
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
> > + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > + clk_disable_unprepare(comp->clks[j]);
> > + }
> > +
> > + /* Need to power off for private rdma devices */
> > + if (i < OVL_ADAPTOR_MERGE0) {
> > + ret = pm_runtime_put(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power off, err-
> > %s\n",
> > + ret,
> > ovl_adaptor_comp_str[i]);
> > + }
> > + }
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static int private_comp_init(struct device *dev, struct
> > device_node *node,
> > + struct mtk_ovl_adaptor_comp *comp,
> > + enum mtk_ovl_adaptor_comp_id id)
> > +{
> > + struct platform_device *comp_pdev;
> > + int ret;
> > + int i;
> > +
> > + if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
> > + dev_err(dev, "Invalid component id %d\n", id);
> > + return -EINVAL;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + comp->dev = &comp_pdev->dev;
> > + comp->regs = of_iomap(node, 0);
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> > + comp->clks[i] = of_clk_get(node, i);
> > + if (IS_ERR(comp->clks[i]))
> > + break;
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base,
> > 0);
> > + if (ret)
> > + dev_info(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + if (id < OVL_ADAPTOR_MERGE0)
> > + pm_runtime_enable(comp->dev);
> > +
> > + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs,
> > ovl_adaptor_comp_str[id]);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-vdo1-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + },
> > + {},
> > +};
> > +
> > +static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
> > + .probe = mtk_disp_ovl_adaptor_comp_probe,
> > + .remove = mtk_disp_ovl_adaptor_comp_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor-comp",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + int i, ret;
> > +
> > + parent = dev->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + ret = private_comp_init(dev, node, &priv-
> > >ovl_adaptor_comp[id], id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr"},
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *phandle = dev->parent->of_node;
> > + const struct of_device_id *of_id;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + of_id = of_match_node(ovl_adaptor_driver_dt_match,
> > phandle);
> > + if (!of_id)
> > + return -ENODEV;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(&pdev->dev);
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0;
> > i++)
> > + pm_runtime_disable(ovl_adaptor-
> > >ovl_adaptor_comp[i].dev);
> > +
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_ovl_adaptor_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > new file mode 100644
> > index 000000000000..7d757be1f491
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_OVL_ADAPTOR_H__
> > +#define __MTK_DISP_OVL_ADAPTOR_H__
> > +
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +
> > +#endif
> > +
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 13/15] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-08-24 4:58 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:58 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 07:47 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:19寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 528
> > ++++++++++++++++++
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.h | 19 +
> > 3 files changed, 549 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 38ec2354a894..f04ac86c9593 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > - mtk_mdp_rdma.o
> > + mtk_mdp_rdma.o \
> > + mtk_disp_ovl_adaptor.o
>
> Alphabetic order.
>
OK.
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..8222ec5ff799
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,528 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
>
> Alphabetic order.
OK.
>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_disp_ovl_adaptor.h"
> > +
> > +#define DISP_MERGE_ENABLE 0x0
> > + #define MERGE_ENABLE BIT(0)
>
> I would like
>
> #define DISP_MERGE_ENABLE 0x0
> #define MERGE_ENABLE BIT(0)
>
I will use merge common driver instead of ovl merge driver. Will remove
merge related part.
> > +#define DISP_MERGE_CFG_0 0x10
> > +#define DISP_MERGE_CFG_1 0x14
> > +#define DISP_MERGE_CFG_4 0x20
> > +#define DISP_MERGE_CFG_5 0x24
> > +#define DISP_MERGE_CFG_10 0x38
> > + #define CFG_10_NO_SWAP 0
> > +#define DISP_MERGE_CFG_12 0x40
> > + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> > + #define CFG12_11_10_1PI_2PO_MERGE 18
> > +#define DISP_MERGE_CFG_24 0x70
> > +#define DISP_MERGE_CFG_25 0x74
> > +#define DISP_MERGE_CFG_26 0x78
> > +#define DISP_MERGE_CFG_27 0x7c
> > +#define DISP_MERGE_MUTE_0 0xf00
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct ovl_adaptor_merge_config {
> > + unsigned int fmt;
> > + unsigned int merge_mode;
> > + unsigned int in_w[2];
> > + unsigned int out_w[2];
> > + unsigned int in_h;
> > +};
> > +
> > +struct mtk_ovl_adaptor_comp {
> > + struct device *dev;
> > + struct clk *clks[2];
> > + struct cmdq_client_reg cmdq_base;
> > + void __iomem *regs;
> > +};
>
> keep only dev, other value should be moved to dev private data.
>
OK.
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct mtk_ovl_adaptor_comp
> > ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0
> > },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1
> > },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2
> > },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3
> > },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4
> > },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5
> > },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6
> > },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7
> > },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > +};
> > +
> > +static void mtk_ovl_adaptor_merge_config(struct
> > mtk_ovl_adaptor_comp *comp,
> > + struct
> > ovl_adaptor_merge_config *merge_cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + switch (merge_cfg->merge_mode) {
> > + case 6:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + break;
> > + case 18:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_27);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp-
> > >cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_12);
> > + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_10);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
>
> Move this function to merge driver.
>
OK.
> > +}
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct ovl_adaptor_merge_config merge_cfg = {0};
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct mtk_ovl_adaptor_comp *rdma_l;
> > + struct mtk_ovl_adaptor_comp *rdma_r;
> > + struct mtk_ovl_adaptor_comp *merge;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> > + rdma_r = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> > + merge = &ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge-
> > >cmdq_base, merge->regs,
> > + DISP_MERGE_ENABLE,
> > MERGE_ENABLE);
>
> Ditto.
OK.
>
> > + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + return;
> > + }
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + merge_cfg.out_w[0] = pending->width;
> > + merge_cfg.in_h = pending->height;
> > + merge_cfg.fmt = pending->format;
> > + if (use_dual_pipe) {
> > + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> > + merge_cfg.in_w[0] = (pending->width / 2) +
> > ((pending->width / 2) % 2);
> > + merge_cfg.in_w[1] = (pending->width / 2) -
> > ((pending->width / 2) % 2);
>
> merge_cfg.in_w[1] = pending->width - merge_cfg.in_w[0];
>
> > + } else {
> > + merge_cfg.merge_mode =
> > CFG12_10_10_1PI_2PO_BUF_MODE;
> > + merge_cfg.in_w[0] = pending->width;
> > + }
> > + mtk_ovl_adaptor_merge_config(merge, &merge_cfg, cmdq_pkt);
> > +
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.source_width = pending->pitch / fmt_info-
> > >cpp[0];
> > + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> > + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> > + rdma_config.width = merge_cfg.in_w[0];
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt,
> > &rdma_l->cmdq_base);
> > +
> > + rdma_config.x_left = merge_cfg.in_w[0];
> > + rdma_config.width = merge_cfg.in_w[1];
> > + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt,
> > &rdma_r->cmdq_base);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_MUTE_0, 0x1);
>
> Move this to merge driver.
OK.
>
> > +
> > + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *rdma_l;
> > + struct mtk_ovl_adaptor_comp *rdma_r;
> > + struct mtk_ovl_adaptor_comp *merge;
> > + unsigned int reg;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = &ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r-
> > >cmdq_base);
> > +
> > + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> > + reg = reg & ~MERGE_ENABLE;
> > + writel_relaxed(reg, merge->regs +
> > DISP_MERGE_ENABLE);
>
> Ditto.
OK.
>
> > +
> > + device_reset_optional(merge->dev);
> > + }
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
> > + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + /* Need to power on for private rdma devices */
> > + if (i < OVL_ADAPTOR_MERGE0) {
> > + ret = pm_runtime_get_sync(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power on, err
> > %d-%s\n",
> > + ret,
> > ovl_adaptor_comp_str[i]);
>
> undo previos pm_runtime_get_sync() and return error.
OK, I will add error handling.
>
> > + }
> > +
> > + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > +
> > + ret = clk_prepare_enable(comp->clks[j]);
> > + if (ret)
> > + dev_err(dev,
> > + "Failed to enable clock %d,
> > err %d-%s\n",
> > + i, ret,
> > ovl_adaptor_comp_str[i]);
>
> undo and previous job and return error.
OK, I will add error handling.
>
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
> > + comp = &ovl_adaptor->ovl_adaptor_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > + clk_disable_unprepare(comp->clks[j]);
> > + }
> > +
> > + /* Need to power off for private rdma devices */
> > + if (i < OVL_ADAPTOR_MERGE0) {
> > + ret = pm_runtime_put(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power off, err-
> > %s\n",
> > + ret,
> > ovl_adaptor_comp_str[i]);
> > + }
> > + }
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static int private_comp_init(struct device *dev, struct
> > device_node *node,
> > + struct mtk_ovl_adaptor_comp *comp,
> > + enum mtk_ovl_adaptor_comp_id id)
> > +{
> > + struct platform_device *comp_pdev;
> > + int ret;
> > + int i;
> > +
> > + if (id < 0 || id >= OVL_ADAPTOR_ID_MAX) {
> > + dev_err(dev, "Invalid component id %d\n", id);
> > + return -EINVAL;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + comp->dev = &comp_pdev->dev;
> > + comp->regs = of_iomap(node, 0);
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> > + comp->clks[i] = of_clk_get(node, i);
> > + if (IS_ERR(comp->clks[i]))
> > + break;
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base,
> > 0);
> > + if (ret)
> > + dev_info(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + if (id < OVL_ADAPTOR_MERGE0)
> > + pm_runtime_enable(comp->dev);
> > +
> > + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs,
> > ovl_adaptor_comp_str[id]);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_probe(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_remove(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-vdo1-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + },
> > + {},
> > +};
> > +
> > +static struct platform_driver mtk_disp_ovl_adaptor_comp_driver = {
> > + .probe = mtk_disp_ovl_adaptor_comp_probe,
> > + .remove = mtk_disp_ovl_adaptor_comp_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor-comp",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_ovl_adaptor_comp_dt_ids,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_ovl_adaptor_comp_driver);
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + int i, ret;
> > +
> > + parent = dev->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + struct mtk_ovl_adaptor_comp *comp;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + ret = private_comp_init(dev, node, &priv-
> > >ovl_adaptor_comp[id], id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id ovl_adaptor_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr"},
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match);
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *phandle = dev->parent->of_node;
> > + const struct of_device_id *of_id;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + of_id = of_match_node(ovl_adaptor_driver_dt_match,
> > phandle);
> > + if (!of_id)
> > + return -ENODEV;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(&pdev->dev);
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_MERGE0;
> > i++)
> > + pm_runtime_disable(ovl_adaptor-
> > >ovl_adaptor_comp[i].dev);
> > +
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_ovl_adaptor_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > new file mode 100644
> > index 000000000000..7d757be1f491
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_OVL_ADAPTOR_H__
> > +#define __MTK_DISP_OVL_ADAPTOR_H__
> > +
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +
> > +#endif
> > +
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v3 14/15] drm/mediatek: add ETHDR support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 440 ++++++++++++++++++++++++
5 files changed, 462 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index f04ac86c9593..c42d0623e629 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,7 +14,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_mdp_rdma.o \
- mtk_disp_ovl_adaptor.o
+ mtk_disp_ovl_adaptor.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7129ba061ecb..964d0ad2b81d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -98,6 +98,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+unsigned int mtk_ethdr_layer_nr(struct device *dev);
+
void mtk_mdp_rdma_start(void __iomem *base,
struct cmdq_pkt *cmdq_pkt,
struct cmdq_client_reg *cmdq_base);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9aebf73144c6..6a18c12fe04e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -452,6 +452,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_OVL_ADAPTOR },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -674,6 +676,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 0fa417219a69..7b09fe6db067 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -54,5 +54,6 @@ extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..05035b6015d8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_ovl_adaptor.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define MIXER_INx_MODE_BYPASS 0
+#define MIXER_INx_MODE_EVEN_EXTEND 1
+#define MIXER_INx_MODE_ODD_EXTEND 2
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *ovl_adaptor_dev;
+ struct device *mmsys_dev;
+ spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+ unsigned long flags;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if (!priv->vblank_cb) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return IRQ_NONE;
+ }
+
+ priv->vblank_cb(priv->vblank_cb_data);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+ unsigned int src_size;
+ bool x_offset_odd = false;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
+ pending->width = ALIGN_DOWN(pending->width, 2);
+ src_size = (pending->height << 16) | pending->width;
+
+ mtk_ovl_adaptor_layer_config(priv->ovl_adaptor_dev, idx, state, cmdq_pkt);
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, 0, cmdq_pkt);
+ return;
+ }
+
+ if (pending->x % 2) {
+ x_offset_odd = true;
+ mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, mixer_pad_mode, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, pending->width / 2 - 1, cmdq_pkt);
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, (x_offset_odd << 31) | offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ w / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(1, mixer->regs + MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ovl_adaptor_stop(priv->ovl_adaptor_dev);
+
+ writel(0, mixer->regs + MIX_EN);
+ writel(1, mixer->regs + MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ writel(0, mixer->regs + MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_ovl_adaptor_clk_enable(priv->ovl_adaptor_dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_ovl_adaptor_clk_disable(priv->ovl_adaptor_dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+unsigned int mtk_ethdr_layer_nr(struct device *dev)
+{
+ return 4;
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct platform_device *ovl_adaptor;
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+
+ priv->mmsys_dev = drm_private->mmsys_dev;
+
+ /* Bring up ovl adaptor rdma and merge */
+ ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
+ PLATFORM_DEVID_AUTO, (void *)priv->mmsys_dev,
+ sizeof(*priv->mmsys_dev));
+ if (IS_ERR(ovl_adaptor))
+ return PTR_ERR(ovl_adaptor);
+
+ priv->ovl_adaptor_dev = &ovl_adaptor->dev;
+
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ spin_lock_init(&priv->lock);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ pm_runtime_enable(dev);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 14/15] drm/mediatek: add ETHDR support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 440 ++++++++++++++++++++++++
5 files changed, 462 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index f04ac86c9593..c42d0623e629 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,7 +14,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_mdp_rdma.o \
- mtk_disp_ovl_adaptor.o
+ mtk_disp_ovl_adaptor.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7129ba061ecb..964d0ad2b81d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -98,6 +98,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+unsigned int mtk_ethdr_layer_nr(struct device *dev);
+
void mtk_mdp_rdma_start(void __iomem *base,
struct cmdq_pkt *cmdq_pkt,
struct cmdq_client_reg *cmdq_base);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9aebf73144c6..6a18c12fe04e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -452,6 +452,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_OVL_ADAPTOR },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -674,6 +676,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 0fa417219a69..7b09fe6db067 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -54,5 +54,6 @@ extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..05035b6015d8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_ovl_adaptor.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define MIXER_INx_MODE_BYPASS 0
+#define MIXER_INx_MODE_EVEN_EXTEND 1
+#define MIXER_INx_MODE_ODD_EXTEND 2
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *ovl_adaptor_dev;
+ struct device *mmsys_dev;
+ spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+ unsigned long flags;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if (!priv->vblank_cb) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return IRQ_NONE;
+ }
+
+ priv->vblank_cb(priv->vblank_cb_data);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+ unsigned int src_size;
+ bool x_offset_odd = false;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
+ pending->width = ALIGN_DOWN(pending->width, 2);
+ src_size = (pending->height << 16) | pending->width;
+
+ mtk_ovl_adaptor_layer_config(priv->ovl_adaptor_dev, idx, state, cmdq_pkt);
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, 0, cmdq_pkt);
+ return;
+ }
+
+ if (pending->x % 2) {
+ x_offset_odd = true;
+ mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, mixer_pad_mode, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, pending->width / 2 - 1, cmdq_pkt);
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, (x_offset_odd << 31) | offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ w / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(1, mixer->regs + MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ovl_adaptor_stop(priv->ovl_adaptor_dev);
+
+ writel(0, mixer->regs + MIX_EN);
+ writel(1, mixer->regs + MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ writel(0, mixer->regs + MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_ovl_adaptor_clk_enable(priv->ovl_adaptor_dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_ovl_adaptor_clk_disable(priv->ovl_adaptor_dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+unsigned int mtk_ethdr_layer_nr(struct device *dev)
+{
+ return 4;
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct platform_device *ovl_adaptor;
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+
+ priv->mmsys_dev = drm_private->mmsys_dev;
+
+ /* Bring up ovl adaptor rdma and merge */
+ ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
+ PLATFORM_DEVID_AUTO, (void *)priv->mmsys_dev,
+ sizeof(*priv->mmsys_dev));
+ if (IS_ERR(ovl_adaptor))
+ return PTR_ERR(ovl_adaptor);
+
+ priv->ovl_adaptor_dev = &ovl_adaptor->dev;
+
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ spin_lock_init(&priv->lock);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ pm_runtime_enable(dev);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
--
2.18.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 14/15] drm/mediatek: add ETHDR support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 440 ++++++++++++++++++++++++
5 files changed, 462 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index f04ac86c9593..c42d0623e629 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,7 +14,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_mdp_rdma.o \
- mtk_disp_ovl_adaptor.o
+ mtk_disp_ovl_adaptor.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7129ba061ecb..964d0ad2b81d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -98,6 +98,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+unsigned int mtk_ethdr_layer_nr(struct device *dev);
+
void mtk_mdp_rdma_start(void __iomem *base,
struct cmdq_pkt *cmdq_pkt,
struct cmdq_client_reg *cmdq_base);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9aebf73144c6..6a18c12fe04e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -452,6 +452,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_OVL_ADAPTOR },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -674,6 +676,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 0fa417219a69..7b09fe6db067 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -54,5 +54,6 @@ extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..05035b6015d8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_ovl_adaptor.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define MIXER_INx_MODE_BYPASS 0
+#define MIXER_INx_MODE_EVEN_EXTEND 1
+#define MIXER_INx_MODE_ODD_EXTEND 2
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *ovl_adaptor_dev;
+ struct device *mmsys_dev;
+ spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+ unsigned long flags;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if (!priv->vblank_cb) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return IRQ_NONE;
+ }
+
+ priv->vblank_cb(priv->vblank_cb_data);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+ unsigned int src_size;
+ bool x_offset_odd = false;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
+ pending->width = ALIGN_DOWN(pending->width, 2);
+ src_size = (pending->height << 16) | pending->width;
+
+ mtk_ovl_adaptor_layer_config(priv->ovl_adaptor_dev, idx, state, cmdq_pkt);
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, 0, cmdq_pkt);
+ return;
+ }
+
+ if (pending->x % 2) {
+ x_offset_odd = true;
+ mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, mixer_pad_mode, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, pending->width / 2 - 1, cmdq_pkt);
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, (x_offset_odd << 31) | offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ w / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(1, mixer->regs + MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ovl_adaptor_stop(priv->ovl_adaptor_dev);
+
+ writel(0, mixer->regs + MIX_EN);
+ writel(1, mixer->regs + MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ writel(0, mixer->regs + MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_ovl_adaptor_clk_enable(priv->ovl_adaptor_dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_ovl_adaptor_clk_disable(priv->ovl_adaptor_dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+unsigned int mtk_ethdr_layer_nr(struct device *dev)
+{
+ return 4;
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct platform_device *ovl_adaptor;
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+
+ priv->mmsys_dev = drm_private->mmsys_dev;
+
+ /* Bring up ovl adaptor rdma and merge */
+ ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
+ PLATFORM_DEVID_AUTO, (void *)priv->mmsys_dev,
+ sizeof(*priv->mmsys_dev));
+ if (IS_ERR(ovl_adaptor))
+ return PTR_ERR(ovl_adaptor);
+
+ priv->ovl_adaptor_dev = &ovl_adaptor->dev;
+
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ spin_lock_init(&priv->lock);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ pm_runtime_enable(dev);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
@ 2021-08-18 9:18 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372 ++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
7 files changed, 354 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index ebcb646bde9c..c61f5bafd22c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
@@ -87,6 +88,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..0da78adf3b4f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -816,25 +823,25 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ i = (priv->data->mmsys_dev_num > 1) ? 0 : drm_crtc_index(&mtk_crtc->base);
+
mtk_crtc->cmdq_client =
- cmdq_mbox_create(mtk_crtc->mmsys_dev,
- drm_crtc_index(&mtk_crtc->base));
+ cmdq_mbox_create(mtk_crtc->mmsys_dev, i);
if (IS_ERR(mtk_crtc->cmdq_client)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
drm_crtc_index(&mtk_crtc->base));
@@ -844,7 +851,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (mtk_crtc->cmdq_client) {
ret = of_property_read_u32_index(priv->mutex_node,
"mediatek,gce-events",
- drm_crtc_index(&mtk_crtc->base),
+ i,
&mtk_crtc->cmdq_event);
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..a57eb12d7c05 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -17,7 +17,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ee8efc13eaea..9623adbc2277 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -380,6 +380,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+ .layer_nr = mtk_ethdr_layer_nr,
+ .layer_config = mtk_ethdr_layer_config,
+ .enable_vblank = mtk_ethdr_enable_vblank,
+ .disable_vblank = mtk_ethdr_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_AAL] = "aal",
[MTK_DISP_BLS] = "bls",
@@ -393,6 +405,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
+ [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
[MTK_DISP_UFOE] = "ufoe",
@@ -436,6 +449,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -563,6 +577,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_OVL_ADAPTOR ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index b42a47c06956..a8e5e770ce2f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_OVL,
MTK_DISP_OVL_2L,
+ MTK_DISP_OVL_ADAPTOR,
MTK_DISP_PWM,
MTK_DISP_RDMA,
MTK_DISP_UFOE,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6a18c12fe04e..c233069b4cc2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -11,6 +11,7 @@
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
+#include <linux/reset-controller.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -160,12 +161,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_ADAPTOR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +183,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +194,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +203,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +212,226 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_match(struct device *dev, void *data)
+{
+ if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
+ return true;
+ return false;
+}
+
+static int mtk_drm_get_drm_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+ struct device *drm_dev;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
+ if (!drm_dev || !dev_get_drvdata(drm_dev))
+ continue;
+
+ all_drm_priv[cnt++] = dev_get_drvdata(drm_dev);
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +450,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +509,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +539,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +609,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +648,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -485,50 +735,40 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
-
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -548,7 +788,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -559,6 +805,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -572,6 +821,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 7b09fe6db067..867d7b8e788f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372 ++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
7 files changed, 354 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index ebcb646bde9c..c61f5bafd22c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
@@ -87,6 +88,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..0da78adf3b4f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -816,25 +823,25 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ i = (priv->data->mmsys_dev_num > 1) ? 0 : drm_crtc_index(&mtk_crtc->base);
+
mtk_crtc->cmdq_client =
- cmdq_mbox_create(mtk_crtc->mmsys_dev,
- drm_crtc_index(&mtk_crtc->base));
+ cmdq_mbox_create(mtk_crtc->mmsys_dev, i);
if (IS_ERR(mtk_crtc->cmdq_client)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
drm_crtc_index(&mtk_crtc->base));
@@ -844,7 +851,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (mtk_crtc->cmdq_client) {
ret = of_property_read_u32_index(priv->mutex_node,
"mediatek,gce-events",
- drm_crtc_index(&mtk_crtc->base),
+ i,
&mtk_crtc->cmdq_event);
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..a57eb12d7c05 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -17,7 +17,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ee8efc13eaea..9623adbc2277 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -380,6 +380,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+ .layer_nr = mtk_ethdr_layer_nr,
+ .layer_config = mtk_ethdr_layer_config,
+ .enable_vblank = mtk_ethdr_enable_vblank,
+ .disable_vblank = mtk_ethdr_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_AAL] = "aal",
[MTK_DISP_BLS] = "bls",
@@ -393,6 +405,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
+ [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
[MTK_DISP_UFOE] = "ufoe",
@@ -436,6 +449,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -563,6 +577,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_OVL_ADAPTOR ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index b42a47c06956..a8e5e770ce2f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_OVL,
MTK_DISP_OVL_2L,
+ MTK_DISP_OVL_ADAPTOR,
MTK_DISP_PWM,
MTK_DISP_RDMA,
MTK_DISP_UFOE,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6a18c12fe04e..c233069b4cc2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -11,6 +11,7 @@
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
+#include <linux/reset-controller.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -160,12 +161,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_ADAPTOR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +183,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +194,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +203,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +212,226 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_match(struct device *dev, void *data)
+{
+ if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
+ return true;
+ return false;
+}
+
+static int mtk_drm_get_drm_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+ struct device *drm_dev;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
+ if (!drm_dev || !dev_get_drvdata(drm_dev))
+ continue;
+
+ all_drm_priv[cnt++] = dev_get_drvdata(drm_dev);
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +450,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +509,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +539,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +609,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +648,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -485,50 +735,40 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
-
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -548,7 +788,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -559,6 +805,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -572,6 +821,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 7b09fe6db067..867d7b8e788f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-18 9:18 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-18 9:18 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372 ++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
7 files changed, 354 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index ebcb646bde9c..c61f5bafd22c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
@@ -87,6 +88,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..0da78adf3b4f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -816,25 +823,25 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ i = (priv->data->mmsys_dev_num > 1) ? 0 : drm_crtc_index(&mtk_crtc->base);
+
mtk_crtc->cmdq_client =
- cmdq_mbox_create(mtk_crtc->mmsys_dev,
- drm_crtc_index(&mtk_crtc->base));
+ cmdq_mbox_create(mtk_crtc->mmsys_dev, i);
if (IS_ERR(mtk_crtc->cmdq_client)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
drm_crtc_index(&mtk_crtc->base));
@@ -844,7 +851,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (mtk_crtc->cmdq_client) {
ret = of_property_read_u32_index(priv->mutex_node,
"mediatek,gce-events",
- drm_crtc_index(&mtk_crtc->base),
+ i,
&mtk_crtc->cmdq_event);
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..a57eb12d7c05 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -17,7 +17,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ee8efc13eaea..9623adbc2277 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -380,6 +380,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+ .layer_nr = mtk_ethdr_layer_nr,
+ .layer_config = mtk_ethdr_layer_config,
+ .enable_vblank = mtk_ethdr_enable_vblank,
+ .disable_vblank = mtk_ethdr_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_AAL] = "aal",
[MTK_DISP_BLS] = "bls",
@@ -393,6 +405,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
+ [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
[MTK_DISP_UFOE] = "ufoe",
@@ -436,6 +449,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -563,6 +577,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_OVL_ADAPTOR ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index b42a47c06956..a8e5e770ce2f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_OVL,
MTK_DISP_OVL_2L,
+ MTK_DISP_OVL_ADAPTOR,
MTK_DISP_PWM,
MTK_DISP_RDMA,
MTK_DISP_UFOE,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6a18c12fe04e..c233069b4cc2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -11,6 +11,7 @@
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
+#include <linux/reset-controller.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -160,12 +161,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_ADAPTOR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +183,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +194,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +203,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +212,226 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_match(struct device *dev, void *data)
+{
+ if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
+ return true;
+ return false;
+}
+
+static int mtk_drm_get_drm_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+ struct device *drm_dev;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
+ if (!drm_dev || !dev_get_drvdata(drm_dev))
+ continue;
+
+ all_drm_priv[cnt++] = dev_get_drvdata(drm_dev);
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_drm_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +450,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +509,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +539,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +609,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +648,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -485,50 +735,40 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
-
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -548,7 +788,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -559,6 +805,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -572,6 +821,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 7b09fe6db067..867d7b8e788f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
(?)
@ 2021-08-20 23:37 ` Chun-Kuang Hu
-1 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-20 23:37 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
Separate this patch to two patch. One is support two mmsys, and
another one is support mt8195 vdosys1.
Regards,
Chun-Kuang.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372 ++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 354 insertions(+), 74 deletions(-)
>
>
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-20 23:37 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-20 23:37 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
Separate this patch to two patch. One is support two mmsys, and
another one is support mt8195 vdosys1.
Regards,
Chun-Kuang.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372 ++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 354 insertions(+), 74 deletions(-)
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-20 23:37 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-20 23:37 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
Separate this patch to two patch. One is support two mmsys, and
another one is support mt8195 vdosys1.
Regards,
Chun-Kuang.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372 ++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 354 insertions(+), 74 deletions(-)
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-20 23:37 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-20 23:37 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
Separate this patch to two patch. One is support two mmsys, and
another one is support mt8195 vdosys1.
Regards,
Chun-Kuang.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372 ++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 354 insertions(+), 74 deletions(-)
>
>
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-08-20 23:37 ` Chun-Kuang Hu
(?)
@ 2021-08-24 4:53 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:53 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-08-21 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> > up two drm drivers, only one drm driver register as the drm device.
> > Each drm driver binds its own component. The first bind drm driver
> > will allocate the drm device, and the last bind drm driver
> > registers
> > the drm device to drm core. Each crtc path is created with the
> > corresponding drm driver data.
>
> Separate this patch to two patch. One is support two mmsys, and
> another one is support mt8195 vdosys1.
>
> Regards,
> Chun-Kuang.
>
OK, I will separate it into two patches.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372
> > ++++++++++++++++----
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> > 7 files changed, 354 insertions(+), 74 deletions(-)
> >
> >
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-24 4:53 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:53 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-08-21 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> > up two drm drivers, only one drm driver register as the drm device.
> > Each drm driver binds its own component. The first bind drm driver
> > will allocate the drm device, and the last bind drm driver
> > registers
> > the drm device to drm core. Each crtc path is created with the
> > corresponding drm driver data.
>
> Separate this patch to two patch. One is support two mmsys, and
> another one is support mt8195 vdosys1.
>
> Regards,
> Chun-Kuang.
>
OK, I will separate it into two patches.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372
> > ++++++++++++++++----
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> > 7 files changed, 354 insertions(+), 74 deletions(-)
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-24 4:53 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:53 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-08-21 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> > up two drm drivers, only one drm driver register as the drm device.
> > Each drm driver binds its own component. The first bind drm driver
> > will allocate the drm device, and the last bind drm driver
> > registers
> > the drm device to drm core. Each crtc path is created with the
> > corresponding drm driver data.
>
> Separate this patch to two patch. One is support two mmsys, and
> another one is support mt8195 vdosys1.
>
> Regards,
> Chun-Kuang.
>
OK, I will separate it into two patches.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 372
> > ++++++++++++++++----
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> > 7 files changed, 354 insertions(+), 74 deletions(-)
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-08-18 9:18 ` Nancy.Lin
(?)
(?)
@ 2021-08-22 1:14 ` Chun-Kuang Hu
-1 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-22 1:14 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>
>
> +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> + .layer_nr = mtk_ethdr_layer_nr,
> + .layer_config = mtk_ethdr_layer_config,
> + .enable_vblank = mtk_ethdr_enable_vblank,
> + .disable_vblank = mtk_ethdr_disable_vblank,
> +};
I think ethdr is inside the group of ovl_adpator. I preter this
function is implemented by ovl_adaptor, and ovl_adaptor control rdma,
merge, ethdr.
Regards,
Chun-Kuang.
> +
>
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-22 1:14 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-22 1:14 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>
>
> +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> + .layer_nr = mtk_ethdr_layer_nr,
> + .layer_config = mtk_ethdr_layer_config,
> + .enable_vblank = mtk_ethdr_enable_vblank,
> + .disable_vblank = mtk_ethdr_disable_vblank,
> +};
I think ethdr is inside the group of ovl_adpator. I preter this
function is implemented by ovl_adaptor, and ovl_adaptor control rdma,
merge, ethdr.
Regards,
Chun-Kuang.
> +
>
_______________________________________________
linux-arm-kernel mailing list
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^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-22 1:14 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-22 1:14 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>
>
> +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> + .layer_nr = mtk_ethdr_layer_nr,
> + .layer_config = mtk_ethdr_layer_config,
> + .enable_vblank = mtk_ethdr_enable_vblank,
> + .disable_vblank = mtk_ethdr_disable_vblank,
> +};
I think ethdr is inside the group of ovl_adpator. I preter this
function is implemented by ovl_adaptor, and ovl_adaptor control rdma,
merge, ethdr.
Regards,
Chun-Kuang.
> +
>
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-22 1:14 ` Chun-Kuang Hu
0 siblings, 0 replies; 78+ messages in thread
From: Chun-Kuang Hu @ 2021-08-22 1:14 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
>
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>
>
> +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> + .layer_nr = mtk_ethdr_layer_nr,
> + .layer_config = mtk_ethdr_layer_config,
> + .enable_vblank = mtk_ethdr_enable_vblank,
> + .disable_vblank = mtk_ethdr_disable_vblank,
> +};
I think ethdr is inside the group of ovl_adpator. I preter this
function is implemented by ovl_adaptor, and ovl_adaptor control rdma,
merge, ethdr.
Regards,
Chun-Kuang.
> +
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-08-22 1:14 ` Chun-Kuang Hu
(?)
@ 2021-08-24 4:52 ` Nancy.Lin
-1 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:52 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 09:14 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> > up two drm drivers, only one drm driver register as the drm device.
> > Each drm driver binds its own component. The first bind drm driver
> > will allocate the drm device, and the last bind drm driver
> > registers
> > the drm device to drm core. Each crtc path is created with the
> > corresponding drm driver data.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> >
> >
> > +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> > + .clk_enable = mtk_ethdr_clk_enable,
> > + .clk_disable = mtk_ethdr_clk_disable,
> > + .config = mtk_ethdr_config,
> > + .start = mtk_ethdr_start,
> > + .stop = mtk_ethdr_stop,
> > + .layer_nr = mtk_ethdr_layer_nr,
> > + .layer_config = mtk_ethdr_layer_config,
> > + .enable_vblank = mtk_ethdr_enable_vblank,
> > + .disable_vblank = mtk_ethdr_disable_vblank,
> > +};
>
> I think ethdr is inside the group of ovl_adpator. I preter this
> function is implemented by ovl_adaptor, and ovl_adaptor control rdma,
> merge, ethdr.
>
> Regards,
> Chun-Kuang.
>
OK, I will change it to the ovl_adaptor function.
> > +
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-24 4:52 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:52 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 09:14 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> > up two drm drivers, only one drm driver register as the drm device.
> > Each drm driver binds its own component. The first bind drm driver
> > will allocate the drm device, and the last bind drm driver
> > registers
> > the drm device to drm core. Each crtc path is created with the
> > corresponding drm driver data.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> >
> >
> > +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> > + .clk_enable = mtk_ethdr_clk_enable,
> > + .clk_disable = mtk_ethdr_clk_disable,
> > + .config = mtk_ethdr_config,
> > + .start = mtk_ethdr_start,
> > + .stop = mtk_ethdr_stop,
> > + .layer_nr = mtk_ethdr_layer_nr,
> > + .layer_config = mtk_ethdr_layer_config,
> > + .enable_vblank = mtk_ethdr_enable_vblank,
> > + .disable_vblank = mtk_ethdr_disable_vblank,
> > +};
>
> I think ethdr is inside the group of ovl_adpator. I preter this
> function is implemented by ovl_adaptor, and ovl_adaptor control rdma,
> merge, ethdr.
>
> Regards,
> Chun-Kuang.
>
OK, I will change it to the ovl_adaptor function.
> > +
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 78+ messages in thread* Re: [PATCH v3 15/15] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-24 4:52 ` Nancy.Lin
0 siblings, 0 replies; 78+ messages in thread
From: Nancy.Lin @ 2021-08-24 4:52 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 09:14 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> > up two drm drivers, only one drm driver register as the drm device.
> > Each drm driver binds its own component. The first bind drm driver
> > will allocate the drm device, and the last bind drm driver
> > registers
> > the drm device to drm core. Each crtc path is created with the
> > corresponding drm driver data.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> >
> >
> > +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> > + .clk_enable = mtk_ethdr_clk_enable,
> > + .clk_disable = mtk_ethdr_clk_disable,
> > + .config = mtk_ethdr_config,
> > + .start = mtk_ethdr_start,
> > + .stop = mtk_ethdr_stop,
> > + .layer_nr = mtk_ethdr_layer_nr,
> > + .layer_config = mtk_ethdr_layer_config,
> > + .enable_vblank = mtk_ethdr_enable_vblank,
> > + .disable_vblank = mtk_ethdr_disable_vblank,
> > +};
>
> I think ethdr is inside the group of ovl_adpator. I preter this
> function is implemented by ovl_adaptor, and ovl_adaptor control rdma,
> merge, ethdr.
>
> Regards,
> Chun-Kuang.
>
OK, I will change it to the ovl_adaptor function.
> > +
> >
^ permalink raw reply [flat|nested] 78+ messages in thread