From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <daniel.vetter@ffwll.ch>, <tony.ye@intel.com>, <zhengguo.xu@intel.com> Subject: [PATCH 25/27] drm/i915/guc: Handle errors in multi-lrc requests Date: Fri, 20 Aug 2021 15:44:44 -0700 [thread overview] Message-ID: <20210820224446.30620-26-matthew.brost@intel.com> (raw) In-Reply-To: <20210820224446.30620-1-matthew.brost@intel.com> If an error occurs in the front end when multi-lrc requests are getting generated we need to skip these in the backend but we still need to emit the breadcrumbs seqno. An issues arrises because with multi-lrc breadcrumbs there is a handshake between the parent and children to make forwad progress. If all the requests are not present this handshake doesn't work. To work around this, if multi-lrc request has an error we skip the handshake but still emit the breadcrumbs seqno. Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 61 ++++++++++++++++++- 1 file changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 2ef38557b0f0..61e737fd1eee 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3546,8 +3546,8 @@ static int emit_bb_start_child_no_preempt_mid_batch(struct i915_request *rq, } static u32 * -emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, - u32 *cs) +__emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) { struct intel_context *ce = rq->context; u8 i; @@ -3575,6 +3575,41 @@ emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, get_children_go_addr(ce), 0); + return cs; +} + +/* + * If this true, a submission of multi-lrc requests had an error and the + * requests need to be skipped. The front end (execuf IOCTL) should've called + * i915_request_skip which squashes the BB but we still need to emit the fini + * breadrcrumbs seqno write. At this point we don't know how many of the + * requests in the multi-lrc submission were generated so we can't do the + * handshake between the parent and children (e.g. if 4 requests should be + * generated but 2nd hit an error only 1 would be seen by the GuC backend). + * Simply skip the handshake, but still emit the breadcrumbd seqno, if an error + * has occurred on any of the requests in submission / relationship. + */ +static inline bool skip_handshake(struct i915_request *rq) +{ + return test_bit(I915_FENCE_FLAG_SKIP_PARALLEL, &rq->fence.flags); +} + +static u32 * +emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) +{ + struct intel_context *ce = rq->context; + + GEM_BUG_ON(!intel_context_is_parent(ce)); + + if (unlikely(skip_handshake(rq))) { + memset(cs, 0, sizeof(u32) * + (ce->engine->emit_fini_breadcrumb_dw - 6)); + cs += ce->engine->emit_fini_breadcrumb_dw - 6; + } else { + cs = __emit_fini_breadcrumb_parent_no_preempt_mid_batch(rq, cs); + } + /* Emit fini breadcrumb */ cs = gen8_emit_ggtt_write(cs, rq->fence.seqno, @@ -3591,7 +3626,8 @@ emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, } static u32 * -emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, u32 *cs) +__emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) { struct intel_context *ce = rq->context; @@ -3617,6 +3653,25 @@ emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, u32 *cs *cs++ = get_children_go_addr(ce->parent); *cs++ = 0; + return cs; +} + +static u32 * +emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) +{ + struct intel_context *ce = rq->context; + + GEM_BUG_ON(!intel_context_is_child(ce)); + + if (unlikely(skip_handshake(rq))) { + memset(cs, 0, sizeof(u32) * + (ce->engine->emit_fini_breadcrumb_dw - 6)); + cs += ce->engine->emit_fini_breadcrumb_dw - 6; + } else { + cs = __emit_fini_breadcrumb_child_no_preempt_mid_batch(rq, cs); + } + /* Emit fini breadcrumb */ cs = gen8_emit_ggtt_write(cs, rq->fence.seqno, -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <daniel.vetter@ffwll.ch>, <tony.ye@intel.com>, <zhengguo.xu@intel.com> Subject: [Intel-gfx] [PATCH 25/27] drm/i915/guc: Handle errors in multi-lrc requests Date: Fri, 20 Aug 2021 15:44:44 -0700 [thread overview] Message-ID: <20210820224446.30620-26-matthew.brost@intel.com> (raw) In-Reply-To: <20210820224446.30620-1-matthew.brost@intel.com> If an error occurs in the front end when multi-lrc requests are getting generated we need to skip these in the backend but we still need to emit the breadcrumbs seqno. An issues arrises because with multi-lrc breadcrumbs there is a handshake between the parent and children to make forwad progress. If all the requests are not present this handshake doesn't work. To work around this, if multi-lrc request has an error we skip the handshake but still emit the breadcrumbs seqno. Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 61 ++++++++++++++++++- 1 file changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 2ef38557b0f0..61e737fd1eee 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3546,8 +3546,8 @@ static int emit_bb_start_child_no_preempt_mid_batch(struct i915_request *rq, } static u32 * -emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, - u32 *cs) +__emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) { struct intel_context *ce = rq->context; u8 i; @@ -3575,6 +3575,41 @@ emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, get_children_go_addr(ce), 0); + return cs; +} + +/* + * If this true, a submission of multi-lrc requests had an error and the + * requests need to be skipped. The front end (execuf IOCTL) should've called + * i915_request_skip which squashes the BB but we still need to emit the fini + * breadrcrumbs seqno write. At this point we don't know how many of the + * requests in the multi-lrc submission were generated so we can't do the + * handshake between the parent and children (e.g. if 4 requests should be + * generated but 2nd hit an error only 1 would be seen by the GuC backend). + * Simply skip the handshake, but still emit the breadcrumbd seqno, if an error + * has occurred on any of the requests in submission / relationship. + */ +static inline bool skip_handshake(struct i915_request *rq) +{ + return test_bit(I915_FENCE_FLAG_SKIP_PARALLEL, &rq->fence.flags); +} + +static u32 * +emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) +{ + struct intel_context *ce = rq->context; + + GEM_BUG_ON(!intel_context_is_parent(ce)); + + if (unlikely(skip_handshake(rq))) { + memset(cs, 0, sizeof(u32) * + (ce->engine->emit_fini_breadcrumb_dw - 6)); + cs += ce->engine->emit_fini_breadcrumb_dw - 6; + } else { + cs = __emit_fini_breadcrumb_parent_no_preempt_mid_batch(rq, cs); + } + /* Emit fini breadcrumb */ cs = gen8_emit_ggtt_write(cs, rq->fence.seqno, @@ -3591,7 +3626,8 @@ emit_fini_breadcrumb_parent_no_preempt_mid_batch(struct i915_request *rq, } static u32 * -emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, u32 *cs) +__emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) { struct intel_context *ce = rq->context; @@ -3617,6 +3653,25 @@ emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, u32 *cs *cs++ = get_children_go_addr(ce->parent); *cs++ = 0; + return cs; +} + +static u32 * +emit_fini_breadcrumb_child_no_preempt_mid_batch(struct i915_request *rq, + u32 *cs) +{ + struct intel_context *ce = rq->context; + + GEM_BUG_ON(!intel_context_is_child(ce)); + + if (unlikely(skip_handshake(rq))) { + memset(cs, 0, sizeof(u32) * + (ce->engine->emit_fini_breadcrumb_dw - 6)); + cs += ce->engine->emit_fini_breadcrumb_dw - 6; + } else { + cs = __emit_fini_breadcrumb_child_no_preempt_mid_batch(rq, cs); + } + /* Emit fini breadcrumb */ cs = gen8_emit_ggtt_write(cs, rq->fence.seqno, -- 2.32.0
next prev parent reply other threads:[~2021-08-20 22:51 UTC|newest] Thread overview: 145+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-20 22:44 [PATCH 00/27] Parallel submission aka multi-bb execbuf Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 01/27] drm/i915/guc: Squash Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 02/27] drm/i915/guc: Allow flexible number of context ids Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:13 ` John Harrison 2021-09-10 0:14 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 03/27] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:16 ` John Harrison 2021-09-10 0:16 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 04/27] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:28 ` John Harrison 2021-09-10 0:21 ` Matthew Brost 2021-09-13 9:55 ` Tvrtko Ursulin 2021-09-13 17:12 ` Matthew Brost 2021-09-14 8:41 ` Tvrtko Ursulin 2021-08-20 22:44 ` [PATCH 05/27] drm/i915: Add GT PM unpark worker Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:36 ` John Harrison 2021-09-10 0:34 ` Matthew Brost 2021-09-10 8:36 ` Tvrtko Ursulin 2021-09-10 20:09 ` Matthew Brost 2021-09-13 10:33 ` Tvrtko Ursulin 2021-09-13 17:20 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 06/27] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:46 ` John Harrison 2021-09-10 0:41 ` Matthew Brost 2021-09-13 22:26 ` John Harrison 2021-09-14 1:12 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 07/27] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:51 ` John Harrison 2021-09-13 16:54 ` Matthew Brost 2021-09-13 22:38 ` John Harrison 2021-09-14 5:02 ` Matthew Brost 2021-09-13 16:55 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 08/27] drm/i915: Add logical engine mapping Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-10 11:12 ` Tvrtko Ursulin 2021-09-10 19:49 ` Matthew Brost 2021-09-13 9:24 ` Tvrtko Ursulin 2021-09-13 16:50 ` Matthew Brost 2021-09-14 8:34 ` Tvrtko Ursulin 2021-09-14 18:04 ` Matthew Brost 2021-09-15 8:24 ` Tvrtko Ursulin 2021-09-15 16:58 ` Matthew Brost 2021-09-16 8:31 ` Tvrtko Ursulin 2021-08-20 22:44 ` [PATCH 09/27] drm/i915: Expose logical engine instance to user Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-13 23:06 ` John Harrison 2021-09-14 1:08 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 10/27] drm/i915/guc: Introduce context parent-child relationship Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-13 23:19 ` John Harrison 2021-09-14 1:18 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 11/27] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 12/27] drm/i915/guc: Add multi-lrc context registration Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-15 19:21 ` John Harrison 2021-09-15 19:31 ` Matthew Brost 2021-09-15 20:23 ` John Harrison 2021-09-15 20:33 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 13/27] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-15 19:24 ` John Harrison 2021-09-15 19:34 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 14/27] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-15 20:04 ` John Harrison 2021-09-15 20:55 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 15/27] drm/i915/guc: Implement multi-lrc submission Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-21 14:04 ` kernel test robot 2021-08-21 14:04 ` kernel test robot 2021-08-21 14:04 ` kernel test robot 2021-08-22 2:18 ` kernel test robot 2021-08-22 2:18 ` kernel test robot 2021-08-22 2:18 ` [Intel-gfx] " kernel test robot 2021-09-20 21:48 ` John Harrison 2021-09-22 16:25 ` Matthew Brost 2021-09-22 20:15 ` John Harrison 2021-09-23 2:44 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 16/27] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-20 21:57 ` John Harrison 2021-08-20 22:44 ` [PATCH 17/27] drm/i915/guc: Implement multi-lrc reset Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-20 22:44 ` John Harrison 2021-09-22 16:16 ` Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] [PATCH 18/27] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost 2021-08-20 22:44 ` Matthew Brost 2021-09-20 22:48 ` [Intel-gfx] " John Harrison 2021-09-21 19:13 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 19/27] drm/i915: Fix bug in user proto-context creation that leaked contexts Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-20 22:57 ` John Harrison 2021-09-21 14:49 ` Tvrtko Ursulin 2021-09-21 19:28 ` Matthew Brost 2021-09-21 19:28 ` Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] [PATCH 20/27] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost 2021-08-20 22:44 ` Matthew Brost 2021-08-29 4:00 ` [Intel-gfx] " kernel test robot 2021-08-29 4:00 ` kernel test robot 2021-08-29 19:59 ` kernel test robot 2021-08-29 19:59 ` kernel test robot 2021-09-21 0:09 ` John Harrison 2021-09-22 16:38 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 21/27] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-21 0:12 ` John Harrison 2021-08-20 22:44 ` [PATCH 22/27] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-28 20:47 ` John Harrison 2021-08-20 22:44 ` [PATCH 23/27] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-10 11:25 ` Tvrtko Ursulin 2021-09-10 20:49 ` Matthew Brost 2021-09-13 10:52 ` Tvrtko Ursulin 2021-09-28 22:20 ` John Harrison 2021-09-28 22:33 ` Matthew Brost 2021-09-28 23:33 ` John Harrison 2021-09-29 0:22 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 24/27] drm/i915: Multi-BB execbuf Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-21 19:01 ` kernel test robot 2021-08-21 19:01 ` kernel test robot 2021-08-30 3:46 ` kernel test robot 2021-08-30 3:46 ` kernel test robot 2021-09-30 22:16 ` Matthew Brost 2021-08-20 22:44 ` Matthew Brost [this message] 2021-08-20 22:44 ` [Intel-gfx] [PATCH 25/27] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost 2021-09-29 20:44 ` John Harrison 2021-09-29 20:58 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 26/27] drm/i915: Enable multi-bb execbuf Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 27/27] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 23:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev3) Patchwork 2021-08-20 23:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-08-20 23:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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