From: Billy Tsai <billy_tsai@aspeedtech.com> To: <jic23@kernel.org>, <lars@metafoo.de>, <pmeerw@pmeerw.net>, <robh+dt@kernel.org>, <joel@jms.id.au>, <andrew@aj.id.au>, <p.zabel@pengutronix.de>, <lgirdwood@gmail.com>, <broonie@kernel.org>, <linux-iio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org> Cc: <BMC-SW@aspeedtech.com> Subject: [v5 13/15] iio: adc: aspeed: Add compensation phase. Date: Tue, 31 Aug 2021 15:14:56 +0800 [thread overview] Message-ID: <20210831071458.2334-14-billy_tsai@aspeedtech.com> (raw) In-Reply-To: <20210831071458.2334-1-billy_tsai@aspeedtech.com> This patch adds a compensation phase to improve the accuracy of ADC measurement. This is the built-in function through input half of the reference voltage to get the ADC offset. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> --- drivers/iio/adc/aspeed_adc.c | 54 +++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 1333d7a88427..121c96de03bd 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -103,6 +103,7 @@ struct aspeed_adc_data { struct reset_control *rst; int vref_mv; u32 sample_period_ns; + int cv; }; #define ASPEED_CHAN(_idx, _data_reg_addr) { \ @@ -112,7 +113,8 @@ struct aspeed_adc_data { .address = (_data_reg_addr), \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ } static const struct iio_chan_spec aspeed_adc_iio_channels[] = { @@ -134,6 +136,51 @@ static const struct iio_chan_spec aspeed_adc_iio_channels[] = { ASPEED_CHAN(15, 0x2E), }; +static int aspeed_adc_compensation(struct iio_dev *indio_dev) +{ + struct aspeed_adc_data *data = iio_priv(indio_dev); + u32 index, adc_raw = 0; + u32 adc_engine_control_reg_val; + + adc_engine_control_reg_val = + readl(data->base + ASPEED_REG_ENGINE_CONTROL); + adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE; + adc_engine_control_reg_val |= + (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | + ASPEED_ADC_ENGINE_ENABLE); + /* + * Enable compensating sensing: + * After that, the input voltage of ADC will force to half of the reference + * voltage. So the expected reading raw data will become half of the max + * value. We can get compensating value = 0x200 - ADC read raw value. + * It is recommended to average at least 10 samples to get a final CV. + */ + writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION | + ASPEED_ADC_CTRL_CHANNEL_ENABLE(0), + data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable compensating sensing mode need to wait some time for ADC stable + * Experiment result is 1ms. + */ + mdelay(1); + + for (index = 0; index < 16; index++) { + /* + * Waiting for the sampling period ensures that the value acquired + * is fresh each time. + */ + ndelay(data->sample_period_ns); + adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address); + } + adc_raw >>= 4; + data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw; + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); + dev_dbg(data->dev, "Compensating value = %d\n", data->cv); + + return 0; +} + static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate) { struct aspeed_adc_data *data = iio_priv(indio_dev); @@ -163,6 +210,10 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, *val = readw(data->base + chan->address); return IIO_VAL_INT; + case IIO_CHAN_INFO_OFFSET: + *val = data->cv; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: *val = data->vref_mv; *val2 = ASPEED_RESOLUTION_BITS; @@ -466,6 +517,7 @@ static int aspeed_adc_probe(struct platform_device *pdev) return ret; } + aspeed_adc_compensation(indio_dev); /* Start all channels in normal mode. */ adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Billy Tsai <billy_tsai@aspeedtech.com> To: <jic23@kernel.org>, <lars@metafoo.de>, <pmeerw@pmeerw.net>, <robh+dt@kernel.org>, <joel@jms.id.au>, <andrew@aj.id.au>, <p.zabel@pengutronix.de>, <lgirdwood@gmail.com>, <broonie@kernel.org>, <linux-iio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org> Cc: <BMC-SW@aspeedtech.com> Subject: [v5 13/15] iio: adc: aspeed: Add compensation phase. Date: Tue, 31 Aug 2021 15:14:56 +0800 [thread overview] Message-ID: <20210831071458.2334-14-billy_tsai@aspeedtech.com> (raw) In-Reply-To: <20210831071458.2334-1-billy_tsai@aspeedtech.com> This patch adds a compensation phase to improve the accuracy of ADC measurement. This is the built-in function through input half of the reference voltage to get the ADC offset. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> --- drivers/iio/adc/aspeed_adc.c | 54 +++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 1333d7a88427..121c96de03bd 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -103,6 +103,7 @@ struct aspeed_adc_data { struct reset_control *rst; int vref_mv; u32 sample_period_ns; + int cv; }; #define ASPEED_CHAN(_idx, _data_reg_addr) { \ @@ -112,7 +113,8 @@ struct aspeed_adc_data { .address = (_data_reg_addr), \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ } static const struct iio_chan_spec aspeed_adc_iio_channels[] = { @@ -134,6 +136,51 @@ static const struct iio_chan_spec aspeed_adc_iio_channels[] = { ASPEED_CHAN(15, 0x2E), }; +static int aspeed_adc_compensation(struct iio_dev *indio_dev) +{ + struct aspeed_adc_data *data = iio_priv(indio_dev); + u32 index, adc_raw = 0; + u32 adc_engine_control_reg_val; + + adc_engine_control_reg_val = + readl(data->base + ASPEED_REG_ENGINE_CONTROL); + adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE; + adc_engine_control_reg_val |= + (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | + ASPEED_ADC_ENGINE_ENABLE); + /* + * Enable compensating sensing: + * After that, the input voltage of ADC will force to half of the reference + * voltage. So the expected reading raw data will become half of the max + * value. We can get compensating value = 0x200 - ADC read raw value. + * It is recommended to average at least 10 samples to get a final CV. + */ + writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION | + ASPEED_ADC_CTRL_CHANNEL_ENABLE(0), + data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable compensating sensing mode need to wait some time for ADC stable + * Experiment result is 1ms. + */ + mdelay(1); + + for (index = 0; index < 16; index++) { + /* + * Waiting for the sampling period ensures that the value acquired + * is fresh each time. + */ + ndelay(data->sample_period_ns); + adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address); + } + adc_raw >>= 4; + data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw; + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); + dev_dbg(data->dev, "Compensating value = %d\n", data->cv); + + return 0; +} + static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate) { struct aspeed_adc_data *data = iio_priv(indio_dev); @@ -163,6 +210,10 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, *val = readw(data->base + chan->address); return IIO_VAL_INT; + case IIO_CHAN_INFO_OFFSET: + *val = data->cv; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: *val = data->vref_mv; *val2 = ASPEED_RESOLUTION_BITS; @@ -466,6 +517,7 @@ static int aspeed_adc_probe(struct platform_device *pdev) return ret; } + aspeed_adc_compensation(indio_dev); /* Start all channels in normal mode. */ adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-31 7:16 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-31 7:14 [v5 00/15] Add support for ast2600 ADC Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 01/15] iio: adc: aspeed: set driver data when adc probe Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:25 ` Jonathan Cameron 2021-09-05 14:25 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 02/15] dt-bindings: iio: adc: Add ast2600-adc bindings Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-01 1:38 ` Rob Herring 2021-09-01 1:38 ` Rob Herring 2021-09-05 14:27 ` Jonathan Cameron 2021-09-05 14:27 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 03/15] iio: adc: aspeed: completes the bitfield declare Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:30 ` Jonathan Cameron 2021-09-05 14:30 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 04/15] iio: adc: aspeed: Keep model data to driver data Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:33 ` Jonathan Cameron 2021-09-05 14:33 ` Jonathan Cameron 2021-09-05 14:50 ` Jonathan Cameron 2021-09-05 14:50 ` Jonathan Cameron 2021-09-16 3:52 ` Joel Stanley 2021-09-16 3:52 ` Joel Stanley 2021-09-18 17:55 ` Jonathan Cameron 2021-09-18 17:55 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 05/15] iio: adc: aspeed: Refactory model data structure Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:37 ` Jonathan Cameron 2021-09-05 14:37 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 06/15] iio: adc: aspeed: Add vref config function Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 07/15] iio: adc: aspeed: Set num_channels with model data Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 08/15] iio: adc: aspeed: Use model_data to set clk scaler Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 09/15] iio: adc: aspeed: Use devm_add_action_or_reset Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:51 ` Philipp Zabel 2021-08-31 7:51 ` Philipp Zabel 2021-08-31 7:14 ` [v5 10/15] iio: adc: aspeed: Support ast2600 adc Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 11/15] iio: adc: aspeed: Fix the calculate error of clock Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:47 ` Jonathan Cameron 2021-09-05 14:47 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 12/15] iio: adc: aspeed: Add func to set sampling rate Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` Billy Tsai [this message] 2021-08-31 7:14 ` [v5 13/15] iio: adc: aspeed: Add compensation phase Billy Tsai 2021-08-31 7:14 ` [v5 14/15] iio: adc: aspeed: Support battery sensing Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 15/15] iio: adc: aspeed: Get and set trimming data Billy Tsai 2021-08-31 7:14 ` Billy Tsai
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