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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
	Kito Cheng <kito.cheng@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()
Date: Sat,  4 Sep 2021 22:35:00 +0200	[thread overview]
Message-ID: <20210904203516.2570119-2-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20210904203516.2570119-1-philipp.tomsich@vrull.eu>

Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1.  Fix these
regressions by introducing a temporary.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---

Changes in v10:
- new patch

 target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b72e76255c..c0a6e25826 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3)
 
 static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
 {
-    tcg_gen_ext32u_tl(arg1, arg1);
-    tcg_gen_add_tl(ret, arg1, arg2);
+    TCGv t = tcg_temp_new();
+    tcg_gen_ext32u_tl(t, arg1);
+    tcg_gen_add_tl(ret, t, arg2);
+    tcg_temp_free(t);
 }
 
 static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
-- 
2.25.1



  reply	other threads:[~2021-09-04 20:41 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-04 20:35 ` Philipp Tomsich [this message]
2021-09-05  8:03   ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Richard Henderson
2021-09-06  5:45   ` Alistair Francis
2021-09-08  5:13   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-05  8:06   ` Richard Henderson
2021-09-06  5:45   ` Alistair Francis
2021-09-08  5:14   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
2021-09-05  8:11   ` Richard Henderson
2021-09-05  9:01     ` Philipp Tomsich
2021-09-10 13:36       ` Philipp Tomsich
2021-09-10 13:40         ` Richard Henderson
2021-09-10 13:47           ` Philipp Tomsich
2021-09-10 13:57             ` Richard Henderson
2021-09-04 20:35 ` [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-09-08  5:16   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-09-08  5:22   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-09-08  5:19   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-09-08  5:21   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-09-08  5:22   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-09-08  5:24   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-09-08  5:25   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
2021-09-08  5:27   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich

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