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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
	Kito Cheng <kito.cheng@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
Date: Sat,  4 Sep 2021 22:35:06 +0200	[thread overview]
Message-ID: <20210904203516.2570119-8-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20210904203516.2570119-1-philipp.tomsich@vrull.eu>

The Zb[abcs] ratification package does not include the proposed
shift-one instructions. There currently is no clear plan to whether
these (or variants of them) will be ratified as Zbo (or a different
extension) or what the timeframe for such a decision could be.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---

(no changes since v3)

Changes in v3:
- Remove shift-one instructions in a separate commit.

 target/riscv/insn32.decode              |  8 ---
 target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
 2 files changed, 78 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b499691a9e..e0f6e315a2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -693,8 +693,6 @@ bset       0010100 .......... 001 ..... 0110011 @r
 bclr       0100100 .......... 001 ..... 0110011 @r
 binv       0110100 .......... 001 ..... 0110011 @r
 bext       0100100 .......... 101 ..... 0110011 @r
-slo        0010000 .......... 001 ..... 0110011 @r
-sro        0010000 .......... 101 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
@@ -704,8 +702,6 @@ bseti      00101. ........... 001 ..... 0010011 @sh
 bclri      01001. ........... 001 ..... 0010011 @sh
 binvi      01101. ........... 001 ..... 0010011 @sh
 bexti      01001. ........... 101 ..... 0010011 @sh
-sloi       00100. ........... 001 ..... 0010011 @sh
-sroi       00100. ........... 101 ..... 0010011 @sh
 rori       01100. ........... 101 ..... 0010011 @sh
 grevi      01101. ........... 101 ..... 0010011 @sh
 gorci      00101. ........... 101 ..... 0010011 @sh
@@ -717,15 +713,11 @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
-slow       0010000 .......... 001 ..... 0111011 @r
-srow       0010000 .......... 101 ..... 0111011 @r
 rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
 gorcw      0010100 .......... 101 ..... 0111011 @r
 
-sloiw      0010000 .......... 001 ..... 0011011 @sh5
-sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index ca92920efd..9891c4912a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -237,44 +237,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
 }
 
-static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_not_tl(ret, arg1);
-    tcg_gen_shl_tl(ret, ret, arg2);
-    tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_slo(DisasContext *ctx, arg_slo *a)
-{
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
-{
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
-}
-
-static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_not_tl(ret, arg1);
-    tcg_gen_shr_tl(ret, ret, arg2);
-    tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_sro(DisasContext *ctx, arg_sro *a)
-{
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
-}
-
-static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
-{
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
-}
-
 static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -420,38 +382,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
     return gen_arith(ctx, a, EXT_NONE, gen_packuw);
 }
 
-static bool trans_slow(DisasContext *ctx, arg_slow *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_srow(DisasContext *ctx, arg_srow *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
-}
-
-static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
-}
-
 static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 {
     TCGv_i32 t1 = tcg_temp_new_i32();
-- 
2.25.1



  parent reply	other threads:[~2021-09-04 20:41 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-05  8:03   ` Richard Henderson
2021-09-06  5:45   ` Alistair Francis
2021-09-08  5:13   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-05  8:06   ` Richard Henderson
2021-09-06  5:45   ` Alistair Francis
2021-09-08  5:14   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
2021-09-05  8:11   ` Richard Henderson
2021-09-05  9:01     ` Philipp Tomsich
2021-09-10 13:36       ` Philipp Tomsich
2021-09-10 13:40         ` Richard Henderson
2021-09-10 13:47           ` Philipp Tomsich
2021-09-10 13:57             ` Richard Henderson
2021-09-04 20:35 ` [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-09-08  5:16   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-09-08  5:22   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-09-08  5:19   ` Bin Meng
2021-09-04 20:35 ` Philipp Tomsich [this message]
2021-09-08  5:21   ` [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Bin Meng
2021-09-04 20:35 ` [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-09-08  5:22   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-09-08  5:24   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-09-08  5:25   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
2021-09-08  5:27   ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich

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