From: Bin Meng <bmeng.cn@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension
Date: Wed, 8 Sep 2021 13:22:08 +0800 [thread overview]
Message-ID: <CAEUhbmX2KhWU3PNOeEWXdT4-RqpzS7-bd4PMeWrP9YAi44vh2Q@mail.gmail.com> (raw)
In-Reply-To: <20210904203516.2570119-6-philipp.tomsich@vrull.eu>
On Sun, Sep 5, 2021 at 4:38 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The following instructions are part of Zba:
> - add.uw (RV64 only)
> - sh[123]add (RV32 and RV64)
> - sh[123]add.uw (RV64-only)
> - slli.uw (RV64-only)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> Changes in v10:
> - Split off gen_add_uw() fix into a separate patch, as requested.
>
> Changes in v9:
> - Rebased to 8880cc4362.
> - Update gen_add_uw() to use a temporary instead of messing with
> arg1 (fixes a regression after rebase on CF3 and SPEC2017).
>
> Changes in v3:
> - The changes to the Zba instructions (i.e. the REQUIRE_ZBA macro
> and its use for qualifying the Zba instructions) are moved into
> a separate commit.
>
> target/riscv/insn32.decode | 20 ++++++++++++--------
> target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2021-09-08 5:24 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-05 8:03 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:13 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-05 8:06 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:14 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
2021-09-05 8:11 ` Richard Henderson
2021-09-05 9:01 ` Philipp Tomsich
2021-09-10 13:36 ` Philipp Tomsich
2021-09-10 13:40 ` Richard Henderson
2021-09-10 13:47 ` Philipp Tomsich
2021-09-10 13:57 ` Richard Henderson
2021-09-04 20:35 ` [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-09-08 5:16 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-09-08 5:22 ` Bin Meng [this message]
2021-09-04 20:35 ` [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-09-08 5:19 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-09-08 5:21 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-09-08 5:22 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-09-08 5:24 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-09-08 5:25 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
2021-09-08 5:27 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
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