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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	Matt Roper <matthew.d.roper@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Aravind Iddamsetty <aravind.iddamsetty@intel.com>,
	Prasad Nallani <prasad.nallani@intel.com>
Subject: [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor
Date: Tue,  7 Sep 2021 10:19:14 -0700	[thread overview]
Message-ID: <20210907171916.2548047-7-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210907171916.2548047-1-matthew.d.roper@intel.com>

In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.

The context priority is set to 'low' at creation time and relies on the
existing context priority to set it to low/normal/high.

HSDES: 1604462009
Bspec: 46145, 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Prasad Nallani <prasad.nallani@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c            |  4 +++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h         |  1 +
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c |  6 +++++-
 drivers/gpu/drm/i915/gt/intel_lrc.h                  | 10 ++++++++++
 drivers/gpu/drm/i915/i915_reg.h                      |  4 ++++
 5 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b346b946602d..2f719f0ecac3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 		engine->props.preempt_timeout_ms = 0;
 
 	/* features common between engines sharing EUs */
-	if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+	if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
 		engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+		engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
+	}
 
 	engine->defaults = engine->props; /* never to change again */
 
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 30a0c69c36c8..00bf0296b28a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -455,6 +455,7 @@ struct intel_engine_cs {
 #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
 #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
 #define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
+#define I915_ENGINE_HAS_EU_PRIORITY    BIT(10)
 	unsigned int flags;
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4c600c46414d..2b36ec7f3a04 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct i915_request *rq)
 static u64 execlists_update_context(struct i915_request *rq)
 {
 	struct intel_context *ce = rq->context;
-	u64 desc = ce->lrc.desc;
+	u64 desc;
 	u32 tail, prev;
 
+	desc = ce->lrc.desc;
+	if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+		desc |= lrc_desc_priority(rq_prio(rq));
+
 	/*
 	 * WaIdleLiteRestore:bdw,skl
 	 *
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 7f697845c4cf..d3f2096b3d51 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context *ce)
 	return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
 }
 
+static inline u32 lrc_desc_priority(int prio)
+{
+	if (prio > I915_PRIORITY_NORMAL)
+		return GEN12_CTX_PRIORITY_HIGH;
+	else if (prio < I915_PRIORITY_NORMAL)
+		return GEN12_CTX_PRIORITY_LOW;
+	else
+		return GEN12_CTX_PRIORITY_NORMAL;
+}
+
 #endif /* __INTEL_LRC_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bb185ce9529..5b68c02c35af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,10 @@ enum {
 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
 #define GEN8_CTX_PRIVILEGE (1 << 8)
 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9)
+#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
+#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
+#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
 
 #define GEN8_CTX_ID_SHIFT 32
 #define GEN8_CTX_ID_WIDTH 21
-- 
2.25.4


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	Matt Roper <matthew.d.roper@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Aravind Iddamsetty <aravind.iddamsetty@intel.com>,
	Prasad Nallani <prasad.nallani@intel.com>
Subject: [Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor
Date: Tue,  7 Sep 2021 10:19:14 -0700	[thread overview]
Message-ID: <20210907171916.2548047-7-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210907171916.2548047-1-matthew.d.roper@intel.com>

In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.

The context priority is set to 'low' at creation time and relies on the
existing context priority to set it to low/normal/high.

HSDES: 1604462009
Bspec: 46145, 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Prasad Nallani <prasad.nallani@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c            |  4 +++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h         |  1 +
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c |  6 +++++-
 drivers/gpu/drm/i915/gt/intel_lrc.h                  | 10 ++++++++++
 drivers/gpu/drm/i915/i915_reg.h                      |  4 ++++
 5 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b346b946602d..2f719f0ecac3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 		engine->props.preempt_timeout_ms = 0;
 
 	/* features common between engines sharing EUs */
-	if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+	if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
 		engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+		engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
+	}
 
 	engine->defaults = engine->props; /* never to change again */
 
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 30a0c69c36c8..00bf0296b28a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -455,6 +455,7 @@ struct intel_engine_cs {
 #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
 #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
 #define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
+#define I915_ENGINE_HAS_EU_PRIORITY    BIT(10)
 	unsigned int flags;
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4c600c46414d..2b36ec7f3a04 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct i915_request *rq)
 static u64 execlists_update_context(struct i915_request *rq)
 {
 	struct intel_context *ce = rq->context;
-	u64 desc = ce->lrc.desc;
+	u64 desc;
 	u32 tail, prev;
 
+	desc = ce->lrc.desc;
+	if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+		desc |= lrc_desc_priority(rq_prio(rq));
+
 	/*
 	 * WaIdleLiteRestore:bdw,skl
 	 *
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 7f697845c4cf..d3f2096b3d51 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context *ce)
 	return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
 }
 
+static inline u32 lrc_desc_priority(int prio)
+{
+	if (prio > I915_PRIORITY_NORMAL)
+		return GEN12_CTX_PRIORITY_HIGH;
+	else if (prio < I915_PRIORITY_NORMAL)
+		return GEN12_CTX_PRIORITY_LOW;
+	else
+		return GEN12_CTX_PRIORITY_NORMAL;
+}
+
 #endif /* __INTEL_LRC_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bb185ce9529..5b68c02c35af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,10 @@ enum {
 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
 #define GEN8_CTX_PRIVILEGE (1 << 8)
 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9)
+#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
+#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
+#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
 
 #define GEN8_CTX_ID_SHIFT 32
 #define GEN8_CTX_ID_WIDTH 21
-- 
2.25.4


  parent reply	other threads:[~2021-09-07 17:19 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-07 17:19 [PATCH 0/8] i915: Introduce Xe_HP compute engines Matt Roper
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
2021-09-07 17:19 ` [PATCH 1/8] drm/i915/xehp: Define compute class and engine Matt Roper
2021-09-07 17:19   ` [Intel-gfx] " Matt Roper
2021-09-08  9:46   ` Tvrtko Ursulin
2021-09-08  9:46     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-08 16:42   ` Daniel Vetter
2021-09-07 17:19 ` [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain Matt Roper
2021-09-07 17:19   ` [Intel-gfx] " Matt Roper
2021-09-08 10:07   ` Tvrtko Ursulin
2021-09-08 10:07     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-08 20:23     ` Matt Roper
2021-09-08 20:23       ` [Intel-gfx] " Matt Roper
2021-09-09  8:11       ` Tvrtko Ursulin
2021-09-09  8:11         ` [Intel-gfx] " Tvrtko Ursulin
2021-09-08 16:46   ` Daniel Vetter
2021-09-07 17:19 ` [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers Matt Roper
2021-09-07 17:19   ` [Intel-gfx] " Matt Roper
2021-09-08 10:09   ` Tvrtko Ursulin
2021-09-08 10:09     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-07 17:19 ` [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions Matt Roper
2021-09-07 17:19   ` [Intel-gfx] " Matt Roper
2021-09-08 10:13   ` Tvrtko Ursulin
2021-09-08 10:13     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-08 13:57     ` Tvrtko Ursulin
2021-09-08 13:57       ` [Intel-gfx] " Tvrtko Ursulin
2021-09-07 17:19 ` [PATCH 5/8] drm/i915/xehp: compute engine pipe_control Matt Roper
2021-09-07 17:19   ` [Intel-gfx] " Matt Roper
2021-09-07 17:19 ` Matt Roper [this message]
2021-09-07 17:19   ` [Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Matt Roper
2021-09-08 14:01   ` Tvrtko Ursulin
2021-09-08 14:01     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-07 17:19 ` [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Matt Roper
2021-09-07 17:19   ` [Intel-gfx] " Matt Roper
2021-09-08 14:10   ` Tvrtko Ursulin
2021-09-08 14:10     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-07 17:19 ` [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS Matt Roper
2021-09-07 17:19   ` [Intel-gfx] " Matt Roper
2021-09-08 14:15   ` Tvrtko Ursulin
2021-09-07 20:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Xe_HP compute engines Patchwork
2021-09-07 20:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-07 20:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-08  0:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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