From: Matt Roper <matthew.d.roper@intel.com> To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Vinay Belgaumkar <vinay.belgaumkar@intel.com>, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Aravind Iddamsetty <aravind.iddamsetty@intel.com> Subject: Re: [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain Date: Wed, 8 Sep 2021 13:23:19 -0700 [thread overview] Message-ID: <20210908202319.GQ461228@mdroper-desk1.amr.corp.intel.com> (raw) In-Reply-To: <4ce6bdc9-82c6-e281-400d-ce658d6ba80b@linux.intel.com> On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote: > > On 07/09/2021 18:19, Matt Roper wrote: > > The reset domain is shared between render and all compute engines, > > so resetting one will affect the others. > > > > Note: Before performing a reset on an RCS or CCS engine, the GuC will > > attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid > > impacting other clients (since some shared modules will be reset). If > > other engines are executing non-preemptable workloads, the impact is > > unavoidable and some work may be lost. > > Since here it talks about engine reset, should this patch add warning if > same is attempted by i915 on a GuC platform - to document it is not Did you mean "on a *non* GuC platform" here? We aren't going to have compute engine support on any platforms where GuC submission isn't the default operating model, so the only way to get compute engines + execlist submission is to force an override via module parameters (e.g., enable_guc=0). Doing so will taint the kernel, so I think the current consensus from offline discussion is that the user has already put themselves into a configuration where it's easier than usual to shoot themselves in the foot; it's not too much different than the kind of trouble a user could get themselves into if they loaded the driver with hangcheck disabled or something. Matt > implemented/supported? Or perhaps later in the series, or future series > works better. > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Regards, > > Tvrtko > > > Bspec: 52549 > > Original-patch-by: Michel Thierry > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c > > index 91200c43951f..30598c1d070c 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > > @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt, > > [VECS1] = GEN11_GRDOM_VECS2, > > [VECS2] = GEN11_GRDOM_VECS3, > > [VECS3] = GEN11_GRDOM_VECS4, > > + [CCS0] = GEN11_GRDOM_RENDER, > > + [CCS1] = GEN11_GRDOM_RENDER, > > + [CCS2] = GEN11_GRDOM_RENDER, > > + [CCS3] = GEN11_GRDOM_RENDER, > > }; > > struct intel_engine_cs *engine; > > intel_engine_mask_t tmp; > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Vinay Belgaumkar <vinay.belgaumkar@intel.com>, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Aravind Iddamsetty <aravind.iddamsetty@intel.com> Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain Date: Wed, 8 Sep 2021 13:23:19 -0700 [thread overview] Message-ID: <20210908202319.GQ461228@mdroper-desk1.amr.corp.intel.com> (raw) In-Reply-To: <4ce6bdc9-82c6-e281-400d-ce658d6ba80b@linux.intel.com> On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote: > > On 07/09/2021 18:19, Matt Roper wrote: > > The reset domain is shared between render and all compute engines, > > so resetting one will affect the others. > > > > Note: Before performing a reset on an RCS or CCS engine, the GuC will > > attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid > > impacting other clients (since some shared modules will be reset). If > > other engines are executing non-preemptable workloads, the impact is > > unavoidable and some work may be lost. > > Since here it talks about engine reset, should this patch add warning if > same is attempted by i915 on a GuC platform - to document it is not Did you mean "on a *non* GuC platform" here? We aren't going to have compute engine support on any platforms where GuC submission isn't the default operating model, so the only way to get compute engines + execlist submission is to force an override via module parameters (e.g., enable_guc=0). Doing so will taint the kernel, so I think the current consensus from offline discussion is that the user has already put themselves into a configuration where it's easier than usual to shoot themselves in the foot; it's not too much different than the kind of trouble a user could get themselves into if they loaded the driver with hangcheck disabled or something. Matt > implemented/supported? Or perhaps later in the series, or future series > works better. > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Regards, > > Tvrtko > > > Bspec: 52549 > > Original-patch-by: Michel Thierry > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c > > index 91200c43951f..30598c1d070c 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > > @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt, > > [VECS1] = GEN11_GRDOM_VECS2, > > [VECS2] = GEN11_GRDOM_VECS3, > > [VECS3] = GEN11_GRDOM_VECS4, > > + [CCS0] = GEN11_GRDOM_RENDER, > > + [CCS1] = GEN11_GRDOM_RENDER, > > + [CCS2] = GEN11_GRDOM_RENDER, > > + [CCS3] = GEN11_GRDOM_RENDER, > > }; > > struct intel_engine_cs *engine; > > intel_engine_mask_t tmp; > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
next prev parent reply other threads:[~2021-09-08 20:23 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-07 17:19 [PATCH 0/8] i915: Introduce Xe_HP compute engines Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-07 17:19 ` [PATCH 1/8] drm/i915/xehp: Define compute class and engine Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-08 9:46 ` Tvrtko Ursulin 2021-09-08 9:46 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-08 16:42 ` Daniel Vetter 2021-09-07 17:19 ` [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-08 10:07 ` Tvrtko Ursulin 2021-09-08 10:07 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-08 20:23 ` Matt Roper [this message] 2021-09-08 20:23 ` Matt Roper 2021-09-09 8:11 ` Tvrtko Ursulin 2021-09-09 8:11 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-08 16:46 ` Daniel Vetter 2021-09-07 17:19 ` [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-08 10:09 ` Tvrtko Ursulin 2021-09-08 10:09 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-07 17:19 ` [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-08 10:13 ` Tvrtko Ursulin 2021-09-08 10:13 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-08 13:57 ` Tvrtko Ursulin 2021-09-08 13:57 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-07 17:19 ` [PATCH 5/8] drm/i915/xehp: compute engine pipe_control Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-07 17:19 ` [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-08 14:01 ` Tvrtko Ursulin 2021-09-08 14:01 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-07 17:19 ` [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-08 14:10 ` Tvrtko Ursulin 2021-09-08 14:10 ` [Intel-gfx] " Tvrtko Ursulin 2021-09-07 17:19 ` [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS Matt Roper 2021-09-07 17:19 ` [Intel-gfx] " Matt Roper 2021-09-08 14:15 ` Tvrtko Ursulin 2021-09-07 20:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Xe_HP compute engines Patchwork 2021-09-07 20:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-09-07 20:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-08 0:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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