* [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
@ 2021-09-08 9:18 Ryan Chen
2021-09-13 5:26 ` Claudiu.Beznea
0 siblings, 1 reply; 7+ messages in thread
From: Ryan Chen @ 2021-09-08 9:18 UTC (permalink / raw)
To: ryan_chen, Michael Turquette, Stephen Boyd, Joel Stanley,
Andrew Jeffery, linux-clk, linux-kernel
AST2600 HPLL calculate formula [SCU200]
HPLL Numerator(M): have fixed value depend on SCU strap.
M = SCU500[10] ? 0x5F : SCU500[8] ? 0xBF : SCU200[12:0]
if SCU500[10] = 1, M=0x5F.
else if SCU500[10]=0 & SCU500[8]=1, M=0xBF.
others (SCU510[10]=0 and SCU510[8]=0)
depend on SCU200[12:0] (default 0x8F) register setting.
HPLL Denumerator (N) = SCU200[18:13] (default 0x2)
HPLL Divider (P) = SCU200[22:19] (default 0x0)
Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
drivers/clk/clk-ast2600.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index 085d0a18b2b6..5d8c46bcf237 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -169,6 +169,33 @@ static const struct clk_div_table ast2600_div_table[] = {
};
/* For hpll/dpll/epll/mpll */
+static struct clk_hw *ast2600_calc_hpll(const char *name, u32 val)
+{
+ unsigned int mult, div;
+ u32 hwstrap = readl(scu_g6_base + ASPEED_G6_STRAP1);
+
+ if (val & BIT(24)) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
+ u32 m = val & 0x1fff;
+ u32 n = (val >> 13) & 0x3f;
+ u32 p = (val >> 19) & 0xf;
+
+ if (hwstrap & BIT(10))
+ m = 0x5F;
+ else {
+ if (hwstrap & BIT(8))
+ m = 0xBF;
+ }
+ mult = (m + 1) / (n + 1);
+ div = (p + 1);
+ }
+ return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+ mult, div);
+};
+
static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
{
unsigned int mult, div;
@@ -716,7 +743,7 @@ static void __init aspeed_g6_cc(struct regmap *map)
* and we assume that it is enabled
*/
regmap_read(map, ASPEED_HPLL_PARAM, &val);
- aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_hpll("hpll", val);
regmap_read(map, ASPEED_MPLL_PARAM, &val);
aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
2021-09-08 9:18 [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula Ryan Chen
@ 2021-09-13 5:26 ` Claudiu.Beznea
2021-09-13 5:31 ` Ryan Chen
0 siblings, 1 reply; 7+ messages in thread
From: Claudiu.Beznea @ 2021-09-13 5:26 UTC (permalink / raw)
To: ryan_chen, mturquette, sboyd, joel, andrew, linux-clk, linux-kernel
On 08.09.2021 12:18, Ryan Chen wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> AST2600 HPLL calculate formula [SCU200]
> HPLL Numerator(M): have fixed value depend on SCU strap.
> M = SCU500[10] ? 0x5F : SCU500[8] ? 0xBF : SCU200[12:0]
>
> if SCU500[10] = 1, M=0x5F.
> else if SCU500[10]=0 & SCU500[8]=1, M=0xBF.
> others (SCU510[10]=0 and SCU510[8]=0)
> depend on SCU200[12:0] (default 0x8F) register setting.
>
> HPLL Denumerator (N) = SCU200[18:13] (default 0x2)
> HPLL Divider (P) = SCU200[22:19] (default 0x0)
>
> Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
> drivers/clk/clk-ast2600.c | 29 ++++++++++++++++++++++++++++-
> 1 file changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
> index 085d0a18b2b6..5d8c46bcf237 100644
> --- a/drivers/clk/clk-ast2600.c
> +++ b/drivers/clk/clk-ast2600.c
> @@ -169,6 +169,33 @@ static const struct clk_div_table ast2600_div_table[] = {
> };
>
> /* For hpll/dpll/epll/mpll */
> +static struct clk_hw *ast2600_calc_hpll(const char *name, u32 val)
> +{
> + unsigned int mult, div;
> + u32 hwstrap = readl(scu_g6_base + ASPEED_G6_STRAP1);
> +
> + if (val & BIT(24)) {
> + /* Pass through mode */
> + mult = div = 1;
> + } else {
> + /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
> + u32 m = val & 0x1fff;
> + u32 n = (val >> 13) & 0x3f;
> + u32 p = (val >> 19) & 0xf;
> +
> + if (hwstrap & BIT(10))
> + m = 0x5F;
> + else {
> + if (hwstrap & BIT(8))
You may write it directly:
else if (hwstrap & BIT(8))
> + m = 0xBF;
> + }
> + mult = (m + 1) / (n + 1);
> + div = (p + 1);
> + }
> + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
> + mult, div);
> +};
> +
> static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
> {
> unsigned int mult, div;
> @@ -716,7 +743,7 @@ static void __init aspeed_g6_cc(struct regmap *map)
> * and we assume that it is enabled
> */
> regmap_read(map, ASPEED_HPLL_PARAM, &val);
> - aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_hpll("hpll", val);
>
> regmap_read(map, ASPEED_MPLL_PARAM, &val);
> aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
2021-09-13 5:26 ` Claudiu.Beznea
@ 2021-09-13 5:31 ` Ryan Chen
2021-09-15 1:17 ` Stephen Boyd
0 siblings, 1 reply; 7+ messages in thread
From: Ryan Chen @ 2021-09-13 5:31 UTC (permalink / raw)
To: Claudiu.Beznea, mturquette, sboyd, joel, andrew, linux-clk, linux-kernel
> -----Original Message-----
> From: Claudiu.Beznea@microchip.com <Claudiu.Beznea@microchip.com>
> Sent: Monday, September 13, 2021 1:26 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; mturquette@baylibre.com;
> sboyd@kernel.org; joel@jms.id.au; andrew@aj.id.au; linux-clk@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
>
> On 08.09.2021 12:18, Ryan Chen wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> > the content is safe
> >
> > AST2600 HPLL calculate formula [SCU200] HPLL Numerator(M): have fixed
> > value depend on SCU strap.
> > M = SCU500[10] ? 0x5F : SCU500[8] ? 0xBF : SCU200[12:0]
> >
> > if SCU500[10] = 1, M=0x5F.
> > else if SCU500[10]=0 & SCU500[8]=1, M=0xBF.
> > others (SCU510[10]=0 and SCU510[8]=0)
> > depend on SCU200[12:0] (default 0x8F) register setting.
> >
> > HPLL Denumerator (N) = SCU200[18:13] (default 0x2)
> > HPLL Divider (P) = SCU200[22:19] (default 0x0)
> >
> > Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> > drivers/clk/clk-ast2600.c | 29 ++++++++++++++++++++++++++++-
> > 1 file changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
> > index 085d0a18b2b6..5d8c46bcf237 100644
> > --- a/drivers/clk/clk-ast2600.c
> > +++ b/drivers/clk/clk-ast2600.c
> > @@ -169,6 +169,33 @@ static const struct clk_div_table
> > ast2600_div_table[] = { };
> >
> > /* For hpll/dpll/epll/mpll */
> > +static struct clk_hw *ast2600_calc_hpll(const char *name, u32 val) {
> > + unsigned int mult, div;
> > + u32 hwstrap = readl(scu_g6_base + ASPEED_G6_STRAP1);
> > +
> > + if (val & BIT(24)) {
> > + /* Pass through mode */
> > + mult = div = 1;
> > + } else {
> > + /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
> > + u32 m = val & 0x1fff;
> > + u32 n = (val >> 13) & 0x3f;
> > + u32 p = (val >> 19) & 0xf;
> > +
> > + if (hwstrap & BIT(10))
> > + m = 0x5F;
> > + else {
> > + if (hwstrap & BIT(8))
>
> You may write it directly:
> else if (hwstrap & BIT(8))
>
Hello,
Like I commit message M = SCU500[10] ? 0x5F : SCU500[8] ? 0xBF : SCU200[12:0]
it need keep from register read, if BIT(8)/BIT(10) not 1.
> > + m = 0xBF;
> > + }
> > + mult = (m + 1) / (n + 1);
> > + div = (p + 1);
> > + }
> > + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
> > + mult, div);
> > +};
> > +
> > static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) {
> > unsigned int mult, div;
> > @@ -716,7 +743,7 @@ static void __init aspeed_g6_cc(struct regmap
> *map)
> > * and we assume that it is enabled
> > */
> > regmap_read(map, ASPEED_HPLL_PARAM, &val);
> > - aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] =
> ast2600_calc_pll("hpll", val);
> > + aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] =
> > + ast2600_calc_hpll("hpll", val);
> >
> > regmap_read(map, ASPEED_MPLL_PARAM, &val);
> > aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] =
> > ast2600_calc_pll("mpll", val);
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
2021-09-13 5:31 ` Ryan Chen
@ 2021-09-15 1:17 ` Stephen Boyd
2021-09-15 2:52 ` Ryan Chen
0 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2021-09-15 1:17 UTC (permalink / raw)
To: Claudiu.Beznea, Ryan Chen, andrew, joel, linux-clk, linux-kernel,
mturquette
Quoting Ryan Chen (2021-09-12 22:31:46)
> > > + if (hwstrap & BIT(10))
> > > + m = 0x5F;
> > > + else {
> > > + if (hwstrap & BIT(8))
> >
> > You may write it directly:
> > else if (hwstrap & BIT(8))
> >
> Hello,
> Like I commit message M = SCU500[10] ? 0x5F : SCU500[8] ? 0xBF : SCU200[12:0]
> it need keep from register read, if BIT(8)/BIT(10) not 1.
>
I don't get it. The review comment was that the else { if (...) can be
collapsed into an else if (..) What does commit message have to do with
it?
^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
2021-09-15 1:17 ` Stephen Boyd
@ 2021-09-15 2:52 ` Ryan Chen
2021-09-15 3:07 ` Joel Stanley
0 siblings, 1 reply; 7+ messages in thread
From: Ryan Chen @ 2021-09-15 2:52 UTC (permalink / raw)
To: Stephen Boyd, Claudiu.Beznea, andrew, joel, linux-clk,
linux-kernel, mturquette
> -----Original Message-----
> From: Stephen Boyd <sboyd@kernel.org>
> Sent: Wednesday, September 15, 2021 9:17 AM
> To: Claudiu.Beznea@microchip.com; Ryan Chen
> <ryan_chen@aspeedtech.com>; andrew@aj.id.au; joel@jms.id.au;
> linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org;
> mturquette@baylibre.com
> Subject: RE: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
>
> Quoting Ryan Chen (2021-09-12 22:31:46)
> > > > + if (hwstrap & BIT(10))
> > > > + m = 0x5F;
> > > > + else {
> > > > + if (hwstrap & BIT(8))
> > >
> > > You may write it directly:
> > > else if (hwstrap & BIT(8))
> > >
> > Hello,
> > Like I commit message M = SCU500[10] ? 0x5F : SCU500[8] ? 0xBF :
> SCU200[12:0]
> > it need keep from register read, if BIT(8)/BIT(10) not 1.
> >
>
> I don't get it. The review comment was that the else { if (...) can be collapsed
> into an else if (..) What does commit message have to do with it?
Sorry for confuse.
Or do you mean like following modification?
if (hwstrap & BIT(10))
m = 0x5F;
else if (hwstrap & BIT(8))
m = 0xBF;
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
2021-09-15 2:52 ` Ryan Chen
@ 2021-09-15 3:07 ` Joel Stanley
2021-09-15 3:11 ` Ryan Chen
0 siblings, 1 reply; 7+ messages in thread
From: Joel Stanley @ 2021-09-15 3:07 UTC (permalink / raw)
To: Ryan Chen
Cc: Stephen Boyd, Claudiu.Beznea, andrew, linux-clk, linux-kernel,
mturquette
On Wed, 15 Sept 2021 at 02:52, Ryan Chen <ryan_chen@aspeedtech.com> wrote:
>
> > -----Original Message-----
> > From: Stephen Boyd <sboyd@kernel.org>
> > Sent: Wednesday, September 15, 2021 9:17 AM
> > To: Claudiu.Beznea@microchip.com; Ryan Chen
> > <ryan_chen@aspeedtech.com>; andrew@aj.id.au; joel@jms.id.au;
> > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org;
> > mturquette@baylibre.com
> > Subject: RE: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
> >
> > Quoting Ryan Chen (2021-09-12 22:31:46)
> > > > > + if (hwstrap & BIT(10))
> > > > > + m = 0x5F;
> > > > > + else {
> > > > > + if (hwstrap & BIT(8))
> > > >
> > > > You may write it directly:
> > > > else if (hwstrap & BIT(8))
> > > >
> > > Hello,
> > > Like I commit message M = SCU500[10] ? 0x5F : SCU500[8] ? 0xBF :
> > SCU200[12:0]
> > > it need keep from register read, if BIT(8)/BIT(10) not 1.
> > >
> >
> > I don't get it. The review comment was that the else { if (...) can be collapsed
> > into an else if (..) What does commit message have to do with it?
> Sorry for confuse.
> Or do you mean like following modification?
>
> if (hwstrap & BIT(10))
> m = 0x5F;
> else if (hwstrap & BIT(8))
> m = 0xBF;
Yep!
Take a look at my review of v1. I wrote it out there.
^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
2021-09-15 3:07 ` Joel Stanley
@ 2021-09-15 3:11 ` Ryan Chen
0 siblings, 0 replies; 7+ messages in thread
From: Ryan Chen @ 2021-09-15 3:11 UTC (permalink / raw)
To: Joel Stanley
Cc: Stephen Boyd, Claudiu.Beznea, andrew, linux-clk, linux-kernel,
mturquette
> -----Original Message-----
> From: Joel Stanley <joel@jms.id.au>
> Sent: Wednesday, September 15, 2021 11:07 AM
> To: Ryan Chen <ryan_chen@aspeedtech.com>
> Cc: Stephen Boyd <sboyd@kernel.org>; Claudiu.Beznea@microchip.com;
> andrew@aj.id.au; linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org;
> mturquette@baylibre.com
> Subject: Re: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
>
> On Wed, 15 Sept 2021 at 02:52, Ryan Chen <ryan_chen@aspeedtech.com>
> wrote:
> >
> > > -----Original Message-----
> > > From: Stephen Boyd <sboyd@kernel.org>
> > > Sent: Wednesday, September 15, 2021 9:17 AM
> > > To: Claudiu.Beznea@microchip.com; Ryan Chen
> > > <ryan_chen@aspeedtech.com>; andrew@aj.id.au; joel@jms.id.au;
> > > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > mturquette@baylibre.com
> > > Subject: RE: [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula
> > >
> > > Quoting Ryan Chen (2021-09-12 22:31:46)
> > > > > > + if (hwstrap & BIT(10))
> > > > > > + m = 0x5F;
> > > > > > + else {
> > > > > > + if (hwstrap & BIT(8))
> > > > >
> > > > > You may write it directly:
> > > > > else if (hwstrap & BIT(8))
> > > > >
> > > > Hello,
> > > > Like I commit message M = SCU500[10] ? 0x5F : SCU500[8] ?
> 0xBF :
> > > SCU200[12:0]
> > > > it need keep from register read, if BIT(8)/BIT(10) not 1.
> > > >
> > >
> > > I don't get it. The review comment was that the else { if (...) can
> > > be collapsed into an else if (..) What does commit message have to do with
> it?
> > Sorry for confuse.
> > Or do you mean like following modification?
> >
> > if (hwstrap & BIT(10))
> > m = 0x5F;
> > else if (hwstrap & BIT(8))
> > m = 0xBF;
>
> Yep!
>
> Take a look at my review of v1. I wrote it out there.
Got it will modify by this.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-09-15 3:11 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2021-09-08 9:18 [PATCHv2] clk:aspeed:Fix AST2600 hpll calculate formula Ryan Chen
2021-09-13 5:26 ` Claudiu.Beznea
2021-09-13 5:31 ` Ryan Chen
2021-09-15 1:17 ` Stephen Boyd
2021-09-15 2:52 ` Ryan Chen
2021-09-15 3:07 ` Joel Stanley
2021-09-15 3:11 ` Ryan Chen
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