From: Eric Tang <tangxingxin1008@gmail.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com Subject: [RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions Date: Sat, 18 Sep 2021 14:28:07 +0800 [thread overview] Message-ID: <20210918062816.7546-2-tangxingxin1008@gmail.com> (raw) In-Reply-To: <20210918062816.7546-1-tangxingxin1008@gmail.com> According to spec, these instructions ignore the upper 32 bit of their input and sign-extend their 32 bit output values. Fixed the output's error when their input values greater than 0xffffffff. Signed-off-by: Eric Tang <tangxingxin1008@gmail.com> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b72e76255c..96b6fcb41d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -484,12 +484,32 @@ static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); } +static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_not_i32(t1, t1); + tcg_gen_shr_i32(t1, t1, t2); + tcg_gen_not_i32(t1, t1); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_srow(DisasContext *ctx, arg_srow *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); ctx->w = true; - return gen_shift(ctx, a, EXT_ZERO, gen_sro); + return gen_shift(ctx, a, EXT_ZERO, gen_srow); } static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) @@ -497,7 +517,7 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_srow); } static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Eric Tang <tangxingxin1008@gmail.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com Subject: [RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions Date: Sat, 18 Sep 2021 14:28:07 +0800 [thread overview] Message-ID: <20210918062816.7546-2-tangxingxin1008@gmail.com> (raw) In-Reply-To: <20210918062816.7546-1-tangxingxin1008@gmail.com> According to spec, these instructions ignore the upper 32 bit of their input and sign-extend their 32 bit output values. Fixed the output's error when their input values greater than 0xffffffff. Signed-off-by: Eric Tang <tangxingxin1008@gmail.com> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b72e76255c..96b6fcb41d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -484,12 +484,32 @@ static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); } +static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_not_i32(t1, t1); + tcg_gen_shr_i32(t1, t1, t2); + tcg_gen_not_i32(t1, t1); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_srow(DisasContext *ctx, arg_srow *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); ctx->w = true; - return gen_shift(ctx, a, EXT_ZERO, gen_sro); + return gen_shift(ctx, a, EXT_ZERO, gen_srow); } static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) @@ -497,7 +517,7 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_srow); } static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -- 2.17.1
next prev parent reply other threads:[~2021-09-18 8:23 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-18 6:28 [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` Eric Tang [this message] 2021-09-18 6:28 ` [RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions Eric Tang 2021-09-18 6:28 ` [RFC 02/10] target/riscv: rvb: add carry-less multiply instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 03/10] target/riscv: rvb: add cmix/cmov instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 04/10] target/riscv: rvb: add generalized shuffle instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 05/10] target/riscv: rvb: add crossbar permutation instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 06/10] target/riscv: rvb: add bfp/bfpw instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 07/10] target/riscv: rvb: add CRC instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 08/10] target/riscv: rvb: add bit-matrix instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-18 6:28 ` [RFC 10/10] target/riscv: rvb: add funnel shfit instructions Eric Tang 2021-09-18 6:28 ` Eric Tang 2021-09-24 4:39 ` [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions Alistair Francis 2021-09-24 4:39 ` Alistair Francis 2021-09-24 5:48 ` eric tang 2021-09-24 5:48 ` eric tang
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