[RFC 07/10] target/riscv: rvb: add CRC instructions

[Eric Tang <tangxingxin1008@gmail.com>]

Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 35f7b0926b..469145ffa9 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -272,3 +272,58 @@ target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2)
 {
     return do_bfp(rs1, rs2, 32);
 }
+
+#define DO_CRC(NAME, VALUE)                                  \
+static target_ulong do_##NAME(target_ulong rs1,              \
+                              int nbits)                     \
+{                                                            \
+    int i;                                                   \
+    target_ulong x = rs1;                                    \
+    for (i = 0; i < nbits; i++) {                            \
+        x = (x >> 1) ^ ((VALUE) & ~((x & 1) - 1));           \
+    }                                                        \
+    return x;                                                \
+}
+
+DO_CRC(crc32, 0xEDB88320)
+DO_CRC(crc32c, 0x82F63B78)
+
+target_ulong HELPER(crc32_b)(target_ulong rs1)
+{
+    return do_crc32(rs1, 8);
+}
+
+target_ulong HELPER(crc32_h)(target_ulong rs1)
+{
+    return do_crc32(rs1, 16);
+}
+
+target_ulong HELPER(crc32_w)(target_ulong rs1)
+{
+    return do_crc32(rs1, 32);
+}
+
+target_ulong HELPER(crc32_d)(target_ulong rs1)
+{
+    return do_crc32(rs1, 64);
+}
+
+target_ulong HELPER(crc32c_b)(target_ulong rs1)
+{
+    return do_crc32c(rs1, 8);
+}
+
+target_ulong HELPER(crc32c_h)(target_ulong rs1)
+{
+    return do_crc32c(rs1, 16);
+}
+
+target_ulong HELPER(crc32c_w)(target_ulong rs1)
+{
+    return do_crc32c(rs1, 32);
+}
+
+target_ulong HELPER(crc32c_d)(target_ulong rs1)
+{
+    return do_crc32c(rs1, 64);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 474b1add63..9654d6f7a7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,6 +76,14 @@ DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_b, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_h, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_w, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_d, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_b, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_h, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_w, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5d354f63a2..b08e38823b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -670,6 +670,14 @@ ctz        011000 000001 ..... 001 ..... 0010011 @r2
 cpop       011000 000010 ..... 001 ..... 0010011 @r2
 sext_b     011000 000100 ..... 001 ..... 0010011 @r2
 sext_h     011000 000101 ..... 001 ..... 0010011 @r2
+crc32_b    0110000 10000 ..... 001 ..... 0010011 @r2
+crc32_h    0110000 10001 ..... 001 ..... 0010011 @r2
+crc32_w    0110000 10010 ..... 001 ..... 0010011 @r2
+crc32_d    0110000 10011 ..... 001 ..... 0010011 @r2
+crc32c_b   0110000 11000 ..... 001 ..... 0010011 @r2
+crc32c_h   0110000 11001 ..... 001 ..... 0010011 @r2
+crc32c_w   0110000 11010 ..... 001 ..... 0010011 @r2
+crc32c_d   0110000 11011 ..... 001 ..... 0010011 @r2
 
 andn       0100000 .......... 111 ..... 0110011 @r
 orn        0100000 .......... 110 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 1997d33008..0d734bfd10 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -386,6 +386,22 @@ GEN_TRANS_CLMUL(clmul)
 GEN_TRANS_CLMUL(clmulh)
 GEN_TRANS_CLMUL(clmulr)
 
+#define GEN_TRANS_CRC(NAME)                                 \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
+{                                                           \
+    REQUIRE_EXT(ctx, RVB);                                  \
+    return gen_unary(ctx, a, EXT_NONE, gen_helper_##NAME);  \
+}                                                           \
+
+GEN_TRANS_CRC(crc32_b)
+GEN_TRANS_CRC(crc32_h)
+GEN_TRANS_CRC(crc32_w)
+GEN_TRANS_CRC(crc32_d)
+GEN_TRANS_CRC(crc32c_b)
+GEN_TRANS_CRC(crc32c_h)
+GEN_TRANS_CRC(crc32c_w)
+GEN_TRANS_CRC(crc32c_d)
+
 static void gen_cmix(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
 {
     tcg_gen_and_tl(arg1, arg1, arg2);
-- 
2.17.1