From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, anshuman.khandual@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Date: Tue, 21 Sep 2021 14:41:09 +0100 [thread overview] Message-ID: <20210921134121.2423546-6-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210921134121.2423546-1-suzuki.poulose@arm.com> We always set the TRBBASER_EL1 to the base of the virtual ring buffer. We are about to change this for working around an erratum. So, in preparation to that, allow the driver to choose a different base for the TRBBASER_EL1 (which is within the buffer range). Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index a32ef083aa36..27616eac24ba 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -59,6 +59,8 @@ struct trbe_buf { * trbe_limit sibling pointers. */ unsigned long trbe_base; + /* The base programmed into the TRBE */ + unsigned long trbe_hw_base; unsigned long trbe_limit; unsigned long trbe_write; int nr_pages; @@ -498,12 +500,13 @@ static void set_trbe_limit_pointer_enabled(unsigned long addr) static void trbe_enable_hw(struct trbe_buf *buf) { - WARN_ON(buf->trbe_write < buf->trbe_base); + WARN_ON(buf->trbe_hw_base < buf->trbe_base); + WARN_ON(buf->trbe_write < buf->trbe_hw_base); WARN_ON(buf->trbe_write >= buf->trbe_limit); set_trbe_disabled(); isb(); clr_trbe_status(); - set_trbe_base_pointer(buf->trbe_base); + set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); /* @@ -707,6 +710,8 @@ static int __arm_trbe_enable(struct trbe_buf *buf, trbe_stop_and_truncate_event(handle); return -ENOSPC; } + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base = buf->trbe_base; *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle; trbe_enable_hw(buf); return 0; @@ -804,7 +809,7 @@ static bool is_perf_trbe(struct perf_output_handle *handle) struct trbe_drvdata *drvdata = cpudata->drvdata; int cpu = smp_processor_id(); - WARN_ON(buf->trbe_base != get_trbe_base_pointer()); + WARN_ON(buf->trbe_hw_base != get_trbe_base_pointer()); WARN_ON(buf->trbe_limit != get_trbe_limit_pointer()); if (cpudata->mode != CS_MODE_PERF) -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, anshuman.khandual@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Date: Tue, 21 Sep 2021 14:41:09 +0100 [thread overview] Message-ID: <20210921134121.2423546-6-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210921134121.2423546-1-suzuki.poulose@arm.com> We always set the TRBBASER_EL1 to the base of the virtual ring buffer. We are about to change this for working around an erratum. So, in preparation to that, allow the driver to choose a different base for the TRBBASER_EL1 (which is within the buffer range). Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index a32ef083aa36..27616eac24ba 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -59,6 +59,8 @@ struct trbe_buf { * trbe_limit sibling pointers. */ unsigned long trbe_base; + /* The base programmed into the TRBE */ + unsigned long trbe_hw_base; unsigned long trbe_limit; unsigned long trbe_write; int nr_pages; @@ -498,12 +500,13 @@ static void set_trbe_limit_pointer_enabled(unsigned long addr) static void trbe_enable_hw(struct trbe_buf *buf) { - WARN_ON(buf->trbe_write < buf->trbe_base); + WARN_ON(buf->trbe_hw_base < buf->trbe_base); + WARN_ON(buf->trbe_write < buf->trbe_hw_base); WARN_ON(buf->trbe_write >= buf->trbe_limit); set_trbe_disabled(); isb(); clr_trbe_status(); - set_trbe_base_pointer(buf->trbe_base); + set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); /* @@ -707,6 +710,8 @@ static int __arm_trbe_enable(struct trbe_buf *buf, trbe_stop_and_truncate_event(handle); return -ENOSPC; } + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base = buf->trbe_base; *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle; trbe_enable_hw(buf); return 0; @@ -804,7 +809,7 @@ static bool is_perf_trbe(struct perf_output_handle *handle) struct trbe_drvdata *drvdata = cpudata->drvdata; int cpu = smp_processor_id(); - WARN_ON(buf->trbe_base != get_trbe_base_pointer()); + WARN_ON(buf->trbe_hw_base != get_trbe_base_pointer()); WARN_ON(buf->trbe_limit != get_trbe_limit_pointer()); if (cpudata->mode != CS_MODE_PERF) -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-09-21 13:41 UTC|newest] Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-21 13:41 [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 01/17] coresight: trbe: Fix incorrect access of the sink specific data Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 5:41 ` Anshuman Khandual 2021-09-22 5:41 ` Anshuman Khandual 2021-09-30 17:57 ` Mathieu Poirier 2021-09-30 17:57 ` Mathieu Poirier 2021-09-21 13:41 ` [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 6:47 ` Anshuman Khandual 2021-09-22 6:47 ` Anshuman Khandual 2021-10-05 16:46 ` Mathieu Poirier 2021-10-05 16:46 ` Mathieu Poirier 2021-09-21 13:41 ` [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-30 17:54 ` Mathieu Poirier 2021-09-30 17:54 ` Mathieu Poirier 2021-10-01 8:36 ` Suzuki K Poulose 2021-10-01 8:36 ` Suzuki K Poulose 2021-10-01 15:15 ` Mathieu Poirier 2021-10-01 15:15 ` Mathieu Poirier 2021-10-01 15:22 ` Suzuki K Poulose 2021-10-01 15:22 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 04/17] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose [this message] 2021-09-21 13:41 ` [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 6:57 ` Anshuman Khandual 2021-09-22 6:57 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 08/17] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 09/17] coresight: trbe: Workaround TRBE errata " Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-23 6:13 ` Anshuman Khandual 2021-09-23 6:13 ` Anshuman Khandual 2021-09-28 10:40 ` Suzuki K Poulose 2021-09-28 10:40 ` Suzuki K Poulose 2021-10-01 4:21 ` Anshuman Khandual 2021-10-01 4:21 ` Anshuman Khandual 2021-10-01 17:15 ` Mathieu Poirier 2021-10-01 17:15 ` Mathieu Poirier 2021-10-04 8:46 ` Suzuki K Poulose 2021-10-04 8:46 ` Suzuki K Poulose 2021-10-04 16:47 ` Mathieu Poirier 2021-10-04 16:47 ` Mathieu Poirier 2021-09-21 13:41 ` [PATCH v2 10/17] arm64: Enable workaround for TRBE " Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 7:23 ` Anshuman Khandual 2021-09-22 7:23 ` Anshuman Khandual 2021-09-22 8:11 ` Suzuki K Poulose 2021-09-22 8:11 ` Suzuki K Poulose 2021-10-01 4:35 ` Anshuman Khandual 2021-10-01 4:35 ` Anshuman Khandual 2021-10-07 16:09 ` Catalin Marinas 2021-10-07 16:09 ` Catalin Marinas 2021-09-21 13:41 ` [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 7:39 ` Anshuman Khandual 2021-09-22 7:39 ` Anshuman Khandual 2021-09-22 12:03 ` Suzuki K Poulose 2021-09-22 12:03 ` Suzuki K Poulose 2021-10-01 4:38 ` Anshuman Khandual 2021-10-01 4:38 ` Anshuman Khandual 2021-10-07 16:10 ` Catalin Marinas 2021-10-07 16:10 ` Catalin Marinas 2021-09-21 13:41 ` [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 7:59 ` Anshuman Khandual 2021-09-22 7:59 ` Anshuman Khandual 2021-10-04 17:42 ` Mathieu Poirier 2021-10-04 17:42 ` Mathieu Poirier 2021-10-05 22:35 ` Suzuki K Poulose 2021-10-05 22:35 ` Suzuki K Poulose 2021-10-06 17:15 ` Mathieu Poirier 2021-10-06 17:15 ` Mathieu Poirier 2021-10-07 9:18 ` Suzuki K Poulose 2021-10-07 9:18 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 9:51 ` Anshuman Khandual 2021-09-22 9:51 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 14/17] coresight: trbe: Make sure we have enough space Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 9:58 ` Anshuman Khandual 2021-09-22 9:58 ` Anshuman Khandual 2021-09-22 10:16 ` Suzuki K Poulose 2021-09-22 10:16 ` Suzuki K Poulose 2021-10-01 4:40 ` Anshuman Khandual 2021-10-01 4:40 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 10:59 ` Anshuman Khandual 2021-09-22 10:59 ` Anshuman Khandual 2021-10-07 16:10 ` Catalin Marinas 2021-10-07 16:10 ` Catalin Marinas 2021-09-21 13:41 ` [PATCH v2 16/17] coresight: trbe: Work around write to out of range Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-23 3:15 ` Anshuman Khandual 2021-09-23 3:15 ` Anshuman Khandual 2021-09-28 10:32 ` Suzuki K Poulose 2021-09-28 10:32 ` Suzuki K Poulose 2021-10-01 4:56 ` Anshuman Khandual 2021-10-01 4:56 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 17/17] arm64: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 11:03 ` Anshuman Khandual 2021-09-22 11:03 ` Anshuman Khandual 2021-10-07 16:11 ` Catalin Marinas 2021-10-07 16:11 ` Catalin Marinas 2021-10-05 17:04 ` [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Mathieu Poirier 2021-10-05 17:04 ` Mathieu Poirier 2021-10-08 7:32 ` Will Deacon 2021-10-08 7:32 ` Will Deacon 2021-10-08 9:25 ` Suzuki K Poulose 2021-10-08 9:25 ` Suzuki K Poulose 2021-10-08 9:52 ` Will Deacon 2021-10-08 9:52 ` Will Deacon 2021-10-08 9:57 ` Suzuki K Poulose 2021-10-08 9:57 ` Suzuki K Poulose
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