* [PATCH v3 0/3] arm64: dts: renesas: r8a779a0 DU support
@ 2021-09-23 1:03 Kieran Bingham
2021-09-23 1:04 ` [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Kieran Bingham @ 2021-09-23 1:03 UTC (permalink / raw)
To: linux-renesas-soc, Laurent Pinchart, Geert Uytterhoeven; +Cc: Kieran Bingham
Provide the DT nodes for the DU, and DSI found on the r8a779a0, and
extend the falcon-cpu board add on with the TI SN65DSI86 bridge which is
used to connect the DSI output to the mini display-port connector on the
Falcon CPU board.
Kieran Bingham (3):
arm64: dts: renesas: r8a779a0: Add DU support
arm64: dts: renesas: r8a779a0: Add DSI encoders
arm64: dts: renesas: r8a779a0: falcon-cpu: Add DSI display output
.../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 79 ++++++++++++++++
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 94 +++++++++++++++++++
2 files changed, 173 insertions(+)
--
2.30.2
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add DU support 2021-09-23 1:03 [PATCH v3 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham @ 2021-09-23 1:04 ` Kieran Bingham 2021-09-23 7:00 ` Geert Uytterhoeven 2021-09-24 14:23 ` [PATCH v3.1 " Kieran Bingham 2021-09-23 1:04 ` [PATCH v3 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham 2021-09-23 1:04 ` [PATCH v3 3/3] arm64: dts: renesas: r8a779a0: falcon-cpu: Add DSI display output Kieran Bingham 2 siblings, 2 replies; 9+ messages in thread From: Kieran Bingham @ 2021-09-23 1:04 UTC (permalink / raw) To: linux-renesas-soc, Laurent Pinchart, Geert Uytterhoeven Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Provide the device nodes for the DU on the V3U platforms. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- v2 - Use a single clock specification for the whole DU. v3: - Use 'du.0' clock name instead of 'du' arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f9a882b34f82..dfe99af89908 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1251,6 +1251,36 @@ vspd1: vsp@fea28000 { renesas,fcp = <&fcpvd1>; }; + du: display@feb00000 { + compatible = "renesas,du-r8a779a0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + vsps = <&vspd0 0>, <&vspd1 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- 2.30.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add DU support 2021-09-23 1:04 ` [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham @ 2021-09-23 7:00 ` Geert Uytterhoeven 2021-09-23 12:05 ` Kieran Bingham 2021-09-24 14:23 ` [PATCH v3.1 " Kieran Bingham 1 sibling, 1 reply; 9+ messages in thread From: Geert Uytterhoeven @ 2021-09-23 7:00 UTC (permalink / raw) To: Kieran Bingham Cc: Linux-Renesas, Laurent Pinchart, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Kieran, On Thu, Sep 23, 2021 at 3:04 AM Kieran Bingham <kieran.bingham@ideasonboard.com> wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > Provide the device nodes for the DU on the V3U platforms. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > --- > v2 > - Use a single clock specification for the whole DU. > > v3: > - Use 'du.0' clock name instead of 'du' Thanks for the update! > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > @@ -1251,6 +1251,36 @@ vspd1: vsp@fea28000 { > renesas,fcp = <&fcpvd1>; > }; > > + du: display@feb00000 { > + compatible = "renesas,du-r8a779a0"; > + reg = <0 0xfeb00000 0 0x40000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 411>; > + clock-names = "du.0"; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + resets = <&cpg 411>; You missed reset-names. > + vsps = <&vspd0 0>, <&vspd1 0>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + du_out_dsi0: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + du_out_dsi1: endpoint { > + }; > + }; > + }; > + }; > + > prr: chipid@fff00044 { > compatible = "renesas,prr"; > reg = <0 0xfff00044 0 4>; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add DU support 2021-09-23 7:00 ` Geert Uytterhoeven @ 2021-09-23 12:05 ` Kieran Bingham 2021-09-24 14:22 ` Kieran Bingham 0 siblings, 1 reply; 9+ messages in thread From: Kieran Bingham @ 2021-09-23 12:05 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Linux-Renesas, Laurent Pinchart, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Geert, On 23/09/2021 08:00, Geert Uytterhoeven wrote: > Hi Kieran, > > On Thu, Sep 23, 2021 at 3:04 AM Kieran Bingham > <kieran.bingham@ideasonboard.com> wrote: >> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> >> Provide the device nodes for the DU on the V3U platforms. >> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> >> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> >> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> >> --- >> v2 >> - Use a single clock specification for the whole DU. >> >> v3: >> - Use 'du.0' clock name instead of 'du' > > Thanks for the update! > >> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi >> @@ -1251,6 +1251,36 @@ vspd1: vsp@fea28000 { >> renesas,fcp = <&fcpvd1>; >> }; >> >> + du: display@feb00000 { >> + compatible = "renesas,du-r8a779a0"; >> + reg = <0 0xfeb00000 0 0x40000>; >> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cpg CPG_MOD 411>; >> + clock-names = "du.0"; >> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; >> + resets = <&cpg 411>; > > You missed reset-names. Adding it in now. Sorry I must get the dtchecks automated in my builds... -- Kieran > >> + vsps = <&vspd0 0>, <&vspd1 0>; >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + du_out_dsi0: endpoint { >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + du_out_dsi1: endpoint { >> + }; >> + }; >> + }; >> + }; >> + >> prr: chipid@fff00044 { >> compatible = "renesas,prr"; >> reg = <0 0xfff00044 0 4>; > > Gr{oetje,eeting}s, > > Geert > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add DU support 2021-09-23 12:05 ` Kieran Bingham @ 2021-09-24 14:22 ` Kieran Bingham 0 siblings, 0 replies; 9+ messages in thread From: Kieran Bingham @ 2021-09-24 14:22 UTC (permalink / raw) To: Kieran Bingham, Geert Uytterhoeven Cc: Linux-Renesas, Laurent Pinchart, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list On 23/09/2021 13:05, Kieran Bingham wrote: > Hi Geert, > > On 23/09/2021 08:00, Geert Uytterhoeven wrote: >> Hi Kieran, >> >> On Thu, Sep 23, 2021 at 3:04 AM Kieran Bingham >> <kieran.bingham@ideasonboard.com> wrote: >>> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> >>> Provide the device nodes for the DU on the V3U platforms. >>> >>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> >>> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> >>> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> >>> --- >>> v2 >>> - Use a single clock specification for the whole DU. >>> >>> v3: >>> - Use 'du.0' clock name instead of 'du' >> >> Thanks for the update! >> >>> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi >>> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi >>> @@ -1251,6 +1251,36 @@ vspd1: vsp@fea28000 { >>> renesas,fcp = <&fcpvd1>; >>> }; >>> >>> + du: display@feb00000 { >>> + compatible = "renesas,du-r8a779a0"; >>> + reg = <0 0xfeb00000 0 0x40000>; >>> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; >>> + clocks = <&cpg CPG_MOD 411>; >>> + clock-names = "du.0"; >>> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; >>> + resets = <&cpg 411>; >> >> You missed reset-names. > > Adding it in now. > > Sorry I must get the dtchecks automated in my builds... > > -- > Kieran > > >> >>> + vsps = <&vspd0 0>, <&vspd1 0>; Also, clearly this should be 'renesas,vsps =' ;-) -- Kieran >>> + status = "disabled"; >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + du_out_dsi0: endpoint { >>> + }; >>> + }; >>> + >>> + port@1 { >>> + reg = <1>; >>> + du_out_dsi1: endpoint { >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> prr: chipid@fff00044 { >>> compatible = "renesas,prr"; >>> reg = <0 0xfff00044 0 4>; >> >> Gr{oetje,eeting}s, >> >> Geert >> -- -- Kieran ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3.1 1/3] arm64: dts: renesas: r8a779a0: Add DU support 2021-09-23 1:04 ` [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham 2021-09-23 7:00 ` Geert Uytterhoeven @ 2021-09-24 14:23 ` Kieran Bingham 1 sibling, 0 replies; 9+ messages in thread From: Kieran Bingham @ 2021-09-24 14:23 UTC (permalink / raw) To: linux-renesas-soc, Laurent Pinchart, Geert Uytterhoeven Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Provide the device nodes for the DU on the V3U platforms. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- v2 - Use a single clock specification for the whole DU. v3: - Use 'du.0' clock name instead of 'du' v3.1: - Add in missing reset-names (at last) - Use full renesas,vsps --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f9a882b34f82..4312597bf315 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1251,6 +1251,38 @@ vspd1: vsp@fea28000 { renesas,fcp = <&fcpvd1>; }; + du: display@feb00000 { + compatible = "renesas,du-r8a779a0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- 2.30.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders 2021-09-23 1:03 [PATCH v3 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham 2021-09-23 1:04 ` [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham @ 2021-09-23 1:04 ` Kieran Bingham 2021-09-23 1:10 ` Laurent Pinchart 2021-09-23 1:04 ` [PATCH v3 3/3] arm64: dts: renesas: r8a779a0: falcon-cpu: Add DSI display output Kieran Bingham 2 siblings, 1 reply; 9+ messages in thread From: Kieran Bingham @ 2021-09-23 1:04 UTC (permalink / raw) To: linux-renesas-soc, Laurent Pinchart, Geert Uytterhoeven Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Provide the two MIPI DSI encoders on the V3U and connect them to the DU accordingly. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- v2 - Fixup indentation v3 - Fix the clock references - Fixup dsi1 as well arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 64 +++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index dfe99af89908..b81b2391ed29 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1270,12 +1270,76 @@ ports { port@0 { reg = <0>; du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; }; }; port@1 { reg = <1>; du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&extal_clk>; + clock-names = "fck", "dsi", "pll"; + + resets = <&cpg 415>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&extal_clk>; + clock-names = "fck", "dsi", "pll"; + + resets = <&cpg 416>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { }; }; }; -- 2.30.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders 2021-09-23 1:04 ` [PATCH v3 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham @ 2021-09-23 1:10 ` Laurent Pinchart 0 siblings, 0 replies; 9+ messages in thread From: Laurent Pinchart @ 2021-09-23 1:10 UTC (permalink / raw) To: Kieran Bingham Cc: linux-renesas-soc, Geert Uytterhoeven, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Kieran, Thank you for the patch. On Thu, Sep 23, 2021 at 02:04:01AM +0100, Kieran Bingham wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Provide the two MIPI DSI encoders on the V3U and connect them to the DU > accordingly. > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > --- > v2 > - Fixup indentation > > v3 > - Fix the clock references > - Fixup dsi1 as well > > arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 64 +++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > index dfe99af89908..b81b2391ed29 100644 > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > @@ -1270,12 +1270,76 @@ ports { > port@0 { > reg = <0>; > du_out_dsi0: endpoint { > + remote-endpoint = <&dsi0_in>; > }; > }; > > port@1 { > reg = <1>; > du_out_dsi1: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi-encoder@fed80000 { > + compatible = "renesas,r8a779a0-dsi-csi2-tx"; > + reg = <0 0xfed80000 0 0x10000>; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + clocks = <&cpg CPG_MOD 415>, > + <&cpg CPG_CORE R8A779A0_CLK_DSI>, > + <&extal_clk>; I'm not sure if EXTAL is the right clock, the datasheet isn't clear about this. It's a guess as good as any other of the possible options, so we could start with it and possibly fix it later, but could you try to get clarification from Renesas on this ? > + clock-names = "fck", "dsi", "pll"; > + > + resets = <&cpg 415>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&du_out_dsi0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi1: dsi-encoder@fed90000 { > + compatible = "renesas,r8a779a0-dsi-csi2-tx"; > + reg = <0 0xfed90000 0 0x10000>; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + clocks = <&cpg CPG_MOD 415>, > + <&cpg CPG_CORE R8A779A0_CLK_DSI>, > + <&extal_clk>; > + clock-names = "fck", "dsi", "pll"; > + > + resets = <&cpg 416>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi1_in: endpoint { > + remote-endpoint = <&du_out_dsi1>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi1_out: endpoint { > }; > }; > }; -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] arm64: dts: renesas: r8a779a0: falcon-cpu: Add DSI display output 2021-09-23 1:03 [PATCH v3 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham 2021-09-23 1:04 ` [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham 2021-09-23 1:04 ` [PATCH v3 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham @ 2021-09-23 1:04 ` Kieran Bingham 2 siblings, 0 replies; 9+ messages in thread From: Kieran Bingham @ 2021-09-23 1:04 UTC (permalink / raw) To: linux-renesas-soc, Laurent Pinchart, Geert Uytterhoeven Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Provide the display output using the sn65dsi86 MIPI DSI bridge Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- v3: - Fix the voltage regulator values - No longer override the clocks - use clk-x6 as clock node name .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index a0a1a1da0d87..9943f09a5cc6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -66,6 +66,15 @@ memory@700000000 { reg = <0x7 0x00000000 0x0 0x80000000>; }; + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -83,6 +92,41 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; }; &extal_clk { @@ -114,6 +158,41 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + + sn65dsi86@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; }; &i2c6 { -- 2.30.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-09-24 14:23 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-23 1:03 [PATCH v3 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham 2021-09-23 1:04 ` [PATCH v3 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham 2021-09-23 7:00 ` Geert Uytterhoeven 2021-09-23 12:05 ` Kieran Bingham 2021-09-24 14:22 ` Kieran Bingham 2021-09-24 14:23 ` [PATCH v3.1 " Kieran Bingham 2021-09-23 1:04 ` [PATCH v3 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham 2021-09-23 1:10 ` Laurent Pinchart 2021-09-23 1:04 ` [PATCH v3 3/3] arm64: dts: renesas: r8a779a0: falcon-cpu: Add DSI display output Kieran Bingham
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