* [Intel-gfx] [PATCH] drm/dp: Add Additional DP2 Headers
@ 2021-09-27 14:38 Fangzhi Zuo
2021-09-27 15:12 ` Harry Wentland
0 siblings, 1 reply; 2+ messages in thread
From: Fangzhi Zuo @ 2021-09-27 14:38 UTC (permalink / raw)
To: intel-gfx, jani.nikula
Cc: harry.wentland, Nicholas.Kazlauskas, wayne.lin, Fangzhi Zuo
Include FEC, DSC, Link Training related headers.
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
---
include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..bfd8e3e0171d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -453,6 +453,7 @@ struct drm_panel;
# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
+#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
@@ -537,6 +538,9 @@ struct drm_panel;
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
+/* DFP Capability Extension */
+#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
@@ -688,6 +692,7 @@ struct drm_panel;
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
# define DP_DECOMPRESSION_EN (1 << 0)
+#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE BIT(0)
@@ -743,6 +748,7 @@ struct drm_panel;
# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
+# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
#define DP_ADJUST_REQUEST_LANE0_1 0x206
#define DP_ADJUST_REQUEST_LANE2_3 0x207
@@ -865,6 +871,8 @@ struct drm_panel;
# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
# define DP_PHY_TEST_PATTERN_CP2520 0x5
+#define DP_PHY_SQUARE_PATTERN 0x249
+
#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
@@ -1109,6 +1117,18 @@ struct drm_panel;
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
+#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
+#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
+
+/* DSC Extended Capability Branch Total DSC Resources */
+#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 /* 2.0 */
+#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
+# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
+# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+# define DP_DSC_DECODER_COUNT_SHIFT 5
+
/* Protocol Converter Extension */
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/dp: Add Additional DP2 Headers
2021-09-27 14:38 [Intel-gfx] [PATCH] drm/dp: Add Additional DP2 Headers Fangzhi Zuo
@ 2021-09-27 15:12 ` Harry Wentland
0 siblings, 0 replies; 2+ messages in thread
From: Harry Wentland @ 2021-09-27 15:12 UTC (permalink / raw)
To: Fangzhi Zuo, intel-gfx, jani.nikula; +Cc: Nicholas.Kazlauskas, wayne.lin
On 2021-09-27 10:38, Fangzhi Zuo wrote:
> Include FEC, DSC, Link Training related headers.
>
> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Please send this to dri-devel and amd-gfx as well.
> ---
The section after the '---' is not part of the commit
description. Please mention here that this patch is based
on top of the other DP2.0 header patches from Intel and
leave a link here, for context.
> include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1d5b3dbb6e56..bfd8e3e0171d 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -453,6 +453,7 @@ struct drm_panel;
> # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
> # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
> # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
> +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
>
> /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
> #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
> @@ -537,6 +538,9 @@ struct drm_panel;
> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
>
> +/* DFP Capability Extension */
> +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> +
> /* Link Configuration */
> #define DP_LINK_BW_SET 0x100
> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> @@ -688,6 +692,7 @@ struct drm_panel;
>
> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> # define DP_DECOMPRESSION_EN (1 << 0)
> +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
>
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE BIT(0)
> @@ -743,6 +748,7 @@ struct drm_panel;
> # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
> # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
> # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
> +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
Are you sure this is DP 2.0? The DP2.0 spec has 'RESERVED'
bits after the STREAM_REGENERATION_STATUS.
>
> #define DP_ADJUST_REQUEST_LANE0_1 0x206
> #define DP_ADJUST_REQUEST_LANE2_3 0x207
> @@ -865,6 +871,8 @@ struct drm_panel;
> # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> # define DP_PHY_TEST_PATTERN_CP2520 0x5
>
> +#define DP_PHY_SQUARE_PATTERN 0x249
> +
> #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> @@ -1109,6 +1117,18 @@ struct drm_panel;
> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
>
> +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
> +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
> +
> +/* DSC Extended Capability Branch Total DSC Resources */
> +#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 /* 2.0 */
To align with the spec and make it easier to search this should be:
DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
> +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
> +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
> +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> +# define DP_DSC_DECODER_COUNT_SHIFT 5
> +
The spec seems to call these "DSC Decoder 1 Aggregation Support" and also
has a definition for "DSC Decoder 1 Maximum Slice Count"
Harry
> /* Protocol Converter Extension */
> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
> #define DP_CEC_TUNNELING_CAPABILITY 0x3000
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2021-09-27 14:38 [Intel-gfx] [PATCH] drm/dp: Add Additional DP2 Headers Fangzhi Zuo
2021-09-27 15:12 ` Harry Wentland
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