From: Alexandre Ghiti <alexandre.ghiti@canonical.com> To: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Zong Li <zong.li@sifive.com>, Anup Patel <anup@brainfault.org>, Atish Patra <Atish.Patra@wdc.com>, Christoph Hellwig <hch@lst.de>, Andrey Ryabinin <ryabinin.a.a@gmail.com>, Alexander Potapenko <glider@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, Dmitry Vyukov <dvyukov@google.com>, Ard Biesheuvel <ardb@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Kees Cook <keescook@chromium.org>, Guo Ren <guoren@linux.alibaba.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Cc: Alexandre Ghiti <alexandre.ghiti@canonical.com> Subject: [PATCH v2 10/10] riscv: Allow user to downgrade to sv39 when hw supports sv48 Date: Wed, 29 Sep 2021 16:51:13 +0200 [thread overview] Message-ID: <20210929145113.1935778-11-alexandre.ghiti@canonical.com> (raw) In-Reply-To: <20210929145113.1935778-1-alexandre.ghiti@canonical.com> This is made possible by using the mmu-type property of the cpu node of the device tree. By default, the kernel will boot with 4-level page table if the hw supports it but it can be interesting for the user to select 3-level page table as it is less memory consuming and faster since it requires less memory accesses in case of a TLB miss. Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> --- arch/riscv/mm/init.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index a304f2b3c178..676635f5d98a 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -641,10 +641,31 @@ static void __init disable_pgtable_l4(void) * then read SATP to see if the configuration was taken into account * meaning sv48 is supported. */ -static __init void set_satp_mode(void) +static __init void set_satp_mode(uintptr_t dtb_pa) { u64 identity_satp, hw_satp; uintptr_t set_satp_mode_pmd; + int cpus_node; + + /* Check if the user asked for sv39 explicitly in the device tree */ + cpus_node = fdt_path_offset((void *)dtb_pa, "/cpus"); + if (cpus_node >= 0) { + int node; + + fdt_for_each_subnode(node, (void *)dtb_pa, cpus_node) { + const char *mmu_type = fdt_getprop((void *)dtb_pa, node, + "mmu-type", NULL); + if (!mmu_type) + continue; + + if (!strcmp(mmu_type, "riscv,sv39")) { + disable_pgtable_l4(); + return; + } + + break; + } + } set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; create_pgd_mapping(early_pg_dir, @@ -802,7 +823,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) #endif #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) - set_satp_mode(); + set_satp_mode(dtb_pa); #endif kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Ghiti <alexandre.ghiti@canonical.com> To: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Zong Li <zong.li@sifive.com>, Anup Patel <anup@brainfault.org>, Atish Patra <Atish.Patra@wdc.com>, Christoph Hellwig <hch@lst.de>, Andrey Ryabinin <ryabinin.a.a@gmail.com>, Alexander Potapenko <glider@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, Dmitry Vyukov <dvyukov@google.com>, Ard Biesheuvel <ardb@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Kees Cook <keescook@chromium.org>, Guo Ren <guoren@linux.alibaba.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Cc: Alexandre Ghiti <alexandre.ghiti@canonical.com> Subject: [PATCH v2 10/10] riscv: Allow user to downgrade to sv39 when hw supports sv48 Date: Wed, 29 Sep 2021 16:51:13 +0200 [thread overview] Message-ID: <20210929145113.1935778-11-alexandre.ghiti@canonical.com> (raw) In-Reply-To: <20210929145113.1935778-1-alexandre.ghiti@canonical.com> This is made possible by using the mmu-type property of the cpu node of the device tree. By default, the kernel will boot with 4-level page table if the hw supports it but it can be interesting for the user to select 3-level page table as it is less memory consuming and faster since it requires less memory accesses in case of a TLB miss. Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> --- arch/riscv/mm/init.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index a304f2b3c178..676635f5d98a 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -641,10 +641,31 @@ static void __init disable_pgtable_l4(void) * then read SATP to see if the configuration was taken into account * meaning sv48 is supported. */ -static __init void set_satp_mode(void) +static __init void set_satp_mode(uintptr_t dtb_pa) { u64 identity_satp, hw_satp; uintptr_t set_satp_mode_pmd; + int cpus_node; + + /* Check if the user asked for sv39 explicitly in the device tree */ + cpus_node = fdt_path_offset((void *)dtb_pa, "/cpus"); + if (cpus_node >= 0) { + int node; + + fdt_for_each_subnode(node, (void *)dtb_pa, cpus_node) { + const char *mmu_type = fdt_getprop((void *)dtb_pa, node, + "mmu-type", NULL); + if (!mmu_type) + continue; + + if (!strcmp(mmu_type, "riscv,sv39")) { + disable_pgtable_l4(); + return; + } + + break; + } + } set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; create_pgd_mapping(early_pg_dir, @@ -802,7 +823,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) #endif #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) - set_satp_mode(); + set_satp_mode(dtb_pa); #endif kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-09-29 15:02 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-29 14:51 [PATCH v2 00/10] Introduce sv48 support without relocatable kernel Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 01/10] riscv: Allow to dynamically define VA_BITS Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 02/10] riscv: Get rid of MAXPHYSMEM configs Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 03/10] asm-generic: Prepare for riscv use of pud_alloc_one and pud_free Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 04/10] riscv: Implement sv48 support Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-10-04 1:34 ` Samuel Holland 2021-10-04 1:34 ` Samuel Holland 2021-10-04 7:31 ` Alexandre Ghiti 2021-10-04 7:31 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 05/10] riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 06/10] riscv: Explicit comment about user virtual address space size Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 07/10] riscv: Improve virtual kernel memory layout dump Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 08/10] Documentation: riscv: Add sv48 description to VM layout Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 09/10] riscv: Initialize thread pointer before calling C functions Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti [this message] 2021-09-29 14:51 ` [PATCH v2 10/10] riscv: Allow user to downgrade to sv39 when hw supports sv48 Alexandre Ghiti 2021-11-24 23:29 ` [PATCH v2 00/10] Introduce sv48 support without relocatable kernel Heiko Stübner 2021-11-24 23:29 ` Heiko Stübner 2021-12-06 10:49 ` Alexandre ghiti 2021-12-06 10:49 ` Alexandre ghiti 2021-12-06 11:17 ` Heiko Stübner 2021-12-06 11:17 ` Heiko Stübner
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