From: Alexandre Ghiti <alexandre.ghiti@canonical.com> To: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Zong Li <zong.li@sifive.com>, Anup Patel <anup@brainfault.org>, Atish Patra <Atish.Patra@wdc.com>, Christoph Hellwig <hch@lst.de>, Andrey Ryabinin <ryabinin.a.a@gmail.com>, Alexander Potapenko <glider@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, Dmitry Vyukov <dvyukov@google.com>, Ard Biesheuvel <ardb@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Kees Cook <keescook@chromium.org>, Guo Ren <guoren@linux.alibaba.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Cc: Alexandre Ghiti <alexandre.ghiti@canonical.com>, Palmer Dabbelt <palmerdabbelt@google.com> Subject: [PATCH v2 06/10] riscv: Explicit comment about user virtual address space size Date: Wed, 29 Sep 2021 16:51:09 +0200 [thread overview] Message-ID: <20210929145113.1935778-7-alexandre.ghiti@canonical.com> (raw) In-Reply-To: <20210929145113.1935778-1-alexandre.ghiti@canonical.com> Define precisely the size of the user accessible virtual space size for sv32/39/48 mmu types and explain why the whole virtual address space is split into 2 equal chunks between kernel and user space. Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> --- arch/riscv/include/asm/pgtable.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 2f92d61237b4..fd37cc45ef2a 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -664,6 +664,15 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, /* * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. * Note that PGDIR_SIZE must evenly divide TASK_SIZE. + * Task size is: + * - 0x9fc00000 (~2.5GB) for RV32. + * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu + * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * + * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V + * Instruction Set Manual Volume II: Privileged Architecture" states that + * "load and store effective addresses, which are 64bits, must have bits + * 63–48 all equal to bit 47, or else a page-fault exception will occur." */ #ifdef CONFIG_64BIT #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Ghiti <alexandre.ghiti@canonical.com> To: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Zong Li <zong.li@sifive.com>, Anup Patel <anup@brainfault.org>, Atish Patra <Atish.Patra@wdc.com>, Christoph Hellwig <hch@lst.de>, Andrey Ryabinin <ryabinin.a.a@gmail.com>, Alexander Potapenko <glider@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, Dmitry Vyukov <dvyukov@google.com>, Ard Biesheuvel <ardb@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Kees Cook <keescook@chromium.org>, Guo Ren <guoren@linux.alibaba.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Cc: Alexandre Ghiti <alexandre.ghiti@canonical.com>, Palmer Dabbelt <palmerdabbelt@google.com> Subject: [PATCH v2 06/10] riscv: Explicit comment about user virtual address space size Date: Wed, 29 Sep 2021 16:51:09 +0200 [thread overview] Message-ID: <20210929145113.1935778-7-alexandre.ghiti@canonical.com> (raw) In-Reply-To: <20210929145113.1935778-1-alexandre.ghiti@canonical.com> Define precisely the size of the user accessible virtual space size for sv32/39/48 mmu types and explain why the whole virtual address space is split into 2 equal chunks between kernel and user space. Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> --- arch/riscv/include/asm/pgtable.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 2f92d61237b4..fd37cc45ef2a 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -664,6 +664,15 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, /* * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. * Note that PGDIR_SIZE must evenly divide TASK_SIZE. + * Task size is: + * - 0x9fc00000 (~2.5GB) for RV32. + * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu + * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * + * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V + * Instruction Set Manual Volume II: Privileged Architecture" states that + * "load and store effective addresses, which are 64bits, must have bits + * 63–48 all equal to bit 47, or else a page-fault exception will occur." */ #ifdef CONFIG_64BIT #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-09-29 14:57 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-29 14:51 [PATCH v2 00/10] Introduce sv48 support without relocatable kernel Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 01/10] riscv: Allow to dynamically define VA_BITS Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 02/10] riscv: Get rid of MAXPHYSMEM configs Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 03/10] asm-generic: Prepare for riscv use of pud_alloc_one and pud_free Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 04/10] riscv: Implement sv48 support Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-10-04 1:34 ` Samuel Holland 2021-10-04 1:34 ` Samuel Holland 2021-10-04 7:31 ` Alexandre Ghiti 2021-10-04 7:31 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 05/10] riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti [this message] 2021-09-29 14:51 ` [PATCH v2 06/10] riscv: Explicit comment about user virtual address space size Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 07/10] riscv: Improve virtual kernel memory layout dump Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 08/10] Documentation: riscv: Add sv48 description to VM layout Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 09/10] riscv: Initialize thread pointer before calling C functions Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 10/10] riscv: Allow user to downgrade to sv39 when hw supports sv48 Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-11-24 23:29 ` [PATCH v2 00/10] Introduce sv48 support without relocatable kernel Heiko Stübner 2021-11-24 23:29 ` Heiko Stübner 2021-12-06 10:49 ` Alexandre ghiti 2021-12-06 10:49 ` Alexandre ghiti 2021-12-06 11:17 ` Heiko Stübner 2021-12-06 11:17 ` Heiko Stübner
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