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From: Frieder Schrempf <frieder@fris.de>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Shawn Guo <shawnguo@kernel.org>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fabio Estevam <festevam@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>
Subject: [PATCH 1/8] arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD card
Date: Thu, 30 Sep 2021 17:56:24 +0200	[thread overview]
Message-ID: <20210930155633.2745201-2-frieder@fris.de> (raw)
In-Reply-To: <20210930155633.2745201-1-frieder@fris.de>

From: Frieder Schrempf <frieder.schrempf@kontron.de>

In order to use ultra high speed modes (UHS) on the SD card slot, we
add matching pinctrls and fix the voltage switching for LDO5 of the
PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 .../dts/freescale/imx8mm-kontron-n801x-s.dts  | 28 ++++++++++++++++++-
 .../freescale/imx8mm-kontron-n801x-som.dtsi   |  2 ++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
index d17abb515835..62ba3bd08a0c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
@@ -189,8 +189,10 @@ usbnet: usbether@1 {
 };
 
 &usdhc2 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 	vmmc-supply = <&reg_vdd_3v3>;
 	vqmmc-supply = <&reg_nvcc_sd>;
 	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
@@ -319,4 +321,28 @@ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
 			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
 		>;
 	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
+		>;
+	};
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
index d0456daefda8..03b3516abd64 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
@@ -86,6 +86,7 @@ pca9450: pmic@25 {
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
 		regulators {
 			reg_vdd_soc: BUCK1 {
@@ -225,6 +226,7 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x141
+			MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x141
 		>;
 	};
 
-- 
2.33.0


WARNING: multiple messages have this Message-ID (diff)
From: Frieder Schrempf <frieder@fris.de>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Shawn Guo <shawnguo@kernel.org>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fabio Estevam <festevam@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>
Subject: [PATCH 1/8] arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD card
Date: Thu, 30 Sep 2021 17:56:24 +0200	[thread overview]
Message-ID: <20210930155633.2745201-2-frieder@fris.de> (raw)
In-Reply-To: <20210930155633.2745201-1-frieder@fris.de>

From: Frieder Schrempf <frieder.schrempf@kontron.de>

In order to use ultra high speed modes (UHS) on the SD card slot, we
add matching pinctrls and fix the voltage switching for LDO5 of the
PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 .../dts/freescale/imx8mm-kontron-n801x-s.dts  | 28 ++++++++++++++++++-
 .../freescale/imx8mm-kontron-n801x-som.dtsi   |  2 ++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
index d17abb515835..62ba3bd08a0c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
@@ -189,8 +189,10 @@ usbnet: usbether@1 {
 };
 
 &usdhc2 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 	vmmc-supply = <&reg_vdd_3v3>;
 	vqmmc-supply = <&reg_nvcc_sd>;
 	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
@@ -319,4 +321,28 @@ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
 			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
 		>;
 	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
+		>;
+	};
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
index d0456daefda8..03b3516abd64 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
@@ -86,6 +86,7 @@ pca9450: pmic@25 {
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
 		regulators {
 			reg_vdd_soc: BUCK1 {
@@ -225,6 +226,7 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x141
+			MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x141
 		>;
 	};
 
-- 
2.33.0


_______________________________________________
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  reply	other threads:[~2021-09-30 15:56 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-30 15:56 [PATCH 0/8] Devicetree fixes and additions for Kontron SL/BL i.MX8MM boards Frieder Schrempf
2021-09-30 15:56 ` Frieder Schrempf
2021-09-30 15:56 ` Frieder Schrempf [this message]
2021-09-30 15:56   ` [PATCH 1/8] arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD card Frieder Schrempf
2021-10-05  6:45   ` Shawn Guo
2021-10-05  6:45     ` Shawn Guo
2021-10-15 10:44     ` Frieder Schrempf
2021-10-15 10:44       ` Frieder Schrempf
2021-09-30 15:56 ` [PATCH 2/8] arm64: dts: imx8mm-kontron: Make sure SOC and DRAM supply voltages are correct Frieder Schrempf
2021-09-30 15:56   ` Frieder Schrempf
2021-09-30 16:02   ` Frieder Schrempf
2021-09-30 16:02     ` Frieder Schrempf
2021-10-05  6:49     ` Shawn Guo
2021-10-05  6:49       ` Shawn Guo
2021-10-05  6:53   ` Shawn Guo
2021-10-05  6:53     ` Shawn Guo
2021-10-05 13:10     ` Frieder Schrempf
2021-10-05 13:10       ` Frieder Schrempf
2021-10-15  3:51       ` Shawn Guo
2021-10-15  3:51         ` Shawn Guo
2021-09-30 15:56 ` [PATCH 3/8] arm64: dts: imx8mm-kontron: Set VDD_SNVS to 800 mV Frieder Schrempf
2021-09-30 15:56   ` Frieder Schrempf
2021-10-05  6:56   ` Shawn Guo
2021-10-05  6:56     ` Shawn Guo
2021-10-05 13:14     ` Frieder Schrempf
2021-10-05 13:14       ` Frieder Schrempf
2021-10-15  4:04       ` Shawn Guo
2021-10-15  4:04         ` Shawn Guo
2021-09-30 15:56 ` [PATCH 4/8] arm64: dts: imx8mm-kontron: Fix reg_rst_eth2 and reg_vdd_5v regulators Frieder Schrempf
2021-09-30 15:56   ` Frieder Schrempf
2021-10-05  7:09   ` Shawn Guo
2021-10-05  7:09     ` Shawn Guo
2021-10-05 17:06     ` Frieder Schrempf
2021-10-05 17:06       ` Frieder Schrempf
2021-10-15  4:09       ` Shawn Guo
2021-10-15  4:09         ` Shawn Guo
2021-10-15 11:32         ` Frieder Schrempf
2021-10-15 11:32           ` Frieder Schrempf
2021-09-30 15:56 ` [PATCH 5/8] arm64: dts: imx8mm-kontron: Fix CAN SPI clock frequency Frieder Schrempf
2021-09-30 15:56   ` Frieder Schrempf
2021-10-05  7:12   ` Shawn Guo
2021-10-05  7:12     ` Shawn Guo
2021-10-05 17:17     ` Frieder Schrempf
2021-10-05 17:17       ` Frieder Schrempf
2021-10-15  4:12       ` Shawn Guo
2021-10-15  4:12         ` Shawn Guo
2021-09-30 15:56 ` [PATCH 6/8] arm64: dts: imx8mm-kontron: Fix connection type for VSC8531 RGMII PHY Frieder Schrempf
2021-10-02 18:14   ` Heiko Thiery
2021-10-02 18:08   ` Heiko Thiery
2021-10-05  7:20   ` Shawn Guo
2021-10-05  7:20     ` Shawn Guo
2021-09-30 15:56 ` [PATCH 7/8] arm64: dts: imx8mm-kontron: Fix reset delays for ethernet PHY Frieder Schrempf
2021-09-30 15:56   ` Frieder Schrempf
2021-09-30 15:56 ` [PATCH 8/8] arm64: dts: imx8mm-kontron: Leave reg_vdd_arm always powered on Frieder Schrempf
2021-09-30 15:56   ` Frieder Schrempf
2021-09-30 18:52   ` Heiko Thiery
2021-09-30 18:52     ` Heiko Thiery
2021-10-05  7:27   ` Shawn Guo
2021-10-05  7:27     ` Shawn Guo

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