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From: Lucas Stach <l.stach@pengutronix.de>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Adam Ford <aford173@gmail.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Marek Vasut <marex@denx.de>, Tim Harvey <tharvey@gateworks.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	kernel@pengutronix.de, patchwork-lst@pengutronix.de
Subject: [PATCH v5 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
Date: Sat,  2 Oct 2021 02:59:39 +0200	[thread overview]
Message-ID: <20211002005954.1367653-4-l.stach@pengutronix.de> (raw)
In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de>

From: Marek Vasut <marex@denx.de>

To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.

Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/soc/imx/gpcv2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c7826ce92f0d..2c43e74db0be 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = BIT(IMX8MM_PGC_GPU2D),
+		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Lucas Stach <l.stach@pengutronix.de>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Adam Ford <aford173@gmail.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Marek Vasut <marex@denx.de>, Tim Harvey <tharvey@gateworks.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	kernel@pengutronix.de, patchwork-lst@pengutronix.de
Subject: [PATCH v5 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
Date: Sat,  2 Oct 2021 02:59:39 +0200	[thread overview]
Message-ID: <20211002005954.1367653-4-l.stach@pengutronix.de> (raw)
In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de>

From: Marek Vasut <marex@denx.de>

To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.

Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/soc/imx/gpcv2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c7826ce92f0d..2c43e74db0be 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = BIT(IMX8MM_PGC_GPU2D),
+		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
-- 
2.30.2


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  parent reply	other threads:[~2021-10-02  1:00 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-02  0:59 [PATCH v5 00/18] i.MX8MM GPC improvements and BLK_CTRL driver Lucas Stach
2021-10-02  0:59 ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up" Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-03 10:43   ` Adam Ford
2021-10-03 10:43     ` Adam Ford
2021-10-03 19:46     ` Lucas Stach
2021-10-03 19:46       ` Lucas Stach
2021-10-04  0:03       ` Adam Ford
2021-10-04  0:03         ` Adam Ford
2021-10-02  0:59 ` [PATCH v5 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` Lucas Stach [this message]
2021-10-02  0:59   ` [PATCH v5 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain Lucas Stach
2021-10-02  0:59 ` [PATCH v5 04/18] soc: imx: gpcv2: add lockdep annotation Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 06/18] soc: imx: gpcv2: keep i.MX8M* bus " Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 07/18] soc: imx: gpcv2: support system suspend/resume Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-12-08 13:47   ` [PATCH] hack: soc: imx: gpcv2: avoid unbalanced powering off of one device Martin Kepplinger
2021-12-08 13:47     ` Martin Kepplinger
2021-12-08 14:05     ` Lucas Stach
2021-12-08 14:05       ` Lucas Stach
2021-12-22  8:12       ` Martin Kepplinger
2021-12-22  8:12         ` Martin Kepplinger
2021-10-02  0:59 ` [PATCH v5 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 09/18] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 10/18] soc: imx: add i.MX8M blk-ctrl driver Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 12/18] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 14/18] arm64: dts: imx8mm: add GPC node Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 15/18] arm64: dts: imx8mm: put USB controllers into power-domains Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 16/18] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 17/18] arm64: dts: imx8mm: add VPU blk-ctrl Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-02  0:59 ` [PATCH v5 18/18] arm64: dts: imx8mm: add DISP blk-ctrl Lucas Stach
2021-10-02  0:59   ` Lucas Stach
2021-10-05  6:40 ` [PATCH v5 00/18] i.MX8MM GPC improvements and BLK_CTRL driver Shawn Guo
2021-10-05  6:40   ` Shawn Guo

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