From: Lucas Stach <l.stach@pengutronix.de> To: Shawn Guo <shawnguo@kernel.org> Cc: Rob Herring <robh+dt@kernel.org>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, Adam Ford <aford173@gmail.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Marek Vasut <marex@denx.de>, Tim Harvey <tharvey@gateworks.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Date: Sat, 2 Oct 2021 02:59:44 +0200 [thread overview] Message-ID: <20211002005954.1367653-9-l.stach@pengutronix.de> (raw) In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> This adds the DT binding for the i.MX8MM VPU blk-ctrl. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> --- .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..26487daa64d9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MM VPU blk-ctrl + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: + The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mm-vpu-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 4 + maxItems: 4 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + - const: h1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: g1 + - const: g2 + - const: h1 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + #include <dt-bindings/power/imx8mm-power.h> + + vpu_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_h1>; + power-domain-names = "bus", "g1", "g2", "h1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, + <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "g1", "g2", "h1"; + #power-domain-cells = <1>; + }; -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Lucas Stach <l.stach@pengutronix.de> To: Shawn Guo <shawnguo@kernel.org> Cc: Rob Herring <robh+dt@kernel.org>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, Adam Ford <aford173@gmail.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Marek Vasut <marex@denx.de>, Tim Harvey <tharvey@gateworks.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Date: Sat, 2 Oct 2021 02:59:44 +0200 [thread overview] Message-ID: <20211002005954.1367653-9-l.stach@pengutronix.de> (raw) In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> This adds the DT binding for the i.MX8MM VPU blk-ctrl. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> --- .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..26487daa64d9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MM VPU blk-ctrl + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: + The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mm-vpu-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 4 + maxItems: 4 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + - const: h1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: g1 + - const: g2 + - const: h1 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + #include <dt-bindings/power/imx8mm-power.h> + + vpu_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_h1>; + power-domain-names = "bus", "g1", "g2", "h1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, + <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "g1", "g2", "h1"; + #power-domain-cells = <1>; + }; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-02 1:00 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-02 0:59 [PATCH v5 00/18] i.MX8MM GPC improvements and BLK_CTRL driver Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up" Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-03 10:43 ` Adam Ford 2021-10-03 10:43 ` Adam Ford 2021-10-03 19:46 ` Lucas Stach 2021-10-03 19:46 ` Lucas Stach 2021-10-04 0:03 ` Adam Ford 2021-10-04 0:03 ` Adam Ford 2021-10-02 0:59 ` [PATCH v5 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 04/18] soc: imx: gpcv2: add lockdep annotation Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 06/18] soc: imx: gpcv2: keep i.MX8M* bus " Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 07/18] soc: imx: gpcv2: support system suspend/resume Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-12-08 13:47 ` [PATCH] hack: soc: imx: gpcv2: avoid unbalanced powering off of one device Martin Kepplinger 2021-12-08 13:47 ` Martin Kepplinger 2021-12-08 14:05 ` Lucas Stach 2021-12-08 14:05 ` Lucas Stach 2021-12-22 8:12 ` Martin Kepplinger 2021-12-22 8:12 ` Martin Kepplinger 2021-10-02 0:59 ` Lucas Stach [this message] 2021-10-02 0:59 ` [PATCH v5 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Lucas Stach 2021-10-02 0:59 ` [PATCH v5 09/18] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 10/18] soc: imx: add i.MX8M blk-ctrl driver Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 12/18] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 14/18] arm64: dts: imx8mm: add GPC node Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 15/18] arm64: dts: imx8mm: put USB controllers into power-domains Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 16/18] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 17/18] arm64: dts: imx8mm: add VPU blk-ctrl Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-02 0:59 ` [PATCH v5 18/18] arm64: dts: imx8mm: add DISP blk-ctrl Lucas Stach 2021-10-02 0:59 ` Lucas Stach 2021-10-05 6:40 ` [PATCH v5 00/18] i.MX8MM GPC improvements and BLK_CTRL driver Shawn Guo 2021-10-05 6:40 ` Shawn Guo
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