From: Will Deacon <will@kernel.org> To: Huangzhaoyang <huangzhaoyang@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com>, Mark Rutland <mark.rutland@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Ionela Voinescu <ionela.voinescu@arm.com>, Quentin Perret <qperret@google.com>, Vladimir Murzin <vladimir.murzin@arm.com>, linux-arm-kernel@lists.infradead.org, Zhaoyang Huang <zhaoyang.huang@unisoc.com>, linux-kernel@vger.kernel.org, ke.wang@unisoc.com Subject: Re: [RFC PATCH] arch: ARM64: add isb before enable pan Date: Fri, 8 Oct 2021 09:01:15 +0100 [thread overview] Message-ID: <20211008080113.GA441@willie-the-truck> (raw) In-Reply-To: <1633673269-15048-1-git-send-email-huangzhaoyang@gmail.com> Hi, On Fri, Oct 08, 2021 at 02:07:49PM +0800, Huangzhaoyang wrote: > From: Zhaoyang Huang <zhaoyang.huang@unisoc.com> > > set_pstate_pan failure is observed in an ARM64 system occasionaly on a reboot > test, which can be work around by a msleep on the sw context. We assume > suspicious on disorder of previous instr of disabling SW_PAN and add an isb here. > > PS: > The bootup test failed with a invalid TTBR1_EL1 that equals 0x34000000, which is > alike racing between on chip PAN and SW_PAN. Sorry, but I'm struggling to understand the problem here. Please could you explain it in more detail? - Why does a TTBR1_EL1 value of `0x34000000` indicate a race? - Can you explain the race that you think might be occurring? - Why does an ISB prevent the race? > Signed-off-by: Zhaoyang Huang <zhaoyang.huang@unisoc.com> > --- > arch/arm64/kernel/cpufeature.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index efed283..3c0de0d 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1663,6 +1663,7 @@ static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) > WARN_ON_ONCE(in_interrupt()); > > sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); > + isb(); > set_pstate_pan(1); SCTLR_EL1.SPAN only affects the PAN behaviour on taking an exception, which is itself a context-synchronizing event, so I can't see why the ISB makes any difference here (at least, for the purposes of PAN). Thanks, Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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From: Will Deacon <will@kernel.org> To: Huangzhaoyang <huangzhaoyang@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com>, Mark Rutland <mark.rutland@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Ionela Voinescu <ionela.voinescu@arm.com>, Quentin Perret <qperret@google.com>, Vladimir Murzin <vladimir.murzin@arm.com>, linux-arm-kernel@lists.infradead.org, Zhaoyang Huang <zhaoyang.huang@unisoc.com>, linux-kernel@vger.kernel.org, ke.wang@unisoc.com Subject: Re: [RFC PATCH] arch: ARM64: add isb before enable pan Date: Fri, 8 Oct 2021 09:01:15 +0100 [thread overview] Message-ID: <20211008080113.GA441@willie-the-truck> (raw) In-Reply-To: <1633673269-15048-1-git-send-email-huangzhaoyang@gmail.com> Hi, On Fri, Oct 08, 2021 at 02:07:49PM +0800, Huangzhaoyang wrote: > From: Zhaoyang Huang <zhaoyang.huang@unisoc.com> > > set_pstate_pan failure is observed in an ARM64 system occasionaly on a reboot > test, which can be work around by a msleep on the sw context. We assume > suspicious on disorder of previous instr of disabling SW_PAN and add an isb here. > > PS: > The bootup test failed with a invalid TTBR1_EL1 that equals 0x34000000, which is > alike racing between on chip PAN and SW_PAN. Sorry, but I'm struggling to understand the problem here. Please could you explain it in more detail? - Why does a TTBR1_EL1 value of `0x34000000` indicate a race? - Can you explain the race that you think might be occurring? - Why does an ISB prevent the race? > Signed-off-by: Zhaoyang Huang <zhaoyang.huang@unisoc.com> > --- > arch/arm64/kernel/cpufeature.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index efed283..3c0de0d 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1663,6 +1663,7 @@ static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) > WARN_ON_ONCE(in_interrupt()); > > sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); > + isb(); > set_pstate_pan(1); SCTLR_EL1.SPAN only affects the PAN behaviour on taking an exception, which is itself a context-synchronizing event, so I can't see why the ISB makes any difference here (at least, for the purposes of PAN). Thanks, Will
next prev parent reply other threads:[~2021-10-08 8:03 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-08 6:07 [RFC PATCH] arch: ARM64: add isb before enable pan Huangzhaoyang 2021-10-08 6:07 ` Huangzhaoyang 2021-10-08 8:01 ` Will Deacon [this message] 2021-10-08 8:01 ` Will Deacon 2021-10-08 8:34 ` Zhaoyang Huang 2021-10-08 8:34 ` Zhaoyang Huang 2021-10-08 8:45 ` Catalin Marinas 2021-10-08 8:45 ` Catalin Marinas 2021-10-08 8:55 ` Zhaoyang Huang 2021-10-08 8:55 ` Zhaoyang Huang 2021-10-08 9:07 ` Catalin Marinas 2021-10-08 9:07 ` Catalin Marinas 2021-10-11 2:49 ` Zhaoyang Huang 2021-10-11 2:49 ` Zhaoyang Huang 2021-10-11 9:38 ` Mark Rutland 2021-10-11 9:38 ` Mark Rutland 2021-10-11 11:08 ` Zhaoyang Huang 2021-10-11 11:08 ` Zhaoyang Huang 2021-10-11 12:15 ` Mark Rutland 2021-10-11 12:15 ` Mark Rutland
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