Re: [RFC PATCH] arch: ARM64: add isb before enable pan

From: Zhaoyang Huang <huangzhaoyang@gmail.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Ionela Voinescu <ionela.voinescu@arm.com>,
	Quentin Perret <qperret@google.com>,
	Vladimir Murzin <vladimir.murzin@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Zhaoyang Huang <zhaoyang.huang@unisoc.com>,
	LKML <linux-kernel@vger.kernel.org>, Ke Wang <ke.wang@unisoc.com>,
	ping.zhou1@unisoc.com
Subject: Re: [RFC PATCH] arch: ARM64: add isb before enable pan
Date: Mon, 11 Oct 2021 10:49:00 +0800	[thread overview]
Message-ID: <CAGWkznHxQBKgz3Axq=hmTOz0BY6ebb7cPtb+xGxCBFv729ULvg@mail.gmail.com> (raw)
In-Reply-To: <YWAKSoBW2KLHSFp1@arm.com>

On Fri, Oct 8, 2021 at 5:07 PM Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Fri, Oct 08, 2021 at 04:55:05PM +0800, Zhaoyang Huang wrote:
> > On Fri, Oct 8, 2021 at 4:45 PM Catalin Marinas <catalin.marinas@arm.com> wrote:
> > > On Fri, Oct 08, 2021 at 04:34:12PM +0800, Zhaoyang Huang wrote:
> > > > On Fri, Oct 8, 2021 at 4:01 PM Will Deacon <will@kernel.org> wrote:
> > > > > On Fri, Oct 08, 2021 at 02:07:49PM +0800, Huangzhaoyang wrote:
> > > > > > From: Zhaoyang Huang <zhaoyang.huang@unisoc.com>
> > > > > >
> > > > > > set_pstate_pan failure is observed in an ARM64 system occasionaly on a reboot
> > > > > > test, which can be work around by a msleep on the sw context. We assume
> > > > > > suspicious on disorder of previous instr of disabling SW_PAN and add an isb here.
> > > > > >
> > > > > > PS:
> > > > > > The bootup test failed with a invalid TTBR1_EL1 that equals 0x34000000, which is
> > > > > > alike racing between on chip PAN and SW_PAN.
> > > > >
> > > > > Sorry, but I'm struggling to understand the problem here. Please could you
> > > > > explain it in more detail?
> > > > >
> > > > >   - Why does a TTBR1_EL1 value of `0x34000000` indicate a race?
> > > > >   - Can you explain the race that you think might be occurring?
> > > > >   - Why does an ISB prevent the race?
> > > > Please find panic logs[1], related codes[2], sample of debug patch[3]
> > > > below. TTBR1_EL1 equals 0x34000000 when panic and can NOT be captured
> > > > by the debug patch during retest (all entrances that msr ttbr1_el1 are
> > > > under watch) which should work. Adding ISB here to prevent race on
> > > > TTBR1 from previous access of sysregs which can affect the msr
> > > > result(the test is still ongoing). Could the race be
> > > > ARM64_HAS_PAN(automated by core) and SW_PAN.
> > >
> > > Can you please change the ARM64_HAS_PAN type to
> > > ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE? I wonder whether
> > > system_uses_ttbr0_pan() changes its output when all CPUs had been
> > > brought up and system_uses_hw_pan() returns true.
> >
> > ok, thanks. We will try. Is it a workaround for known defect?
>
> No, other than the potential kernel bug you reported.
Changing the type to ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE doesn't work
for this issue.
>
> --
> Catalin