From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Matt Roper <matthew.d.roper@intel.com> Subject: [PATCH 00/11] i915: Initial multi-tile support Date: Fri, 8 Oct 2021 14:56:24 -0700 [thread overview] Message-ID: <20211008215635.2026385-1-matthew.d.roper@intel.com> (raw) Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform. Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of "tile" is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work. Daniele Ceraolo Spurio (2): drm/i915: split general MMIO setup from per-GT uncore init drm/i915: Initial support for per-tile uncore Matt Roper (1): drm/i915: Restructure probe to handle multi-tile platforms Michal Wajdeczko (1): drm/i915/guc: Update CT debug macro for multi-tile Michał Winiarski (1): drm/i915: Store backpointer to GT in uncore Paulo Zanoni (3): drm/i915: rework some irq functions to take intel_gt as argument drm/i915/xehp: Determine which tile raised an interrupt drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Tvrtko Ursulin (2): drm/i915: Prepare for multiple gts drm/i915/xehpsdv: Initialize multi-tiles Venkata Sandeep Dhanalakota (1): drm/i915: Release per-gt resources allocated drivers/gpu/drm/i915/gt/intel_gt.c | 180 +++++++++++++++++- drivers/gpu/drm/i915/gt/intel_gt.h | 11 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_drv.c | 80 ++++++-- drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_irq.c | 71 ++++--- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_memory_region.h | 3 + drivers/gpu/drm/i915/intel_uncore.c | 36 ++-- drivers/gpu/drm/i915/intel_uncore.h | 6 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +- 17 files changed, 345 insertions(+), 89 deletions(-) -- 2.33.0
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Matt Roper <matthew.d.roper@intel.com> Subject: [Intel-gfx] [PATCH 00/11] i915: Initial multi-tile support Date: Fri, 8 Oct 2021 14:56:24 -0700 [thread overview] Message-ID: <20211008215635.2026385-1-matthew.d.roper@intel.com> (raw) Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform. Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of "tile" is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work. Daniele Ceraolo Spurio (2): drm/i915: split general MMIO setup from per-GT uncore init drm/i915: Initial support for per-tile uncore Matt Roper (1): drm/i915: Restructure probe to handle multi-tile platforms Michal Wajdeczko (1): drm/i915/guc: Update CT debug macro for multi-tile Michał Winiarski (1): drm/i915: Store backpointer to GT in uncore Paulo Zanoni (3): drm/i915: rework some irq functions to take intel_gt as argument drm/i915/xehp: Determine which tile raised an interrupt drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Tvrtko Ursulin (2): drm/i915: Prepare for multiple gts drm/i915/xehpsdv: Initialize multi-tiles Venkata Sandeep Dhanalakota (1): drm/i915: Release per-gt resources allocated drivers/gpu/drm/i915/gt/intel_gt.c | 180 +++++++++++++++++- drivers/gpu/drm/i915/gt/intel_gt.h | 11 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_drv.c | 80 ++++++-- drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_irq.c | 71 ++++--- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_memory_region.h | 3 + drivers/gpu/drm/i915/intel_uncore.c | 36 ++-- drivers/gpu/drm/i915/intel_uncore.h | 6 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +- 17 files changed, 345 insertions(+), 89 deletions(-) -- 2.33.0
next reply other threads:[~2021-10-08 21:57 UTC|newest] Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-08 21:56 Matt Roper [this message] 2021-10-08 21:56 ` [Intel-gfx] [PATCH 00/11] i915: Initial multi-tile support Matt Roper 2021-10-08 21:56 ` [PATCH 01/11] drm/i915: rework some irq functions to take intel_gt as argument Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-27 6:22 ` Lucas De Marchi 2021-10-28 14:13 ` Andi Shyti 2021-10-08 21:56 ` [PATCH 02/11] drm/i915: split general MMIO setup from per-GT uncore init Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-27 6:26 ` Lucas De Marchi 2021-10-28 14:17 ` Andi Shyti 2021-10-08 21:56 ` [PATCH 03/11] drm/i915: Restructure probe to handle multi-tile platforms Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-13 12:12 ` Jani Nikula 2021-10-13 12:12 ` [Intel-gfx] " Jani Nikula 2021-10-27 6:57 ` Lucas De Marchi 2021-10-27 7:58 ` Jani Nikula 2021-10-08 21:56 ` [PATCH 04/11] drm/i915: Store backpointer to GT in uncore Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-28 14:26 ` Andi Shyti 2021-10-08 21:56 ` [PATCH 05/11] drm/i915: Prepare for multiple gts Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-27 7:01 ` Lucas De Marchi 2021-10-08 21:56 ` [PATCH 06/11] drm/i915: Initial support for per-tile uncore Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-28 15:41 ` Andi Shyti 2021-10-08 21:56 ` [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-08 23:48 ` Matt Roper 2021-10-08 23:48 ` [Intel-gfx] " Matt Roper 2021-10-13 0:55 ` Andi Shyti 2021-10-27 7:13 ` Lucas De Marchi 2021-10-27 7:13 ` [Intel-gfx] " Lucas De Marchi 2021-10-08 21:56 ` [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-28 16:30 ` Andi Shyti 2021-10-28 23:20 ` Matt Roper 2021-10-29 0:16 ` Andi Shyti 2021-10-08 21:56 ` [PATCH 09/11] drm/i915/guc: Update CT debug macro for multi-tile Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-08 21:56 ` [PATCH 10/11] drm/i915: Release per-gt resources allocated Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-28 16:33 ` Andi Shyti 2021-10-08 21:56 ` [PATCH 11/11] drm/i915/xehpsdv: Initialize multi-tiles Matt Roper 2021-10-08 21:56 ` [Intel-gfx] " Matt Roper 2021-10-08 23:33 ` [PATCH v2 " Matt Roper 2021-10-08 23:33 ` [Intel-gfx] " Matt Roper 2021-10-11 7:51 ` Tvrtko Ursulin 2021-10-12 23:11 ` Andi Shyti 2021-10-08 22:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support Patchwork 2021-10-08 23:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-10-09 0:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev2) Patchwork 2021-10-09 0:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-10-09 2:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial multi-tile support Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20211008215635.2026385-1-matthew.d.roper@intel.com \ --to=matthew.d.roper@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.