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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	Paulo Zanoni <paulo.r.zanoni@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>
Subject: [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
Date: Fri,  8 Oct 2021 14:56:32 -0700	[thread overview]
Message-ID: <20211008215635.2026385-9-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20211008215635.2026385-1-matthew.d.roper@intel.com>

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Loop through all the tiles when initializing and resetting interrupts.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f99ad56cde6..e788e283d4a8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3190,14 +3190,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_gt *gt = &dev_priv->gt;
 	struct intel_uncore *uncore = gt->uncore;
+	unsigned int i;
 
 	dg1_master_intr_disable(dev_priv->uncore.regs);
 
-	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(dev_priv);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_reset(gt);
 
-	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
-	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+		uncore = gt->uncore;
+		GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+		GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+	}
+
+	gen11_display_irq_reset(dev_priv);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3890,13 +3895,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = &dev_priv->gt;
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_gt *gt;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+	unsigned int i;
 
-	gen11_gt_irq_postinstall(gt);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_postinstall(gt);
 
-	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+		GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+			      gu_misc_masked);
+	}
 
 	if (HAS_DISPLAY(dev_priv)) {
 		icp_irq_postinstall(dev_priv);
@@ -3905,8 +3913,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 				   GEN11_DISPLAY_IRQ_ENABLE);
 	}
 
-	dg1_master_intr_enable(uncore->regs);
-	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+	dg1_master_intr_enable(dev_priv->gt.uncore->regs);
+	intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR);
 }
 
 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.33.0


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	Paulo Zanoni <paulo.r.zanoni@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>
Subject: [Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
Date: Fri,  8 Oct 2021 14:56:32 -0700	[thread overview]
Message-ID: <20211008215635.2026385-9-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20211008215635.2026385-1-matthew.d.roper@intel.com>

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Loop through all the tiles when initializing and resetting interrupts.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f99ad56cde6..e788e283d4a8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3190,14 +3190,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_gt *gt = &dev_priv->gt;
 	struct intel_uncore *uncore = gt->uncore;
+	unsigned int i;
 
 	dg1_master_intr_disable(dev_priv->uncore.regs);
 
-	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(dev_priv);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_reset(gt);
 
-	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
-	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+		uncore = gt->uncore;
+		GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+		GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+	}
+
+	gen11_display_irq_reset(dev_priv);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3890,13 +3895,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = &dev_priv->gt;
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_gt *gt;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+	unsigned int i;
 
-	gen11_gt_irq_postinstall(gt);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_postinstall(gt);
 
-	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+		GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+			      gu_misc_masked);
+	}
 
 	if (HAS_DISPLAY(dev_priv)) {
 		icp_irq_postinstall(dev_priv);
@@ -3905,8 +3913,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 				   GEN11_DISPLAY_IRQ_ENABLE);
 	}
 
-	dg1_master_intr_enable(uncore->regs);
-	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+	dg1_master_intr_enable(dev_priv->gt.uncore->regs);
+	intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR);
 }
 
 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.33.0


  parent reply	other threads:[~2021-10-08 21:57 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-08 21:56 [PATCH 00/11] i915: Initial multi-tile support Matt Roper
2021-10-08 21:56 ` [Intel-gfx] " Matt Roper
2021-10-08 21:56 ` [PATCH 01/11] drm/i915: rework some irq functions to take intel_gt as argument Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-27  6:22   ` Lucas De Marchi
2021-10-28 14:13   ` Andi Shyti
2021-10-08 21:56 ` [PATCH 02/11] drm/i915: split general MMIO setup from per-GT uncore init Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-27  6:26   ` Lucas De Marchi
2021-10-28 14:17   ` Andi Shyti
2021-10-08 21:56 ` [PATCH 03/11] drm/i915: Restructure probe to handle multi-tile platforms Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-13 12:12   ` Jani Nikula
2021-10-13 12:12     ` [Intel-gfx] " Jani Nikula
2021-10-27  6:57     ` Lucas De Marchi
2021-10-27  7:58       ` Jani Nikula
2021-10-08 21:56 ` [PATCH 04/11] drm/i915: Store backpointer to GT in uncore Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-28 14:26   ` Andi Shyti
2021-10-08 21:56 ` [PATCH 05/11] drm/i915: Prepare for multiple gts Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-27  7:01   ` Lucas De Marchi
2021-10-08 21:56 ` [PATCH 06/11] drm/i915: Initial support for per-tile uncore Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-28 15:41   ` Andi Shyti
2021-10-08 21:56 ` [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-08 23:48   ` Matt Roper
2021-10-08 23:48     ` [Intel-gfx] " Matt Roper
2021-10-13  0:55   ` Andi Shyti
2021-10-27  7:13   ` Lucas De Marchi
2021-10-27  7:13     ` [Intel-gfx] " Lucas De Marchi
2021-10-08 21:56 ` Matt Roper [this message]
2021-10-08 21:56   ` [Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Matt Roper
2021-10-28 16:30   ` Andi Shyti
2021-10-28 23:20     ` Matt Roper
2021-10-29  0:16       ` Andi Shyti
2021-10-08 21:56 ` [PATCH 09/11] drm/i915/guc: Update CT debug macro for multi-tile Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-08 21:56 ` [PATCH 10/11] drm/i915: Release per-gt resources allocated Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-28 16:33   ` Andi Shyti
2021-10-08 21:56 ` [PATCH 11/11] drm/i915/xehpsdv: Initialize multi-tiles Matt Roper
2021-10-08 21:56   ` [Intel-gfx] " Matt Roper
2021-10-08 23:33   ` [PATCH v2 " Matt Roper
2021-10-08 23:33     ` [Intel-gfx] " Matt Roper
2021-10-11  7:51     ` Tvrtko Ursulin
2021-10-12 23:11     ` Andi Shyti
2021-10-08 22:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support Patchwork
2021-10-08 23:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-09  0:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev2) Patchwork
2021-10-09  0:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-09  2:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial multi-tile support Patchwork

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