* [Intel-gfx] [PATCH 1/9] drm/i915: Move PCH refclok stuff into its own file
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-17 23:56 ` David Airlie
2021-10-15 7:16 ` [Intel-gfx] [PATCH 2/9] drm/i915: Move PCH modeset code to " Ville Syrjala
` (15 subsequent siblings)
16 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the PCH refclk stuff (including all the LPT/WPT
iCLKIP/CLKOUT_DP things) to its own file.
We also suck in the mPHY programming from intel_fdi.c
since we're the only caller.
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 537 +--------------
drivers/gpu/drm/i915/display/intel_display.h | 4 -
.../drm/i915/display/intel_display_power.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
drivers/gpu/drm/i915/display/intel_fdi.c | 99 ---
drivers/gpu/drm/i915/display/intel_fdi.h | 1 -
.../gpu/drm/i915/display/intel_pch_refclk.c | 648 ++++++++++++++++++
.../gpu/drm/i915/display/intel_pch_refclk.h | 21 +
drivers/gpu/drm/i915/i915_drv.c | 1 +
11 files changed, 675 insertions(+), 640 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pch_refclk.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pch_refclk.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 660bb03de6fc..96f3b8f6c50d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -226,6 +226,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
display/intel_overlay.o \
+ display/intel_pch_refclk.o \
display/intel_plane_initial.o \
display/intel_psr.o \
display/intel_quirks.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 1c161eeed82f..bf03bd0ecd43 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -45,6 +45,7 @@
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug.h"
+#include "intel_pch_refclk.h"
/* Here's the desired hotplug mode */
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ff598b6cd953..995050443065 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -96,6 +96,7 @@
#include "intel_hotplug.h"
#include "intel_overlay.h"
#include "intel_panel.h"
+#include "intel_pch_refclk.h"
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
@@ -103,7 +104,6 @@
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_quirks.h"
-#include "intel_sbi.h"
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vga.h"
@@ -1388,133 +1388,6 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
return false;
}
-void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
-{
- u32 temp;
-
- intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
-
- mutex_lock(&dev_priv->sb_lock);
-
- temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
- temp |= SBI_SSCCTL_DISABLE;
- intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
-
- mutex_unlock(&dev_priv->sb_lock);
-}
-
-/* Program iCLKIP clock to the desired frequency */
-static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int clock = crtc_state->hw.adjusted_mode.crtc_clock;
- u32 divsel, phaseinc, auxdiv, phasedir = 0;
- u32 temp;
-
- lpt_disable_iclkip(dev_priv);
-
- /* The iCLK virtual clock root frequency is in MHz,
- * but the adjusted_mode->crtc_clock in in KHz. To get the
- * divisors, it is necessary to divide one by another, so we
- * convert the virtual clock precision to KHz here for higher
- * precision.
- */
- for (auxdiv = 0; auxdiv < 2; auxdiv++) {
- u32 iclk_virtual_root_freq = 172800 * 1000;
- u32 iclk_pi_range = 64;
- u32 desired_divisor;
-
- desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
- clock << auxdiv);
- divsel = (desired_divisor / iclk_pi_range) - 2;
- phaseinc = desired_divisor % iclk_pi_range;
-
- /*
- * Near 20MHz is a corner case which is
- * out of range for the 7-bit divisor
- */
- if (divsel <= 0x7f)
- break;
- }
-
- /* This should not happen with any sane values */
- drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
- ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
- drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
- ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
-
- drm_dbg_kms(&dev_priv->drm,
- "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
- clock, auxdiv, divsel, phasedir, phaseinc);
-
- mutex_lock(&dev_priv->sb_lock);
-
- /* Program SSCDIVINTPHASE6 */
- temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
- temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
- temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
- temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
- temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
- temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
- temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
- intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
-
- /* Program SSCAUXDIV */
- temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
- temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
- temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
- intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
-
- /* Enable modulator and associated divider */
- temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
- temp &= ~SBI_SSCCTL_DISABLE;
- intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
-
- mutex_unlock(&dev_priv->sb_lock);
-
- /* Wait for initialization time */
- udelay(24);
-
- intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
-}
-
-int lpt_get_iclkip(struct drm_i915_private *dev_priv)
-{
- u32 divsel, phaseinc, auxdiv;
- u32 iclk_virtual_root_freq = 172800 * 1000;
- u32 iclk_pi_range = 64;
- u32 desired_divisor;
- u32 temp;
-
- if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
- return 0;
-
- mutex_lock(&dev_priv->sb_lock);
-
- temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
- if (temp & SBI_SSCCTL_DISABLE) {
- mutex_unlock(&dev_priv->sb_lock);
- return 0;
- }
-
- temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
- divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
- SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
- phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
- SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
-
- temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
- auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
- SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
-
- mutex_unlock(&dev_priv->sb_lock);
-
- desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
-
- return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
- desired_divisor << auxdiv);
-}
static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
enum pipe pch_transcoder)
@@ -4299,414 +4172,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
return ret;
}
-static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
-{
- struct intel_encoder *encoder;
- int i;
- u32 val, final;
- bool has_lvds = false;
- bool has_cpu_edp = false;
- bool has_panel = false;
- bool has_ck505 = false;
- bool can_ssc = false;
- bool using_ssc_source = false;
-
- /* We need to take the global config into account */
- for_each_intel_encoder(&dev_priv->drm, encoder) {
- switch (encoder->type) {
- case INTEL_OUTPUT_LVDS:
- has_panel = true;
- has_lvds = true;
- break;
- case INTEL_OUTPUT_EDP:
- has_panel = true;
- if (encoder->port == PORT_A)
- has_cpu_edp = true;
- break;
- default:
- break;
- }
- }
-
- if (HAS_PCH_IBX(dev_priv)) {
- has_ck505 = dev_priv->vbt.display_clock_mode;
- can_ssc = has_ck505;
- } else {
- has_ck505 = false;
- can_ssc = true;
- }
-
- /* Check if any DPLLs are using the SSC source */
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
- u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
-
- if (!(temp & DPLL_VCO_ENABLE))
- continue;
-
- if ((temp & PLL_REF_INPUT_MASK) ==
- PLLB_REF_INPUT_SPREADSPECTRUMIN) {
- using_ssc_source = true;
- break;
- }
- }
-
- drm_dbg_kms(&dev_priv->drm,
- "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
- has_panel, has_lvds, has_ck505, using_ssc_source);
-
- /* Ironlake: try to setup display ref clock before DPLL
- * enabling. This is only under driver's control after
- * PCH B stepping, previous chipset stepping should be
- * ignoring this setting.
- */
- val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
-
- /* As we must carefully and slowly disable/enable each source in turn,
- * compute the final state we want first and check if we need to
- * make any changes at all.
- */
- final = val;
- final &= ~DREF_NONSPREAD_SOURCE_MASK;
- if (has_ck505)
- final |= DREF_NONSPREAD_CK505_ENABLE;
- else
- final |= DREF_NONSPREAD_SOURCE_ENABLE;
-
- final &= ~DREF_SSC_SOURCE_MASK;
- final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
- final &= ~DREF_SSC1_ENABLE;
-
- if (has_panel) {
- final |= DREF_SSC_SOURCE_ENABLE;
-
- if (intel_panel_use_ssc(dev_priv) && can_ssc)
- final |= DREF_SSC1_ENABLE;
-
- if (has_cpu_edp) {
- if (intel_panel_use_ssc(dev_priv) && can_ssc)
- final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
- else
- final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
- } else
- final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
- } else if (using_ssc_source) {
- final |= DREF_SSC_SOURCE_ENABLE;
- final |= DREF_SSC1_ENABLE;
- }
-
- if (final == val)
- return;
-
- /* Always enable nonspread source */
- val &= ~DREF_NONSPREAD_SOURCE_MASK;
-
- if (has_ck505)
- val |= DREF_NONSPREAD_CK505_ENABLE;
- else
- val |= DREF_NONSPREAD_SOURCE_ENABLE;
-
- if (has_panel) {
- val &= ~DREF_SSC_SOURCE_MASK;
- val |= DREF_SSC_SOURCE_ENABLE;
-
- /* SSC must be turned on before enabling the CPU output */
- if (intel_panel_use_ssc(dev_priv) && can_ssc) {
- drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
- val |= DREF_SSC1_ENABLE;
- } else
- val &= ~DREF_SSC1_ENABLE;
-
- /* Get SSC going before enabling the outputs */
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
- udelay(200);
-
- val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
-
- /* Enable CPU source on CPU attached eDP */
- if (has_cpu_edp) {
- if (intel_panel_use_ssc(dev_priv) && can_ssc) {
- drm_dbg_kms(&dev_priv->drm,
- "Using SSC on eDP\n");
- val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
- } else
- val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
- } else
- val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
-
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
- udelay(200);
- } else {
- drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
-
- val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
-
- /* Turn off CPU output */
- val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
-
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
- udelay(200);
-
- if (!using_ssc_source) {
- drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
-
- /* Turn off the SSC source */
- val &= ~DREF_SSC_SOURCE_MASK;
- val |= DREF_SSC_SOURCE_DISABLE;
-
- /* Turn off SSC1 */
- val &= ~DREF_SSC1_ENABLE;
-
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
- udelay(200);
- }
- }
-
- BUG_ON(val != final);
-}
-
-/* Implements 3 different sequences from BSpec chapter "Display iCLK
- * Programming" based on the parameters passed:
- * - Sequence to enable CLKOUT_DP
- * - Sequence to enable CLKOUT_DP without spread
- * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
- */
-static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
- bool with_spread, bool with_fdi)
-{
- u32 reg, tmp;
-
- if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
- "FDI requires downspread\n"))
- with_spread = true;
- if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
- with_fdi, "LP PCH doesn't have FDI\n"))
- with_fdi = false;
-
- mutex_lock(&dev_priv->sb_lock);
-
- tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
- tmp &= ~SBI_SSCCTL_DISABLE;
- tmp |= SBI_SSCCTL_PATHALT;
- intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
-
- udelay(24);
-
- if (with_spread) {
- tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
- tmp &= ~SBI_SSCCTL_PATHALT;
- intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
-
- if (with_fdi)
- lpt_fdi_program_mphy(dev_priv);
- }
-
- reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
- tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
- tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
- intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
-
- mutex_unlock(&dev_priv->sb_lock);
-}
-
-/* Sequence to disable CLKOUT_DP */
-void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
-{
- u32 reg, tmp;
-
- mutex_lock(&dev_priv->sb_lock);
-
- reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
- tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
- tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
- intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
-
- tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
- if (!(tmp & SBI_SSCCTL_DISABLE)) {
- if (!(tmp & SBI_SSCCTL_PATHALT)) {
- tmp |= SBI_SSCCTL_PATHALT;
- intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
- udelay(32);
- }
- tmp |= SBI_SSCCTL_DISABLE;
- intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
- }
-
- mutex_unlock(&dev_priv->sb_lock);
-}
-
-#define BEND_IDX(steps) ((50 + (steps)) / 5)
-
-static const u16 sscdivintphase[] = {
- [BEND_IDX( 50)] = 0x3B23,
- [BEND_IDX( 45)] = 0x3B23,
- [BEND_IDX( 40)] = 0x3C23,
- [BEND_IDX( 35)] = 0x3C23,
- [BEND_IDX( 30)] = 0x3D23,
- [BEND_IDX( 25)] = 0x3D23,
- [BEND_IDX( 20)] = 0x3E23,
- [BEND_IDX( 15)] = 0x3E23,
- [BEND_IDX( 10)] = 0x3F23,
- [BEND_IDX( 5)] = 0x3F23,
- [BEND_IDX( 0)] = 0x0025,
- [BEND_IDX( -5)] = 0x0025,
- [BEND_IDX(-10)] = 0x0125,
- [BEND_IDX(-15)] = 0x0125,
- [BEND_IDX(-20)] = 0x0225,
- [BEND_IDX(-25)] = 0x0225,
- [BEND_IDX(-30)] = 0x0325,
- [BEND_IDX(-35)] = 0x0325,
- [BEND_IDX(-40)] = 0x0425,
- [BEND_IDX(-45)] = 0x0425,
- [BEND_IDX(-50)] = 0x0525,
-};
-
-/*
- * Bend CLKOUT_DP
- * steps -50 to 50 inclusive, in steps of 5
- * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
- * change in clock period = -(steps / 10) * 5.787 ps
- */
-static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
-{
- u32 tmp;
- int idx = BEND_IDX(steps);
-
- if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
- return;
-
- if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
- return;
-
- mutex_lock(&dev_priv->sb_lock);
-
- if (steps % 10 != 0)
- tmp = 0xAAAAAAAB;
- else
- tmp = 0x00000000;
- intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
-
- tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
- tmp &= 0xffff0000;
- tmp |= sscdivintphase[idx];
- intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
-
- mutex_unlock(&dev_priv->sb_lock);
-}
-
-#undef BEND_IDX
-
-static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
-{
- u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
- u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
-
- if ((ctl & SPLL_PLL_ENABLE) == 0)
- return false;
-
- if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
- (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
- return true;
-
- if (IS_BROADWELL(dev_priv) &&
- (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
- return true;
-
- return false;
-}
-
-static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
- enum intel_dpll_id id)
-{
- u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
- u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
-
- if ((ctl & WRPLL_PLL_ENABLE) == 0)
- return false;
-
- if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
- return true;
-
- if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
- (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
- (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
- return true;
-
- return false;
-}
-
-static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
-{
- struct intel_encoder *encoder;
- bool has_fdi = false;
-
- for_each_intel_encoder(&dev_priv->drm, encoder) {
- switch (encoder->type) {
- case INTEL_OUTPUT_ANALOG:
- has_fdi = true;
- break;
- default:
- break;
- }
- }
-
- /*
- * The BIOS may have decided to use the PCH SSC
- * reference so we must not disable it until the
- * relevant PLLs have stopped relying on it. We'll
- * just leave the PCH SSC reference enabled in case
- * any active PLL is using it. It will get disabled
- * after runtime suspend if we don't have FDI.
- *
- * TODO: Move the whole reference clock handling
- * to the modeset sequence proper so that we can
- * actually enable/disable/reconfigure these things
- * safely. To do that we need to introduce a real
- * clock hierarchy. That would also allow us to do
- * clock bending finally.
- */
- dev_priv->pch_ssc_use = 0;
-
- if (spll_uses_pch_ssc(dev_priv)) {
- drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
- dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
- }
-
- if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
- drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
- dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
- }
-
- if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
- drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
- dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
- }
-
- if (dev_priv->pch_ssc_use)
- return;
-
- if (has_fdi) {
- lpt_bend_clkout_dp(dev_priv, 0);
- lpt_enable_clkout_dp(dev_priv, true, true);
- } else {
- lpt_disable_clkout_dp(dev_priv);
- }
-}
-
-/*
- * Initialize reference clocks when the driver loads
- */
-void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
- ilk_init_pch_refclk(dev_priv);
- else if (HAS_PCH_LPT(dev_priv))
- lpt_init_pch_refclk(dev_priv);
-}
-
static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 0c76bf57f86b..39c18b8807f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -521,7 +521,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n, bool fec_enable);
-void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
@@ -544,7 +543,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
const char *name, u32 reg);
void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
-void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
void intel_init_display_hooks(struct drm_i915_private *dev_priv);
unsigned int intel_fb_xy_to_linear(int x, int y,
const struct intel_plane_state *state,
@@ -583,7 +581,6 @@ intel_framebuffer_create(struct drm_i915_gem_object *obj,
void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe);
-int lpt_get_iclkip(struct drm_i915_private *dev_priv);
bool intel_fuzzy_clock_check(int clock1, int clock2);
void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
@@ -632,7 +629,6 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915);
void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
void intel_display_resume(struct drm_device *dev);
-void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
int intel_modeset_all_pipes(struct intel_atomic_state *state);
/* modesetting asserts */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1672604f9ef7..d88da0d0f05a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -15,6 +15,7 @@
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_hotplug.h"
+#include "intel_pch_refclk.h"
#include "intel_pcode.h"
#include "intel_pm.h"
#include "intel_pps.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 0a7e04db04be..ca69b67bbc23 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -26,6 +26,7 @@
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_dpll_mgr.h"
+#include "intel_pch_refclk.h"
#include "intel_tc.h"
/**
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index dd2cf0c59921..d1c1600c66cb 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -8,7 +8,6 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_fdi.h"
-#include "intel_sbi.h"
static void assert_fdi_tx(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state)
@@ -1006,104 +1005,6 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
udelay(100);
}
-static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
-{
- u32 tmp;
-
- tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
- tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
- intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
-
- if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
- FDI_MPHY_IOSFSB_RESET_STATUS, 100))
- drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
-
- tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
- tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
- intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
-
- if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
- FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
- drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
-}
-
-/* WaMPhyProgramming:hsw */
-void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
-{
- u32 tmp;
-
- lpt_fdi_reset_mphy(dev_priv);
-
- tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
- tmp &= ~(0xFF << 24);
- tmp |= (0x12 << 24);
- intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
- tmp |= (1 << 11);
- intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
- tmp |= (1 << 11);
- intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
- tmp |= (1 << 24) | (1 << 21) | (1 << 18);
- intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
- tmp |= (1 << 24) | (1 << 21) | (1 << 18);
- intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
- tmp &= ~(7 << 13);
- tmp |= (5 << 13);
- intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
- tmp &= ~(7 << 13);
- tmp |= (5 << 13);
- intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
- tmp &= ~0xFF;
- tmp |= 0x1C;
- intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
- tmp &= ~0xFF;
- tmp |= 0x1C;
- intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
- tmp &= ~(0xFF << 16);
- tmp |= (0x1C << 16);
- intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
- tmp &= ~(0xFF << 16);
- tmp |= (0x1C << 16);
- intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
- tmp |= (1 << 27);
- intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
- tmp |= (1 << 27);
- intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
- tmp &= ~(0xF << 28);
- tmp |= (4 << 28);
- intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
-
- tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
- tmp &= ~(0xF << 28);
- tmp |= (4 << 28);
- intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
-}
-
static const struct intel_fdi_funcs ilk_funcs = {
.fdi_link_train = ilk_fdi_link_train,
};
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
index 640d6585c137..5a361730f80a 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -24,7 +24,6 @@ void intel_fdi_init_hook(struct drm_i915_private *dev_priv);
void hsw_fdi_link_train(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
-void lpt_fdi_program_mphy(struct drm_i915_private *i915);
void intel_fdi_link_train(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
new file mode 100644
index 000000000000..b688fd87e3da
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -0,0 +1,648 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_panel.h"
+#include "intel_pch_refclk.h"
+#include "intel_sbi.h"
+
+static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
+{
+ u32 tmp;
+
+ tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
+ tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
+ intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
+
+ if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
+ FDI_MPHY_IOSFSB_RESET_STATUS, 100))
+ drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
+
+ tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
+ tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
+ intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
+
+ if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
+ FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
+ drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
+}
+
+/* WaMPhyProgramming:hsw */
+static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
+{
+ u32 tmp;
+
+ lpt_fdi_reset_mphy(dev_priv);
+
+ tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
+ tmp &= ~(0xFF << 24);
+ tmp |= (0x12 << 24);
+ intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
+ tmp |= (1 << 11);
+ intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
+ tmp |= (1 << 11);
+ intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
+ tmp |= (1 << 24) | (1 << 21) | (1 << 18);
+ intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
+ tmp |= (1 << 24) | (1 << 21) | (1 << 18);
+ intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
+ tmp &= ~(7 << 13);
+ tmp |= (5 << 13);
+ intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
+ tmp &= ~(7 << 13);
+ tmp |= (5 << 13);
+ intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
+ tmp &= ~0xFF;
+ tmp |= 0x1C;
+ intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
+ tmp &= ~0xFF;
+ tmp |= 0x1C;
+ intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
+ tmp &= ~(0xFF << 16);
+ tmp |= (0x1C << 16);
+ intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
+ tmp &= ~(0xFF << 16);
+ tmp |= (0x1C << 16);
+ intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
+ tmp |= (1 << 27);
+ intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
+ tmp |= (1 << 27);
+ intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
+ tmp &= ~(0xF << 28);
+ tmp |= (4 << 28);
+ intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
+
+ tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
+ tmp &= ~(0xF << 28);
+ tmp |= (4 << 28);
+ intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
+}
+
+void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
+{
+ u32 temp;
+
+ intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
+ temp |= SBI_SSCCTL_DISABLE;
+ intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
+
+ mutex_unlock(&dev_priv->sb_lock);
+}
+
+/* Program iCLKIP clock to the desired frequency */
+void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int clock = crtc_state->hw.adjusted_mode.crtc_clock;
+ u32 divsel, phaseinc, auxdiv, phasedir = 0;
+ u32 temp;
+
+ lpt_disable_iclkip(dev_priv);
+
+ /* The iCLK virtual clock root frequency is in MHz,
+ * but the adjusted_mode->crtc_clock in KHz. To get the
+ * divisors, it is necessary to divide one by another, so we
+ * convert the virtual clock precision to KHz here for higher
+ * precision.
+ */
+ for (auxdiv = 0; auxdiv < 2; auxdiv++) {
+ u32 iclk_virtual_root_freq = 172800 * 1000;
+ u32 iclk_pi_range = 64;
+ u32 desired_divisor;
+
+ desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
+ clock << auxdiv);
+ divsel = (desired_divisor / iclk_pi_range) - 2;
+ phaseinc = desired_divisor % iclk_pi_range;
+
+ /*
+ * Near 20MHz is a corner case which is
+ * out of range for the 7-bit divisor
+ */
+ if (divsel <= 0x7f)
+ break;
+ }
+
+ /* This should not happen with any sane values */
+ drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
+ ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
+ drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
+ ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
+ clock, auxdiv, divsel, phasedir, phaseinc);
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ /* Program SSCDIVINTPHASE6 */
+ temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
+ temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
+ temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
+ temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
+ temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
+ temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
+ temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
+ intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
+
+ /* Program SSCAUXDIV */
+ temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
+ temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
+ temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
+ intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
+
+ /* Enable modulator and associated divider */
+ temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
+ temp &= ~SBI_SSCCTL_DISABLE;
+ intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
+
+ mutex_unlock(&dev_priv->sb_lock);
+
+ /* Wait for initialization time */
+ udelay(24);
+
+ intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
+}
+
+int lpt_get_iclkip(struct drm_i915_private *dev_priv)
+{
+ u32 divsel, phaseinc, auxdiv;
+ u32 iclk_virtual_root_freq = 172800 * 1000;
+ u32 iclk_pi_range = 64;
+ u32 desired_divisor;
+ u32 temp;
+
+ if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
+ return 0;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
+ if (temp & SBI_SSCCTL_DISABLE) {
+ mutex_unlock(&dev_priv->sb_lock);
+ return 0;
+ }
+
+ temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
+ divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
+ SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
+ phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
+ SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
+
+ temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
+ auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
+ SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
+
+ mutex_unlock(&dev_priv->sb_lock);
+
+ desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
+
+ return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
+ desired_divisor << auxdiv);
+}
+
+/* Implements 3 different sequences from BSpec chapter "Display iCLK
+ * Programming" based on the parameters passed:
+ * - Sequence to enable CLKOUT_DP
+ * - Sequence to enable CLKOUT_DP without spread
+ * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
+ */
+static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
+ bool with_spread, bool with_fdi)
+{
+ u32 reg, tmp;
+
+ if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
+ "FDI requires downspread\n"))
+ with_spread = true;
+ if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
+ with_fdi, "LP PCH doesn't have FDI\n"))
+ with_fdi = false;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
+ tmp &= ~SBI_SSCCTL_DISABLE;
+ tmp |= SBI_SSCCTL_PATHALT;
+ intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+
+ udelay(24);
+
+ if (with_spread) {
+ tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
+ tmp &= ~SBI_SSCCTL_PATHALT;
+ intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+
+ if (with_fdi)
+ lpt_fdi_program_mphy(dev_priv);
+ }
+
+ reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
+ tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
+ tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
+ intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
+
+ mutex_unlock(&dev_priv->sb_lock);
+}
+
+/* Sequence to disable CLKOUT_DP */
+void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
+{
+ u32 reg, tmp;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
+ tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
+ tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
+ intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
+
+ tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
+ if (!(tmp & SBI_SSCCTL_DISABLE)) {
+ if (!(tmp & SBI_SSCCTL_PATHALT)) {
+ tmp |= SBI_SSCCTL_PATHALT;
+ intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+ udelay(32);
+ }
+ tmp |= SBI_SSCCTL_DISABLE;
+ intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+ }
+
+ mutex_unlock(&dev_priv->sb_lock);
+}
+
+#define BEND_IDX(steps) ((50 + (steps)) / 5)
+
+static const u16 sscdivintphase[] = {
+ [BEND_IDX( 50)] = 0x3B23,
+ [BEND_IDX( 45)] = 0x3B23,
+ [BEND_IDX( 40)] = 0x3C23,
+ [BEND_IDX( 35)] = 0x3C23,
+ [BEND_IDX( 30)] = 0x3D23,
+ [BEND_IDX( 25)] = 0x3D23,
+ [BEND_IDX( 20)] = 0x3E23,
+ [BEND_IDX( 15)] = 0x3E23,
+ [BEND_IDX( 10)] = 0x3F23,
+ [BEND_IDX( 5)] = 0x3F23,
+ [BEND_IDX( 0)] = 0x0025,
+ [BEND_IDX( -5)] = 0x0025,
+ [BEND_IDX(-10)] = 0x0125,
+ [BEND_IDX(-15)] = 0x0125,
+ [BEND_IDX(-20)] = 0x0225,
+ [BEND_IDX(-25)] = 0x0225,
+ [BEND_IDX(-30)] = 0x0325,
+ [BEND_IDX(-35)] = 0x0325,
+ [BEND_IDX(-40)] = 0x0425,
+ [BEND_IDX(-45)] = 0x0425,
+ [BEND_IDX(-50)] = 0x0525,
+};
+
+/*
+ * Bend CLKOUT_DP
+ * steps -50 to 50 inclusive, in steps of 5
+ * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
+ * change in clock period = -(steps / 10) * 5.787 ps
+ */
+static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
+{
+ u32 tmp;
+ int idx = BEND_IDX(steps);
+
+ if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
+ return;
+
+ if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
+ return;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ if (steps % 10 != 0)
+ tmp = 0xAAAAAAAB;
+ else
+ tmp = 0x00000000;
+ intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
+
+ tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
+ tmp &= 0xffff0000;
+ tmp |= sscdivintphase[idx];
+ intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
+
+ mutex_unlock(&dev_priv->sb_lock);
+}
+
+#undef BEND_IDX
+
+static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
+{
+ u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
+ u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
+
+ if ((ctl & SPLL_PLL_ENABLE) == 0)
+ return false;
+
+ if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
+ (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
+ return true;
+
+ if (IS_BROADWELL(dev_priv) &&
+ (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
+ return true;
+
+ return false;
+}
+
+static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
+ enum intel_dpll_id id)
+{
+ u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
+ u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
+
+ if ((ctl & WRPLL_PLL_ENABLE) == 0)
+ return false;
+
+ if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
+ return true;
+
+ if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
+ (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
+ (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
+ return true;
+
+ return false;
+}
+
+static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
+{
+ struct intel_encoder *encoder;
+ bool has_fdi = false;
+
+ for_each_intel_encoder(&dev_priv->drm, encoder) {
+ switch (encoder->type) {
+ case INTEL_OUTPUT_ANALOG:
+ has_fdi = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /*
+ * The BIOS may have decided to use the PCH SSC
+ * reference so we must not disable it until the
+ * relevant PLLs have stopped relying on it. We'll
+ * just leave the PCH SSC reference enabled in case
+ * any active PLL is using it. It will get disabled
+ * after runtime suspend if we don't have FDI.
+ *
+ * TODO: Move the whole reference clock handling
+ * to the modeset sequence proper so that we can
+ * actually enable/disable/reconfigure these things
+ * safely. To do that we need to introduce a real
+ * clock hierarchy. That would also allow us to do
+ * clock bending finally.
+ */
+ dev_priv->pch_ssc_use = 0;
+
+ if (spll_uses_pch_ssc(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
+ dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
+ }
+
+ if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
+ drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
+ dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
+ }
+
+ if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
+ drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
+ dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
+ }
+
+ if (dev_priv->pch_ssc_use)
+ return;
+
+ if (has_fdi) {
+ lpt_bend_clkout_dp(dev_priv, 0);
+ lpt_enable_clkout_dp(dev_priv, true, true);
+ } else {
+ lpt_disable_clkout_dp(dev_priv);
+ }
+}
+
+static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
+{
+ struct intel_encoder *encoder;
+ int i;
+ u32 val, final;
+ bool has_lvds = false;
+ bool has_cpu_edp = false;
+ bool has_panel = false;
+ bool has_ck505 = false;
+ bool can_ssc = false;
+ bool using_ssc_source = false;
+
+ /* We need to take the global config into account */
+ for_each_intel_encoder(&dev_priv->drm, encoder) {
+ switch (encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+ has_panel = true;
+ has_lvds = true;
+ break;
+ case INTEL_OUTPUT_EDP:
+ has_panel = true;
+ if (encoder->port == PORT_A)
+ has_cpu_edp = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (HAS_PCH_IBX(dev_priv)) {
+ has_ck505 = dev_priv->vbt.display_clock_mode;
+ can_ssc = has_ck505;
+ } else {
+ has_ck505 = false;
+ can_ssc = true;
+ }
+
+ /* Check if any DPLLs are using the SSC source */
+ for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
+ u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
+
+ if (!(temp & DPLL_VCO_ENABLE))
+ continue;
+
+ if ((temp & PLL_REF_INPUT_MASK) ==
+ PLLB_REF_INPUT_SPREADSPECTRUMIN) {
+ using_ssc_source = true;
+ break;
+ }
+ }
+
+ drm_dbg_kms(&dev_priv->drm,
+ "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
+ has_panel, has_lvds, has_ck505, using_ssc_source);
+
+ /* Ironlake: try to setup display ref clock before DPLL
+ * enabling. This is only under driver's control after
+ * PCH B stepping, previous chipset stepping should be
+ * ignoring this setting.
+ */
+ val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
+
+ /* As we must carefully and slowly disable/enable each source in turn,
+ * compute the final state we want first and check if we need to
+ * make any changes at all.
+ */
+ final = val;
+ final &= ~DREF_NONSPREAD_SOURCE_MASK;
+ if (has_ck505)
+ final |= DREF_NONSPREAD_CK505_ENABLE;
+ else
+ final |= DREF_NONSPREAD_SOURCE_ENABLE;
+
+ final &= ~DREF_SSC_SOURCE_MASK;
+ final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+ final &= ~DREF_SSC1_ENABLE;
+
+ if (has_panel) {
+ final |= DREF_SSC_SOURCE_ENABLE;
+
+ if (intel_panel_use_ssc(dev_priv) && can_ssc)
+ final |= DREF_SSC1_ENABLE;
+
+ if (has_cpu_edp) {
+ if (intel_panel_use_ssc(dev_priv) && can_ssc)
+ final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+ else
+ final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ } else {
+ final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ }
+ } else if (using_ssc_source) {
+ final |= DREF_SSC_SOURCE_ENABLE;
+ final |= DREF_SSC1_ENABLE;
+ }
+
+ if (final == val)
+ return;
+
+ /* Always enable nonspread source */
+ val &= ~DREF_NONSPREAD_SOURCE_MASK;
+
+ if (has_ck505)
+ val |= DREF_NONSPREAD_CK505_ENABLE;
+ else
+ val |= DREF_NONSPREAD_SOURCE_ENABLE;
+
+ if (has_panel) {
+ val &= ~DREF_SSC_SOURCE_MASK;
+ val |= DREF_SSC_SOURCE_ENABLE;
+
+ /* SSC must be turned on before enabling the CPU output */
+ if (intel_panel_use_ssc(dev_priv) && can_ssc) {
+ drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
+ val |= DREF_SSC1_ENABLE;
+ } else {
+ val &= ~DREF_SSC1_ENABLE;
+ }
+
+ /* Get SSC going before enabling the outputs */
+ intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ udelay(200);
+
+ val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+
+ /* Enable CPU source on CPU attached eDP */
+ if (has_cpu_edp) {
+ if (intel_panel_use_ssc(dev_priv) && can_ssc) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Using SSC on eDP\n");
+ val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+ } else {
+ val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ }
+ } else {
+ val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ }
+
+ intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ udelay(200);
+ } else {
+ drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
+
+ val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+
+ /* Turn off CPU output */
+ val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+
+ intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ udelay(200);
+
+ if (!using_ssc_source) {
+ drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
+
+ /* Turn off the SSC source */
+ val &= ~DREF_SSC_SOURCE_MASK;
+ val |= DREF_SSC_SOURCE_DISABLE;
+
+ /* Turn off SSC1 */
+ val &= ~DREF_SSC1_ENABLE;
+
+ intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ udelay(200);
+ }
+ }
+
+ BUG_ON(val != final);
+}
+
+/*
+ * Initialize reference clocks when the driver loads
+ */
+void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
+{
+ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
+ ilk_init_pch_refclk(dev_priv);
+ else if (HAS_PCH_LPT(dev_priv))
+ lpt_init_pch_refclk(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
new file mode 100644
index 000000000000..12ab2c75a800
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_PCH_REFCLK_H_
+#define _INTEL_PCH_REFCLK_H_
+
+#include <linux/types.h>
+
+struct drm_i915_private;
+struct intel_crtc_state;
+
+void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);
+void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
+int lpt_get_iclkip(struct drm_i915_private *dev_priv);
+
+void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
+void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b18a250e5d2e..1e5b75ae9932 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -54,6 +54,7 @@
#include "display/intel_fbdev.h"
#include "display/intel_hotplug.h"
#include "display/intel_overlay.h"
+#include "display/intel_pch_refclk.h"
#include "display/intel_pipe_crc.h"
#include "display/intel_pps.h"
#include "display/intel_sprite.h"
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 1/9] drm/i915: Move PCH refclok stuff into its own file
2021-10-15 7:16 ` [Intel-gfx] [PATCH 1/9] drm/i915: Move PCH refclok stuff " Ville Syrjala
@ 2021-10-17 23:56 ` David Airlie
2021-10-18 8:13 ` Ville Syrjälä
0 siblings, 1 reply; 39+ messages in thread
From: David Airlie @ 2021-10-17 23:56 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the PCH refclk stuff (including all the LPT/WPT
> iCLKIP/CLKOUT_DP things) to its own file.
>
> We also suck in the mPHY programming from intel_fdi.c
> since we're the only caller.
The title of the patch has a typo refclok->reclock.
Other than that this looks fine,
Reviewed-by: Dave Airlie <airlied@redhat.com>
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 537 +--------------
> drivers/gpu/drm/i915/display/intel_display.h | 4 -
> .../drm/i915/display/intel_display_power.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
> drivers/gpu/drm/i915/display/intel_fdi.c | 99 ---
> drivers/gpu/drm/i915/display/intel_fdi.h | 1 -
> .../gpu/drm/i915/display/intel_pch_refclk.c | 648 ++++++++++++++++++
> .../gpu/drm/i915/display/intel_pch_refclk.h | 21 +
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> 11 files changed, 675 insertions(+), 640 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pch_refclk.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pch_refclk.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 660bb03de6fc..96f3b8f6c50d 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -226,6 +226,7 @@ i915-y += \
> display/intel_hotplug.o \
> display/intel_lpe_audio.o \
> display/intel_overlay.o \
> + display/intel_pch_refclk.o \
> display/intel_plane_initial.o \
> display/intel_psr.o \
> display/intel_quirks.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 1c161eeed82f..bf03bd0ecd43 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -45,6 +45,7 @@
> #include "intel_fifo_underrun.h"
> #include "intel_gmbus.h"
> #include "intel_hotplug.h"
> +#include "intel_pch_refclk.h"
>
> /* Here's the desired hotplug mode */
> #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ff598b6cd953..995050443065 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -96,6 +96,7 @@
> #include "intel_hotplug.h"
> #include "intel_overlay.h"
> #include "intel_panel.h"
> +#include "intel_pch_refclk.h"
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
> @@ -103,7 +104,6 @@
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_quirks.h"
> -#include "intel_sbi.h"
> #include "intel_sprite.h"
> #include "intel_tc.h"
> #include "intel_vga.h"
> @@ -1388,133 +1388,6 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
> return false;
> }
>
> -void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
> -{
> - u32 temp;
> -
> - intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> - temp |= SBI_SSCCTL_DISABLE;
> - intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
> -
> - mutex_unlock(&dev_priv->sb_lock);
> -}
> -
> -/* Program iCLKIP clock to the desired frequency */
> -static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> - u32 divsel, phaseinc, auxdiv, phasedir = 0;
> - u32 temp;
> -
> - lpt_disable_iclkip(dev_priv);
> -
> - /* The iCLK virtual clock root frequency is in MHz,
> - * but the adjusted_mode->crtc_clock in in KHz. To get the
> - * divisors, it is necessary to divide one by another, so we
> - * convert the virtual clock precision to KHz here for higher
> - * precision.
> - */
> - for (auxdiv = 0; auxdiv < 2; auxdiv++) {
> - u32 iclk_virtual_root_freq = 172800 * 1000;
> - u32 iclk_pi_range = 64;
> - u32 desired_divisor;
> -
> - desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> - clock << auxdiv);
> - divsel = (desired_divisor / iclk_pi_range) - 2;
> - phaseinc = desired_divisor % iclk_pi_range;
> -
> - /*
> - * Near 20MHz is a corner case which is
> - * out of range for the 7-bit divisor
> - */
> - if (divsel <= 0x7f)
> - break;
> - }
> -
> - /* This should not happen with any sane values */
> - drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
> - ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
> - drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
> - ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
> - clock, auxdiv, divsel, phasedir, phaseinc);
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - /* Program SSCDIVINTPHASE6 */
> - temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
> - temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
> - temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
> - temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
> - temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
> - temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
> - temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
> - intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
> -
> - /* Program SSCAUXDIV */
> - temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
> - temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
> - temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
> - intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
> -
> - /* Enable modulator and associated divider */
> - temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> - temp &= ~SBI_SSCCTL_DISABLE;
> - intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
> -
> - mutex_unlock(&dev_priv->sb_lock);
> -
> - /* Wait for initialization time */
> - udelay(24);
> -
> - intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
> -}
> -
> -int lpt_get_iclkip(struct drm_i915_private *dev_priv)
> -{
> - u32 divsel, phaseinc, auxdiv;
> - u32 iclk_virtual_root_freq = 172800 * 1000;
> - u32 iclk_pi_range = 64;
> - u32 desired_divisor;
> - u32 temp;
> -
> - if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
> - return 0;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> - if (temp & SBI_SSCCTL_DISABLE) {
> - mutex_unlock(&dev_priv->sb_lock);
> - return 0;
> - }
> -
> - temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
> - divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
> - SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
> - phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
> - SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
> -
> - temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
> - auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
> - SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
> -
> - mutex_unlock(&dev_priv->sb_lock);
> -
> - desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
> -
> - return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> - desired_divisor << auxdiv);
> -}
>
> static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
> enum pipe pch_transcoder)
> @@ -4299,414 +4172,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> return ret;
> }
>
> -static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> -{
> - struct intel_encoder *encoder;
> - int i;
> - u32 val, final;
> - bool has_lvds = false;
> - bool has_cpu_edp = false;
> - bool has_panel = false;
> - bool has_ck505 = false;
> - bool can_ssc = false;
> - bool using_ssc_source = false;
> -
> - /* We need to take the global config into account */
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> - switch (encoder->type) {
> - case INTEL_OUTPUT_LVDS:
> - has_panel = true;
> - has_lvds = true;
> - break;
> - case INTEL_OUTPUT_EDP:
> - has_panel = true;
> - if (encoder->port == PORT_A)
> - has_cpu_edp = true;
> - break;
> - default:
> - break;
> - }
> - }
> -
> - if (HAS_PCH_IBX(dev_priv)) {
> - has_ck505 = dev_priv->vbt.display_clock_mode;
> - can_ssc = has_ck505;
> - } else {
> - has_ck505 = false;
> - can_ssc = true;
> - }
> -
> - /* Check if any DPLLs are using the SSC source */
> - for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
> - u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
> -
> - if (!(temp & DPLL_VCO_ENABLE))
> - continue;
> -
> - if ((temp & PLL_REF_INPUT_MASK) ==
> - PLLB_REF_INPUT_SPREADSPECTRUMIN) {
> - using_ssc_source = true;
> - break;
> - }
> - }
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
> - has_panel, has_lvds, has_ck505, using_ssc_source);
> -
> - /* Ironlake: try to setup display ref clock before DPLL
> - * enabling. This is only under driver's control after
> - * PCH B stepping, previous chipset stepping should be
> - * ignoring this setting.
> - */
> - val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
> -
> - /* As we must carefully and slowly disable/enable each source in turn,
> - * compute the final state we want first and check if we need to
> - * make any changes at all.
> - */
> - final = val;
> - final &= ~DREF_NONSPREAD_SOURCE_MASK;
> - if (has_ck505)
> - final |= DREF_NONSPREAD_CK505_ENABLE;
> - else
> - final |= DREF_NONSPREAD_SOURCE_ENABLE;
> -
> - final &= ~DREF_SSC_SOURCE_MASK;
> - final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> - final &= ~DREF_SSC1_ENABLE;
> -
> - if (has_panel) {
> - final |= DREF_SSC_SOURCE_ENABLE;
> -
> - if (intel_panel_use_ssc(dev_priv) && can_ssc)
> - final |= DREF_SSC1_ENABLE;
> -
> - if (has_cpu_edp) {
> - if (intel_panel_use_ssc(dev_priv) && can_ssc)
> - final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
> - else
> - final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> - } else
> - final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
> - } else if (using_ssc_source) {
> - final |= DREF_SSC_SOURCE_ENABLE;
> - final |= DREF_SSC1_ENABLE;
> - }
> -
> - if (final == val)
> - return;
> -
> - /* Always enable nonspread source */
> - val &= ~DREF_NONSPREAD_SOURCE_MASK;
> -
> - if (has_ck505)
> - val |= DREF_NONSPREAD_CK505_ENABLE;
> - else
> - val |= DREF_NONSPREAD_SOURCE_ENABLE;
> -
> - if (has_panel) {
> - val &= ~DREF_SSC_SOURCE_MASK;
> - val |= DREF_SSC_SOURCE_ENABLE;
> -
> - /* SSC must be turned on before enabling the CPU output */
> - if (intel_panel_use_ssc(dev_priv) && can_ssc) {
> - drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
> - val |= DREF_SSC1_ENABLE;
> - } else
> - val &= ~DREF_SSC1_ENABLE;
> -
> - /* Get SSC going before enabling the outputs */
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> - udelay(200);
> -
> - val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> -
> - /* Enable CPU source on CPU attached eDP */
> - if (has_cpu_edp) {
> - if (intel_panel_use_ssc(dev_priv) && can_ssc) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Using SSC on eDP\n");
> - val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
> - } else
> - val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> - } else
> - val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
> -
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> - udelay(200);
> - } else {
> - drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
> -
> - val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> -
> - /* Turn off CPU output */
> - val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
> -
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> - udelay(200);
> -
> - if (!using_ssc_source) {
> - drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
> -
> - /* Turn off the SSC source */
> - val &= ~DREF_SSC_SOURCE_MASK;
> - val |= DREF_SSC_SOURCE_DISABLE;
> -
> - /* Turn off SSC1 */
> - val &= ~DREF_SSC1_ENABLE;
> -
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> - udelay(200);
> - }
> - }
> -
> - BUG_ON(val != final);
> -}
> -
> -/* Implements 3 different sequences from BSpec chapter "Display iCLK
> - * Programming" based on the parameters passed:
> - * - Sequence to enable CLKOUT_DP
> - * - Sequence to enable CLKOUT_DP without spread
> - * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
> - */
> -static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
> - bool with_spread, bool with_fdi)
> -{
> - u32 reg, tmp;
> -
> - if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
> - "FDI requires downspread\n"))
> - with_spread = true;
> - if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
> - with_fdi, "LP PCH doesn't have FDI\n"))
> - with_fdi = false;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> - tmp &= ~SBI_SSCCTL_DISABLE;
> - tmp |= SBI_SSCCTL_PATHALT;
> - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> -
> - udelay(24);
> -
> - if (with_spread) {
> - tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> - tmp &= ~SBI_SSCCTL_PATHALT;
> - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> -
> - if (with_fdi)
> - lpt_fdi_program_mphy(dev_priv);
> - }
> -
> - reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> - tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> - tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> - intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> -
> - mutex_unlock(&dev_priv->sb_lock);
> -}
> -
> -/* Sequence to disable CLKOUT_DP */
> -void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
> -{
> - u32 reg, tmp;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> - tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> - tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> - intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> -
> - tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> - if (!(tmp & SBI_SSCCTL_DISABLE)) {
> - if (!(tmp & SBI_SSCCTL_PATHALT)) {
> - tmp |= SBI_SSCCTL_PATHALT;
> - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> - udelay(32);
> - }
> - tmp |= SBI_SSCCTL_DISABLE;
> - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> - }
> -
> - mutex_unlock(&dev_priv->sb_lock);
> -}
> -
> -#define BEND_IDX(steps) ((50 + (steps)) / 5)
> -
> -static const u16 sscdivintphase[] = {
> - [BEND_IDX( 50)] = 0x3B23,
> - [BEND_IDX( 45)] = 0x3B23,
> - [BEND_IDX( 40)] = 0x3C23,
> - [BEND_IDX( 35)] = 0x3C23,
> - [BEND_IDX( 30)] = 0x3D23,
> - [BEND_IDX( 25)] = 0x3D23,
> - [BEND_IDX( 20)] = 0x3E23,
> - [BEND_IDX( 15)] = 0x3E23,
> - [BEND_IDX( 10)] = 0x3F23,
> - [BEND_IDX( 5)] = 0x3F23,
> - [BEND_IDX( 0)] = 0x0025,
> - [BEND_IDX( -5)] = 0x0025,
> - [BEND_IDX(-10)] = 0x0125,
> - [BEND_IDX(-15)] = 0x0125,
> - [BEND_IDX(-20)] = 0x0225,
> - [BEND_IDX(-25)] = 0x0225,
> - [BEND_IDX(-30)] = 0x0325,
> - [BEND_IDX(-35)] = 0x0325,
> - [BEND_IDX(-40)] = 0x0425,
> - [BEND_IDX(-45)] = 0x0425,
> - [BEND_IDX(-50)] = 0x0525,
> -};
> -
> -/*
> - * Bend CLKOUT_DP
> - * steps -50 to 50 inclusive, in steps of 5
> - * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
> - * change in clock period = -(steps / 10) * 5.787 ps
> - */
> -static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
> -{
> - u32 tmp;
> - int idx = BEND_IDX(steps);
> -
> - if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
> - return;
> -
> - if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
> - return;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - if (steps % 10 != 0)
> - tmp = 0xAAAAAAAB;
> - else
> - tmp = 0x00000000;
> - intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
> -
> - tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
> - tmp &= 0xffff0000;
> - tmp |= sscdivintphase[idx];
> - intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
> -
> - mutex_unlock(&dev_priv->sb_lock);
> -}
> -
> -#undef BEND_IDX
> -
> -static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
> -{
> - u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
> - u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
> -
> - if ((ctl & SPLL_PLL_ENABLE) == 0)
> - return false;
> -
> - if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
> - (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
> - return true;
> -
> - if (IS_BROADWELL(dev_priv) &&
> - (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
> - return true;
> -
> - return false;
> -}
> -
> -static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
> - enum intel_dpll_id id)
> -{
> - u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
> - u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
> -
> - if ((ctl & WRPLL_PLL_ENABLE) == 0)
> - return false;
> -
> - if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
> - return true;
> -
> - if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
> - (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
> - (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
> - return true;
> -
> - return false;
> -}
> -
> -static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
> -{
> - struct intel_encoder *encoder;
> - bool has_fdi = false;
> -
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> - switch (encoder->type) {
> - case INTEL_OUTPUT_ANALOG:
> - has_fdi = true;
> - break;
> - default:
> - break;
> - }
> - }
> -
> - /*
> - * The BIOS may have decided to use the PCH SSC
> - * reference so we must not disable it until the
> - * relevant PLLs have stopped relying on it. We'll
> - * just leave the PCH SSC reference enabled in case
> - * any active PLL is using it. It will get disabled
> - * after runtime suspend if we don't have FDI.
> - *
> - * TODO: Move the whole reference clock handling
> - * to the modeset sequence proper so that we can
> - * actually enable/disable/reconfigure these things
> - * safely. To do that we need to introduce a real
> - * clock hierarchy. That would also allow us to do
> - * clock bending finally.
> - */
> - dev_priv->pch_ssc_use = 0;
> -
> - if (spll_uses_pch_ssc(dev_priv)) {
> - drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
> - dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
> - }
> -
> - if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
> - drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
> - dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
> - }
> -
> - if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
> - drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
> - dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
> - }
> -
> - if (dev_priv->pch_ssc_use)
> - return;
> -
> - if (has_fdi) {
> - lpt_bend_clkout_dp(dev_priv, 0);
> - lpt_enable_clkout_dp(dev_priv, true, true);
> - } else {
> - lpt_disable_clkout_dp(dev_priv);
> - }
> -}
> -
> -/*
> - * Initialize reference clocks when the driver loads
> - */
> -void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
> -{
> - if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> - ilk_init_pch_refclk(dev_priv);
> - else if (HAS_PCH_LPT(dev_priv))
> - lpt_init_pch_refclk(dev_priv);
> -}
> -
> static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 0c76bf57f86b..39c18b8807f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -521,7 +521,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n, bool fec_enable);
> -void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> enum drm_mode_status
> @@ -544,7 +543,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
> const char *name, u32 reg);
> void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
> void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
> -void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
> void intel_init_display_hooks(struct drm_i915_private *dev_priv);
> unsigned int intel_fb_xy_to_linear(int x, int y,
> const struct intel_plane_state *state,
> @@ -583,7 +581,6 @@ intel_framebuffer_create(struct drm_i915_gem_object *obj,
> void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
> enum pipe pipe);
>
> -int lpt_get_iclkip(struct drm_i915_private *dev_priv);
> bool intel_fuzzy_clock_check(int clock1, int clock2);
>
> void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
> @@ -632,7 +629,6 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915);
> void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
> void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
> void intel_display_resume(struct drm_device *dev);
> -void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
> int intel_modeset_all_pipes(struct intel_atomic_state *state);
>
> /* modesetting asserts */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1672604f9ef7..d88da0d0f05a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -15,6 +15,7 @@
> #include "intel_dpio_phy.h"
> #include "intel_dpll.h"
> #include "intel_hotplug.h"
> +#include "intel_pch_refclk.h"
> #include "intel_pcode.h"
> #include "intel_pm.h"
> #include "intel_pps.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 0a7e04db04be..ca69b67bbc23 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -26,6 +26,7 @@
> #include "intel_dpio_phy.h"
> #include "intel_dpll.h"
> #include "intel_dpll_mgr.h"
> +#include "intel_pch_refclk.h"
> #include "intel_tc.h"
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index dd2cf0c59921..d1c1600c66cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -8,7 +8,6 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_fdi.h"
> -#include "intel_sbi.h"
>
> static void assert_fdi_tx(struct drm_i915_private *dev_priv,
> enum pipe pipe, bool state)
> @@ -1006,104 +1005,6 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
> udelay(100);
> }
>
> -static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
> -{
> - u32 tmp;
> -
> - tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
> - tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> - intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
> -
> - if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
> - FDI_MPHY_IOSFSB_RESET_STATUS, 100))
> - drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
> -
> - tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
> - tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> - intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
> -
> - if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
> - FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
> - drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
> -}
> -
> -/* WaMPhyProgramming:hsw */
> -void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
> -{
> - u32 tmp;
> -
> - lpt_fdi_reset_mphy(dev_priv);
> -
> - tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
> - tmp &= ~(0xFF << 24);
> - tmp |= (0x12 << 24);
> - intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
> - tmp |= (1 << 11);
> - intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
> - tmp |= (1 << 11);
> - intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
> - tmp |= (1 << 24) | (1 << 21) | (1 << 18);
> - intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
> - tmp |= (1 << 24) | (1 << 21) | (1 << 18);
> - intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
> - tmp &= ~(7 << 13);
> - tmp |= (5 << 13);
> - intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
> - tmp &= ~(7 << 13);
> - tmp |= (5 << 13);
> - intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
> - tmp &= ~0xFF;
> - tmp |= 0x1C;
> - intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
> - tmp &= ~0xFF;
> - tmp |= 0x1C;
> - intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
> - tmp &= ~(0xFF << 16);
> - tmp |= (0x1C << 16);
> - intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
> - tmp &= ~(0xFF << 16);
> - tmp |= (0x1C << 16);
> - intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
> - tmp |= (1 << 27);
> - intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
> - tmp |= (1 << 27);
> - intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
> - tmp &= ~(0xF << 28);
> - tmp |= (4 << 28);
> - intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
> - tmp &= ~(0xF << 28);
> - tmp |= (4 << 28);
> - intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
> -}
> -
> static const struct intel_fdi_funcs ilk_funcs = {
> .fdi_link_train = ilk_fdi_link_train,
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
> index 640d6585c137..5a361730f80a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.h
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.h
> @@ -24,7 +24,6 @@ void intel_fdi_init_hook(struct drm_i915_private *dev_priv);
> void hsw_fdi_link_train(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
> -void lpt_fdi_program_mphy(struct drm_i915_private *i915);
>
> void intel_fdi_link_train(struct intel_crtc *crtc,
> const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> new file mode 100644
> index 000000000000..b688fd87e3da
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -0,0 +1,648 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "intel_panel.h"
> +#include "intel_pch_refclk.h"
> +#include "intel_sbi.h"
> +
> +static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
> +{
> + u32 tmp;
> +
> + tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
> + tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> + intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
> +
> + if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
> + FDI_MPHY_IOSFSB_RESET_STATUS, 100))
> + drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
> +
> + tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
> + tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> + intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
> +
> + if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
> + FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
> + drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
> +}
> +
> +/* WaMPhyProgramming:hsw */
> +static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
> +{
> + u32 tmp;
> +
> + lpt_fdi_reset_mphy(dev_priv);
> +
> + tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
> + tmp &= ~(0xFF << 24);
> + tmp |= (0x12 << 24);
> + intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
> + tmp |= (1 << 11);
> + intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
> + tmp |= (1 << 11);
> + intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
> + tmp |= (1 << 24) | (1 << 21) | (1 << 18);
> + intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
> + tmp |= (1 << 24) | (1 << 21) | (1 << 18);
> + intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
> + tmp &= ~(7 << 13);
> + tmp |= (5 << 13);
> + intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
> + tmp &= ~(7 << 13);
> + tmp |= (5 << 13);
> + intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
> + tmp &= ~0xFF;
> + tmp |= 0x1C;
> + intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
> + tmp &= ~0xFF;
> + tmp |= 0x1C;
> + intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
> + tmp &= ~(0xFF << 16);
> + tmp |= (0x1C << 16);
> + intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
> + tmp &= ~(0xFF << 16);
> + tmp |= (0x1C << 16);
> + intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
> + tmp |= (1 << 27);
> + intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
> + tmp |= (1 << 27);
> + intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
> + tmp &= ~(0xF << 28);
> + tmp |= (4 << 28);
> + intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
> +
> + tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
> + tmp &= ~(0xF << 28);
> + tmp |= (4 << 28);
> + intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
> +}
> +
> +void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
> +{
> + u32 temp;
> +
> + intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> + temp |= SBI_SSCCTL_DISABLE;
> + intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +/* Program iCLKIP clock to the desired frequency */
> +void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> + u32 divsel, phaseinc, auxdiv, phasedir = 0;
> + u32 temp;
> +
> + lpt_disable_iclkip(dev_priv);
> +
> + /* The iCLK virtual clock root frequency is in MHz,
> + * but the adjusted_mode->crtc_clock in KHz. To get the
> + * divisors, it is necessary to divide one by another, so we
> + * convert the virtual clock precision to KHz here for higher
> + * precision.
> + */
> + for (auxdiv = 0; auxdiv < 2; auxdiv++) {
> + u32 iclk_virtual_root_freq = 172800 * 1000;
> + u32 iclk_pi_range = 64;
> + u32 desired_divisor;
> +
> + desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> + clock << auxdiv);
> + divsel = (desired_divisor / iclk_pi_range) - 2;
> + phaseinc = desired_divisor % iclk_pi_range;
> +
> + /*
> + * Near 20MHz is a corner case which is
> + * out of range for the 7-bit divisor
> + */
> + if (divsel <= 0x7f)
> + break;
> + }
> +
> + /* This should not happen with any sane values */
> + drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
> + ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
> + drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
> + ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
> + clock, auxdiv, divsel, phasedir, phaseinc);
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + /* Program SSCDIVINTPHASE6 */
> + temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
> + temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
> + temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
> + temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
> + temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
> + temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
> + temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
> + intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
> +
> + /* Program SSCAUXDIV */
> + temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
> + temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
> + temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
> + intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
> +
> + /* Enable modulator and associated divider */
> + temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> + temp &= ~SBI_SSCCTL_DISABLE;
> + intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +
> + /* Wait for initialization time */
> + udelay(24);
> +
> + intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
> +}
> +
> +int lpt_get_iclkip(struct drm_i915_private *dev_priv)
> +{
> + u32 divsel, phaseinc, auxdiv;
> + u32 iclk_virtual_root_freq = 172800 * 1000;
> + u32 iclk_pi_range = 64;
> + u32 desired_divisor;
> + u32 temp;
> +
> + if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
> + return 0;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> + if (temp & SBI_SSCCTL_DISABLE) {
> + mutex_unlock(&dev_priv->sb_lock);
> + return 0;
> + }
> +
> + temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
> + divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
> + SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
> + phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
> + SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
> +
> + temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
> + auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
> + SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +
> + desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
> +
> + return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> + desired_divisor << auxdiv);
> +}
> +
> +/* Implements 3 different sequences from BSpec chapter "Display iCLK
> + * Programming" based on the parameters passed:
> + * - Sequence to enable CLKOUT_DP
> + * - Sequence to enable CLKOUT_DP without spread
> + * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
> + */
> +static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
> + bool with_spread, bool with_fdi)
> +{
> + u32 reg, tmp;
> +
> + if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
> + "FDI requires downspread\n"))
> + with_spread = true;
> + if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
> + with_fdi, "LP PCH doesn't have FDI\n"))
> + with_fdi = false;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> + tmp &= ~SBI_SSCCTL_DISABLE;
> + tmp |= SBI_SSCCTL_PATHALT;
> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> +
> + udelay(24);
> +
> + if (with_spread) {
> + tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> + tmp &= ~SBI_SSCCTL_PATHALT;
> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> +
> + if (with_fdi)
> + lpt_fdi_program_mphy(dev_priv);
> + }
> +
> + reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> + tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> + tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> + intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +/* Sequence to disable CLKOUT_DP */
> +void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
> +{
> + u32 reg, tmp;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> + tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> + tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> + intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> +
> + tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> + if (!(tmp & SBI_SSCCTL_DISABLE)) {
> + if (!(tmp & SBI_SSCCTL_PATHALT)) {
> + tmp |= SBI_SSCCTL_PATHALT;
> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> + udelay(32);
> + }
> + tmp |= SBI_SSCCTL_DISABLE;
> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> + }
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +#define BEND_IDX(steps) ((50 + (steps)) / 5)
> +
> +static const u16 sscdivintphase[] = {
> + [BEND_IDX( 50)] = 0x3B23,
> + [BEND_IDX( 45)] = 0x3B23,
> + [BEND_IDX( 40)] = 0x3C23,
> + [BEND_IDX( 35)] = 0x3C23,
> + [BEND_IDX( 30)] = 0x3D23,
> + [BEND_IDX( 25)] = 0x3D23,
> + [BEND_IDX( 20)] = 0x3E23,
> + [BEND_IDX( 15)] = 0x3E23,
> + [BEND_IDX( 10)] = 0x3F23,
> + [BEND_IDX( 5)] = 0x3F23,
> + [BEND_IDX( 0)] = 0x0025,
> + [BEND_IDX( -5)] = 0x0025,
> + [BEND_IDX(-10)] = 0x0125,
> + [BEND_IDX(-15)] = 0x0125,
> + [BEND_IDX(-20)] = 0x0225,
> + [BEND_IDX(-25)] = 0x0225,
> + [BEND_IDX(-30)] = 0x0325,
> + [BEND_IDX(-35)] = 0x0325,
> + [BEND_IDX(-40)] = 0x0425,
> + [BEND_IDX(-45)] = 0x0425,
> + [BEND_IDX(-50)] = 0x0525,
> +};
> +
> +/*
> + * Bend CLKOUT_DP
> + * steps -50 to 50 inclusive, in steps of 5
> + * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
> + * change in clock period = -(steps / 10) * 5.787 ps
> + */
> +static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
> +{
> + u32 tmp;
> + int idx = BEND_IDX(steps);
> +
> + if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
> + return;
> +
> + if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
> + return;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + if (steps % 10 != 0)
> + tmp = 0xAAAAAAAB;
> + else
> + tmp = 0x00000000;
> + intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
> +
> + tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
> + tmp &= 0xffff0000;
> + tmp |= sscdivintphase[idx];
> + intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +#undef BEND_IDX
> +
> +static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
> +{
> + u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
> + u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
> +
> + if ((ctl & SPLL_PLL_ENABLE) == 0)
> + return false;
> +
> + if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
> + (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
> + return true;
> +
> + if (IS_BROADWELL(dev_priv) &&
> + (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
> + return true;
> +
> + return false;
> +}
> +
> +static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
> + enum intel_dpll_id id)
> +{
> + u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
> + u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
> +
> + if ((ctl & WRPLL_PLL_ENABLE) == 0)
> + return false;
> +
> + if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
> + return true;
> +
> + if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
> + (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
> + (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
> + return true;
> +
> + return false;
> +}
> +
> +static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_encoder *encoder;
> + bool has_fdi = false;
> +
> + for_each_intel_encoder(&dev_priv->drm, encoder) {
> + switch (encoder->type) {
> + case INTEL_OUTPUT_ANALOG:
> + has_fdi = true;
> + break;
> + default:
> + break;
> + }
> + }
> +
> + /*
> + * The BIOS may have decided to use the PCH SSC
> + * reference so we must not disable it until the
> + * relevant PLLs have stopped relying on it. We'll
> + * just leave the PCH SSC reference enabled in case
> + * any active PLL is using it. It will get disabled
> + * after runtime suspend if we don't have FDI.
> + *
> + * TODO: Move the whole reference clock handling
> + * to the modeset sequence proper so that we can
> + * actually enable/disable/reconfigure these things
> + * safely. To do that we need to introduce a real
> + * clock hierarchy. That would also allow us to do
> + * clock bending finally.
> + */
> + dev_priv->pch_ssc_use = 0;
> +
> + if (spll_uses_pch_ssc(dev_priv)) {
> + drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
> + dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
> + }
> +
> + if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
> + drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
> + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
> + }
> +
> + if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
> + drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
> + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
> + }
> +
> + if (dev_priv->pch_ssc_use)
> + return;
> +
> + if (has_fdi) {
> + lpt_bend_clkout_dp(dev_priv, 0);
> + lpt_enable_clkout_dp(dev_priv, true, true);
> + } else {
> + lpt_disable_clkout_dp(dev_priv);
> + }
> +}
> +
> +static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_encoder *encoder;
> + int i;
> + u32 val, final;
> + bool has_lvds = false;
> + bool has_cpu_edp = false;
> + bool has_panel = false;
> + bool has_ck505 = false;
> + bool can_ssc = false;
> + bool using_ssc_source = false;
> +
> + /* We need to take the global config into account */
> + for_each_intel_encoder(&dev_priv->drm, encoder) {
> + switch (encoder->type) {
> + case INTEL_OUTPUT_LVDS:
> + has_panel = true;
> + has_lvds = true;
> + break;
> + case INTEL_OUTPUT_EDP:
> + has_panel = true;
> + if (encoder->port == PORT_A)
> + has_cpu_edp = true;
> + break;
> + default:
> + break;
> + }
> + }
> +
> + if (HAS_PCH_IBX(dev_priv)) {
> + has_ck505 = dev_priv->vbt.display_clock_mode;
> + can_ssc = has_ck505;
> + } else {
> + has_ck505 = false;
> + can_ssc = true;
> + }
> +
> + /* Check if any DPLLs are using the SSC source */
> + for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
> + u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
> +
> + if (!(temp & DPLL_VCO_ENABLE))
> + continue;
> +
> + if ((temp & PLL_REF_INPUT_MASK) ==
> + PLLB_REF_INPUT_SPREADSPECTRUMIN) {
> + using_ssc_source = true;
> + break;
> + }
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
> + has_panel, has_lvds, has_ck505, using_ssc_source);
> +
> + /* Ironlake: try to setup display ref clock before DPLL
> + * enabling. This is only under driver's control after
> + * PCH B stepping, previous chipset stepping should be
> + * ignoring this setting.
> + */
> + val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
> +
> + /* As we must carefully and slowly disable/enable each source in turn,
> + * compute the final state we want first and check if we need to
> + * make any changes at all.
> + */
> + final = val;
> + final &= ~DREF_NONSPREAD_SOURCE_MASK;
> + if (has_ck505)
> + final |= DREF_NONSPREAD_CK505_ENABLE;
> + else
> + final |= DREF_NONSPREAD_SOURCE_ENABLE;
> +
> + final &= ~DREF_SSC_SOURCE_MASK;
> + final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> + final &= ~DREF_SSC1_ENABLE;
> +
> + if (has_panel) {
> + final |= DREF_SSC_SOURCE_ENABLE;
> +
> + if (intel_panel_use_ssc(dev_priv) && can_ssc)
> + final |= DREF_SSC1_ENABLE;
> +
> + if (has_cpu_edp) {
> + if (intel_panel_use_ssc(dev_priv) && can_ssc)
> + final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
> + else
> + final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> + } else {
> + final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
> + }
> + } else if (using_ssc_source) {
> + final |= DREF_SSC_SOURCE_ENABLE;
> + final |= DREF_SSC1_ENABLE;
> + }
> +
> + if (final == val)
> + return;
> +
> + /* Always enable nonspread source */
> + val &= ~DREF_NONSPREAD_SOURCE_MASK;
> +
> + if (has_ck505)
> + val |= DREF_NONSPREAD_CK505_ENABLE;
> + else
> + val |= DREF_NONSPREAD_SOURCE_ENABLE;
> +
> + if (has_panel) {
> + val &= ~DREF_SSC_SOURCE_MASK;
> + val |= DREF_SSC_SOURCE_ENABLE;
> +
> + /* SSC must be turned on before enabling the CPU output */
> + if (intel_panel_use_ssc(dev_priv) && can_ssc) {
> + drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
> + val |= DREF_SSC1_ENABLE;
> + } else {
> + val &= ~DREF_SSC1_ENABLE;
> + }
> +
> + /* Get SSC going before enabling the outputs */
> + intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + udelay(200);
> +
> + val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> +
> + /* Enable CPU source on CPU attached eDP */
> + if (has_cpu_edp) {
> + if (intel_panel_use_ssc(dev_priv) && can_ssc) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Using SSC on eDP\n");
> + val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
> + } else {
> + val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> + }
> + } else {
> + val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
> + }
> +
> + intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + udelay(200);
> + } else {
> + drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
> +
> + val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> +
> + /* Turn off CPU output */
> + val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
> +
> + intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + udelay(200);
> +
> + if (!using_ssc_source) {
> + drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
> +
> + /* Turn off the SSC source */
> + val &= ~DREF_SSC_SOURCE_MASK;
> + val |= DREF_SSC_SOURCE_DISABLE;
> +
> + /* Turn off SSC1 */
> + val &= ~DREF_SSC1_ENABLE;
> +
> + intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + udelay(200);
> + }
> + }
> +
> + BUG_ON(val != final);
> +}
> +
> +/*
> + * Initialize reference clocks when the driver loads
> + */
> +void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
> +{
> + if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> + ilk_init_pch_refclk(dev_priv);
> + else if (HAS_PCH_LPT(dev_priv))
> + lpt_init_pch_refclk(dev_priv);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> new file mode 100644
> index 000000000000..12ab2c75a800
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_PCH_REFCLK_H_
> +#define _INTEL_PCH_REFCLK_H_
> +
> +#include <linux/types.h>
> +
> +struct drm_i915_private;
> +struct intel_crtc_state;
> +
> +void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);
> +void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
> +int lpt_get_iclkip(struct drm_i915_private *dev_priv);
> +
> +void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
> +void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b18a250e5d2e..1e5b75ae9932 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -54,6 +54,7 @@
> #include "display/intel_fbdev.h"
> #include "display/intel_hotplug.h"
> #include "display/intel_overlay.h"
> +#include "display/intel_pch_refclk.h"
> #include "display/intel_pipe_crc.h"
> #include "display/intel_pps.h"
> #include "display/intel_sprite.h"
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 1/9] drm/i915: Move PCH refclok stuff into its own file
2021-10-17 23:56 ` David Airlie
@ 2021-10-18 8:13 ` Ville Syrjälä
2021-10-18 13:13 ` Ville Syrjälä
0 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjälä @ 2021-10-18 8:13 UTC (permalink / raw)
To: David Airlie; +Cc: Development, Intel, Jani Nikula
On Mon, Oct 18, 2021 at 09:56:33AM +1000, David Airlie wrote:
> On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Move the PCH refclk stuff (including all the LPT/WPT
> > iCLKIP/CLKOUT_DP things) to its own file.
> >
> > We also suck in the mPHY programming from intel_fdi.c
> > since we're the only caller.
>
> The title of the patch has a typo refclok->reclock.
I must be blind since I don't see the typo.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH 1/9] drm/i915: Move PCH refclok stuff into its own file
2021-10-18 8:13 ` Ville Syrjälä
@ 2021-10-18 13:13 ` Ville Syrjälä
0 siblings, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2021-10-18 13:13 UTC (permalink / raw)
To: David Airlie; +Cc: Development, Intel, Jani Nikula
On Mon, Oct 18, 2021 at 11:13:41AM +0300, Ville Syrjälä wrote:
> On Mon, Oct 18, 2021 at 09:56:33AM +1000, David Airlie wrote:
> > On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
> > <ville.syrjala@linux.intel.com> wrote:
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Move the PCH refclk stuff (including all the LPT/WPT
> > > iCLKIP/CLKOUT_DP things) to its own file.
> > >
> > > We also suck in the mPHY programming from intel_fdi.c
> > > since we're the only caller.
> >
> > The title of the patch has a typo refclok->reclock.
>
> I must be blind since I don't see the typo.
Oh now I see it. Your suggested fix had another typo ;)
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 2/9] drm/i915: Move PCH modeset code to its own file
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
2021-10-15 7:16 ` [Intel-gfx] [PATCH 1/9] drm/i915: Move PCH refclok stuff " Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-17 23:57 ` David Airlie
2021-10-15 7:16 ` [Intel-gfx] [PATCH 3/9] drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention Ville Syrjala
` (14 subsequent siblings)
16 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Start moving the code for PCH modeset sequence/etc. to
its own file.
Still not sure about the file name though...
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 348 +----------------
drivers/gpu/drm/i915/display/intel_display.h | 5 -
.../gpu/drm/i915/display/intel_pch_display.c | 365 ++++++++++++++++++
.../gpu/drm/i915/display/intel_pch_display.h | 22 ++
6 files changed, 390 insertions(+), 352 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pch_display.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pch_display.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 96f3b8f6c50d..467872cca027 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -226,6 +226,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
display/intel_overlay.o \
+ display/intel_pch_display.o \
display/intel_pch_refclk.o \
display/intel_plane_initial.o \
display/intel_psr.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index bf03bd0ecd43..54540138bd1d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -45,6 +45,7 @@
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug.h"
+#include "intel_pch_display.h"
#include "intel_pch_refclk.h"
/* Here's the desired hotplug mode */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 995050443065..69549886fe5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -96,6 +96,7 @@
#include "intel_hotplug.h"
#include "intel_overlay.h"
#include "intel_panel.h"
+#include "intel_pch_display.h"
#include "intel_pch_refclk.h"
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
@@ -454,80 +455,6 @@ static void assert_planes_disabled(struct intel_crtc *crtc)
assert_plane_disabled(plane);
}
-void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- u32 val;
- bool enabled;
-
- val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
- enabled = !!(val & TRANS_ENABLE);
- I915_STATE_WARN(enabled,
- "transcoder assertion failed, should be off on pipe %c but is still active\n",
- pipe_name(pipe));
-}
-
-static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, enum port port,
- i915_reg_t dp_reg)
-{
- enum pipe port_pipe;
- bool state;
-
- state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
-
- I915_STATE_WARN(state && port_pipe == pipe,
- "PCH DP %c enabled on transcoder %c, should be disabled\n",
- port_name(port), pipe_name(pipe));
-
- I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
- "IBX PCH DP %c still using transcoder B\n",
- port_name(port));
-}
-
-static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, enum port port,
- i915_reg_t hdmi_reg)
-{
- enum pipe port_pipe;
- bool state;
-
- state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
-
- I915_STATE_WARN(state && port_pipe == pipe,
- "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
- port_name(port), pipe_name(pipe));
-
- I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
- "IBX PCH HDMI %c still using transcoder B\n",
- port_name(port));
-}
-
-static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- enum pipe port_pipe;
-
- assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
- assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
- assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
-
- I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
- port_pipe == pipe,
- "PCH VGA enabled on transcoder %c, should be disabled\n",
- pipe_name(pipe));
-
- I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
- port_pipe == pipe,
- "PCH LVDS enabled on transcoder %c, should be disabled\n",
- pipe_name(pipe));
-
- /* PCH SDVOB multiplex with HDMIB */
- assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
- assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
- assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
-}
-
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
struct intel_digital_port *dig_port,
unsigned int expected_mask)
@@ -562,154 +489,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
expected_mask);
}
-static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
- u32 val, pipeconf_val;
-
- /* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
-
- /* FDI must be feeding us bits for PCH ports */
- assert_fdi_tx_enabled(dev_priv, pipe);
- assert_fdi_rx_enabled(dev_priv, pipe);
-
- if (HAS_PCH_CPT(dev_priv)) {
- reg = TRANS_CHICKEN2(pipe);
- val = intel_de_read(dev_priv, reg);
- /*
- * Workaround: Set the timing override bit
- * before enabling the pch transcoder.
- */
- val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
- /* Configure frame start delay to match the CPU */
- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
- val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
- intel_de_write(dev_priv, reg, val);
- }
-
- reg = PCH_TRANSCONF(pipe);
- val = intel_de_read(dev_priv, reg);
- pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
-
- if (HAS_PCH_IBX(dev_priv)) {
- /* Configure frame start delay to match the CPU */
- val &= ~TRANS_FRAME_START_DELAY_MASK;
- val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
-
- /*
- * Make the BPC in transcoder be consistent with
- * that in pipeconf reg. For HDMI we must use 8bpc
- * here for both 8bpc and 12bpc.
- */
- val &= ~PIPECONF_BPC_MASK;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- val |= PIPECONF_8BPC;
- else
- val |= pipeconf_val & PIPECONF_BPC_MASK;
- }
-
- val &= ~TRANS_INTERLACE_MASK;
- if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
- if (HAS_PCH_IBX(dev_priv) &&
- intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
- val |= TRANS_LEGACY_INTERLACED_ILK;
- else
- val |= TRANS_INTERLACED;
- } else {
- val |= TRANS_PROGRESSIVE;
- }
-
- intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
- if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
- drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
- pipe_name(pipe));
-}
-
-static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
- enum transcoder cpu_transcoder)
-{
- u32 val, pipeconf_val;
-
- /* FDI must be feeding us bits for PCH ports */
- assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
- assert_fdi_rx_enabled(dev_priv, PIPE_A);
-
- val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
- /* Workaround: set timing override bit. */
- val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
- /* Configure frame start delay to match the CPU */
- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
- val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
- intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
-
- val = TRANS_ENABLE;
- pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
-
- if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
- PIPECONF_INTERLACED_ILK)
- val |= TRANS_INTERLACED;
- else
- val |= TRANS_PROGRESSIVE;
-
- intel_de_write(dev_priv, LPT_TRANSCONF, val);
- if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
- TRANS_STATE_ENABLE, 100))
- drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
-}
-
-static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- i915_reg_t reg;
- u32 val;
-
- /* FDI relies on the transcoder */
- assert_fdi_tx_disabled(dev_priv, pipe);
- assert_fdi_rx_disabled(dev_priv, pipe);
-
- /* Ports must be off as well */
- assert_pch_ports_disabled(dev_priv, pipe);
-
- reg = PCH_TRANSCONF(pipe);
- val = intel_de_read(dev_priv, reg);
- val &= ~TRANS_ENABLE;
- intel_de_write(dev_priv, reg, val);
- /* wait for PCH transcoder off, transcoder state */
- if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
- drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
- pipe_name(pipe));
-
- if (HAS_PCH_CPT(dev_priv)) {
- /* Workaround: Clear the timing override chicken bit again. */
- reg = TRANS_CHICKEN2(pipe);
- val = intel_de_read(dev_priv, reg);
- val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
- intel_de_write(dev_priv, reg, val);
- }
-}
-
-void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
-{
- u32 val;
-
- val = intel_de_read(dev_priv, LPT_TRANSCONF);
- val &= ~TRANS_ENABLE;
- intel_de_write(dev_priv, LPT_TRANSCONF, val);
- /* wait for PCH transcoder off, transcoder state */
- if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
- TRANS_STATE_ENABLE, 50))
- drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
-
- /* Workaround: clear timing override bit. */
- val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
- val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
- intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
-}
-
enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1388,31 +1167,6 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
return false;
}
-
-static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
- enum pipe pch_transcoder)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-
- intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
- intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
- intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
- intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
- intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
- intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
-
- intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
- intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
- intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
- intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
- intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
- intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
- intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
- intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
-}
-
/*
* Finds the encoder associated with the given CRTC. This can only be
* used when we know that the CRTC isn't feeding multiple encoders!
@@ -1443,106 +1197,6 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
return encoder;
}
-/*
- * Enable PCH resources required for PCH ports:
- * - PCH PLLs
- * - FDI training & RX/TX
- * - update transcoder timings
- * - DP transcoding bits
- * - transcoder
- */
-static void ilk_pch_enable(const struct intel_atomic_state *state,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- enum pipe pipe = crtc->pipe;
- u32 temp;
-
- assert_pch_transcoder_disabled(dev_priv, pipe);
-
- /* For PCH output, training FDI link */
- intel_fdi_link_train(crtc, crtc_state);
-
- /* We need to program the right clock selection before writing the pixel
- * mutliplier into the DPLL. */
- if (HAS_PCH_CPT(dev_priv)) {
- u32 sel;
-
- temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
- temp |= TRANS_DPLL_ENABLE(pipe);
- sel = TRANS_DPLLB_SEL(pipe);
- if (crtc_state->shared_dpll ==
- intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
- temp |= sel;
- else
- temp &= ~sel;
- intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
- }
-
- /* XXX: pch pll's can be enabled any time before we enable the PCH
- * transcoder, and we actually should do this to not upset any PCH
- * transcoder that already use the clock when we share it.
- *
- * Note that enable_shared_dpll tries to do the right thing, but
- * get_shared_dpll unconditionally resets the pll - we need that to have
- * the right LVDS enable sequence. */
- intel_enable_shared_dpll(crtc_state);
-
- /* set transcoder timing, panel must allow it */
- assert_pps_unlocked(dev_priv, pipe);
- ilk_pch_transcoder_set_timings(crtc_state, pipe);
-
- intel_fdi_normal_train(crtc);
-
- /* For PCH DP, enable TRANS_DP_CTL */
- if (HAS_PCH_CPT(dev_priv) &&
- intel_crtc_has_dp_encoder(crtc_state)) {
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
- u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
- i915_reg_t reg = TRANS_DP_CTL(pipe);
- enum port port;
-
- temp = intel_de_read(dev_priv, reg);
- temp &= ~(TRANS_DP_PORT_SEL_MASK |
- TRANS_DP_SYNC_MASK |
- TRANS_DP_BPC_MASK);
- temp |= TRANS_DP_OUTPUT_ENABLE;
- temp |= bpc << 9; /* same format but at 11:9 */
-
- if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
- temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
- if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
- temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
-
- port = intel_get_crtc_new_encoder(state, crtc_state)->port;
- drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
- temp |= TRANS_DP_PORT_SEL(port);
-
- intel_de_write(dev_priv, reg, temp);
- }
-
- ilk_enable_pch_transcoder(crtc_state);
-}
-
-void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-
- assert_pch_transcoder_disabled(dev_priv, PIPE_A);
-
- lpt_program_iclkip(crtc_state);
-
- /* Set transcoder timing. */
- ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
-
- lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
-}
-
static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 39c18b8807f9..93c84f2174b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -541,8 +541,6 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
const char *name, u32 reg, int ref_freq);
int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
const char *name, u32 reg);
-void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
-void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
void intel_init_display_hooks(struct drm_i915_private *dev_priv);
unsigned int intel_fb_xy_to_linear(int x, int y,
const struct intel_plane_state *state,
@@ -578,9 +576,6 @@ struct drm_framebuffer *
intel_framebuffer_create(struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd);
-void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe);
-
bool intel_fuzzy_clock_check(int clock1, int clock2);
void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
new file mode 100644
index 000000000000..0056c2fe49ec
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "g4x_dp.h"
+#include "intel_crt.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_fdi.h"
+#include "intel_lvds.h"
+#include "intel_pch_display.h"
+#include "intel_pch_refclk.h"
+#include "intel_pps.h"
+#include "intel_sdvo.h"
+
+static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port,
+ i915_reg_t dp_reg)
+{
+ enum pipe port_pipe;
+ bool state;
+
+ state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
+
+ I915_STATE_WARN(state && port_pipe == pipe,
+ "PCH DP %c enabled on transcoder %c, should be disabled\n",
+ port_name(port), pipe_name(pipe));
+
+ I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
+ "IBX PCH DP %c still using transcoder B\n",
+ port_name(port));
+}
+
+static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port,
+ i915_reg_t hdmi_reg)
+{
+ enum pipe port_pipe;
+ bool state;
+
+ state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
+
+ I915_STATE_WARN(state && port_pipe == pipe,
+ "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
+ port_name(port), pipe_name(pipe));
+
+ I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
+ "IBX PCH HDMI %c still using transcoder B\n",
+ port_name(port));
+}
+
+static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ enum pipe port_pipe;
+
+ assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
+ assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
+ assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
+
+ I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
+ port_pipe == pipe,
+ "PCH VGA enabled on transcoder %c, should be disabled\n",
+ pipe_name(pipe));
+
+ I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
+ port_pipe == pipe,
+ "PCH LVDS enabled on transcoder %c, should be disabled\n",
+ pipe_name(pipe));
+
+ /* PCH SDVOB multiplex with HDMIB */
+ assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
+}
+
+static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ u32 val;
+ bool enabled;
+
+ val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
+ enabled = !!(val & TRANS_ENABLE);
+ I915_STATE_WARN(enabled,
+ "transcoder assertion failed, should be off on pipe %c but is still active\n",
+ pipe_name(pipe));
+}
+
+static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
+ enum pipe pch_transcoder)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
+ intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
+ intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
+ intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
+ intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
+ intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
+
+ intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
+ intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
+ intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
+ intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
+ intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
+ intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
+ intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
+ intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
+}
+
+static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t reg;
+ u32 val, pipeconf_val;
+
+ /* Make sure PCH DPLL is enabled */
+ assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
+
+ /* FDI must be feeding us bits for PCH ports */
+ assert_fdi_tx_enabled(dev_priv, pipe);
+ assert_fdi_rx_enabled(dev_priv, pipe);
+
+ if (HAS_PCH_CPT(dev_priv)) {
+ reg = TRANS_CHICKEN2(pipe);
+ val = intel_de_read(dev_priv, reg);
+ /*
+ * Workaround: Set the timing override bit
+ * before enabling the pch transcoder.
+ */
+ val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ intel_de_write(dev_priv, reg, val);
+ }
+
+ reg = PCH_TRANSCONF(pipe);
+ val = intel_de_read(dev_priv, reg);
+ pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
+
+ if (HAS_PCH_IBX(dev_priv)) {
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_FRAME_START_DELAY_MASK;
+ val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+
+ /*
+ * Make the BPC in transcoder be consistent with
+ * that in pipeconf reg. For HDMI we must use 8bpc
+ * here for both 8bpc and 12bpc.
+ */
+ val &= ~PIPECONF_BPC_MASK;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ val |= PIPECONF_8BPC;
+ else
+ val |= pipeconf_val & PIPECONF_BPC_MASK;
+ }
+
+ val &= ~TRANS_INTERLACE_MASK;
+ if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
+ if (HAS_PCH_IBX(dev_priv) &&
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
+ val |= TRANS_LEGACY_INTERLACED_ILK;
+ else
+ val |= TRANS_INTERLACED;
+ } else {
+ val |= TRANS_PROGRESSIVE;
+ }
+
+ intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
+ if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
+ drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
+ pipe_name(pipe));
+}
+
+void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ i915_reg_t reg;
+ u32 val;
+
+ /* FDI relies on the transcoder */
+ assert_fdi_tx_disabled(dev_priv, pipe);
+ assert_fdi_rx_disabled(dev_priv, pipe);
+
+ /* Ports must be off as well */
+ assert_pch_ports_disabled(dev_priv, pipe);
+
+ reg = PCH_TRANSCONF(pipe);
+ val = intel_de_read(dev_priv, reg);
+ val &= ~TRANS_ENABLE;
+ intel_de_write(dev_priv, reg, val);
+ /* wait for PCH transcoder off, transcoder state */
+ if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
+ drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
+ pipe_name(pipe));
+
+ if (HAS_PCH_CPT(dev_priv)) {
+ /* Workaround: Clear the timing override chicken bit again. */
+ reg = TRANS_CHICKEN2(pipe);
+ val = intel_de_read(dev_priv, reg);
+ val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
+ intel_de_write(dev_priv, reg, val);
+ }
+}
+
+/*
+ * Enable PCH resources required for PCH ports:
+ * - PCH PLLs
+ * - FDI training & RX/TX
+ * - update transcoder timings
+ * - DP transcoding bits
+ * - transcoder
+ */
+void ilk_pch_enable(const struct intel_atomic_state *state,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 temp;
+
+ assert_pch_transcoder_disabled(dev_priv, pipe);
+
+ /* For PCH output, training FDI link */
+ intel_fdi_link_train(crtc, crtc_state);
+
+ /*
+ * We need to program the right clock selection
+ * before writing the pixel multiplier into the DPLL.
+ */
+ if (HAS_PCH_CPT(dev_priv)) {
+ u32 sel;
+
+ temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+ temp |= TRANS_DPLL_ENABLE(pipe);
+ sel = TRANS_DPLLB_SEL(pipe);
+ if (crtc_state->shared_dpll ==
+ intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
+ temp |= sel;
+ else
+ temp &= ~sel;
+ intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+ }
+
+ /*
+ * XXX: pch pll's can be enabled any time before we enable the PCH
+ * transcoder, and we actually should do this to not upset any PCH
+ * transcoder that already use the clock when we share it.
+ *
+ * Note that enable_shared_dpll tries to do the right thing, but
+ * get_shared_dpll unconditionally resets the pll - we need that
+ * to have the right LVDS enable sequence.
+ */
+ intel_enable_shared_dpll(crtc_state);
+
+ /* set transcoder timing, panel must allow it */
+ assert_pps_unlocked(dev_priv, pipe);
+ ilk_pch_transcoder_set_timings(crtc_state, pipe);
+
+ intel_fdi_normal_train(crtc);
+
+ /* For PCH DP, enable TRANS_DP_CTL */
+ if (HAS_PCH_CPT(dev_priv) &&
+ intel_crtc_has_dp_encoder(crtc_state)) {
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
+ i915_reg_t reg = TRANS_DP_CTL(pipe);
+ enum port port;
+
+ temp = intel_de_read(dev_priv, reg);
+ temp &= ~(TRANS_DP_PORT_SEL_MASK |
+ TRANS_DP_SYNC_MASK |
+ TRANS_DP_BPC_MASK);
+ temp |= TRANS_DP_OUTPUT_ENABLE;
+ temp |= bpc << 9; /* same format but at 11:9 */
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
+
+ port = intel_get_crtc_new_encoder(state, crtc_state)->port;
+ drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
+ temp |= TRANS_DP_PORT_SEL(port);
+
+ intel_de_write(dev_priv, reg, temp);
+ }
+
+ ilk_enable_pch_transcoder(crtc_state);
+}
+
+static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder)
+{
+ u32 val, pipeconf_val;
+
+ /* FDI must be feeding us bits for PCH ports */
+ assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
+ assert_fdi_rx_enabled(dev_priv, PIPE_A);
+
+ val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
+ /* Workaround: set timing override bit. */
+ val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
+
+ val = TRANS_ENABLE;
+ pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
+
+ if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
+ PIPECONF_INTERLACED_ILK)
+ val |= TRANS_INTERLACED;
+ else
+ val |= TRANS_PROGRESSIVE;
+
+ intel_de_write(dev_priv, LPT_TRANSCONF, val);
+ if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
+ TRANS_STATE_ENABLE, 100))
+ drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
+}
+
+void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = intel_de_read(dev_priv, LPT_TRANSCONF);
+ val &= ~TRANS_ENABLE;
+ intel_de_write(dev_priv, LPT_TRANSCONF, val);
+ /* wait for PCH transcoder off, transcoder state */
+ if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
+ TRANS_STATE_ENABLE, 50))
+ drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
+
+ /* Workaround: clear timing override bit. */
+ val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
+ val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
+ intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
+}
+
+void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ assert_pch_transcoder_disabled(dev_priv, PIPE_A);
+
+ lpt_program_iclkip(crtc_state);
+
+ /* Set transcoder timing. */
+ ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
+
+ lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
new file mode 100644
index 000000000000..6eba1fd667ea
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_PCH_DISPLAY_H_
+#define _INTEL_PCH_DISPLAY_H_
+
+enum pipe;
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc_state;
+
+void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe);
+void ilk_pch_enable(const struct intel_atomic_state *state,
+ const struct intel_crtc_state *crtc_state);
+
+void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
+void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
+
+#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 2/9] drm/i915: Move PCH modeset code to its own file
2021-10-15 7:16 ` [Intel-gfx] [PATCH 2/9] drm/i915: Move PCH modeset code to " Ville Syrjala
@ 2021-10-17 23:57 ` David Airlie
0 siblings, 0 replies; 39+ messages in thread
From: David Airlie @ 2021-10-17 23:57 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Start moving the code for PCH modeset sequence/etc. to
> its own file.
>
> Still not sure about the file name though...
Name is good enough for now, there aren't a lot of great names, no
point getting stuck on it.
Otherwise
Reviewed-by: Dave Airlie <airlied@redhat.com>
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 348 +----------------
> drivers/gpu/drm/i915/display/intel_display.h | 5 -
> .../gpu/drm/i915/display/intel_pch_display.c | 365 ++++++++++++++++++
> .../gpu/drm/i915/display/intel_pch_display.h | 22 ++
> 6 files changed, 390 insertions(+), 352 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pch_display.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pch_display.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 96f3b8f6c50d..467872cca027 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -226,6 +226,7 @@ i915-y += \
> display/intel_hotplug.o \
> display/intel_lpe_audio.o \
> display/intel_overlay.o \
> + display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> display/intel_plane_initial.o \
> display/intel_psr.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index bf03bd0ecd43..54540138bd1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -45,6 +45,7 @@
> #include "intel_fifo_underrun.h"
> #include "intel_gmbus.h"
> #include "intel_hotplug.h"
> +#include "intel_pch_display.h"
> #include "intel_pch_refclk.h"
>
> /* Here's the desired hotplug mode */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 995050443065..69549886fe5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -96,6 +96,7 @@
> #include "intel_hotplug.h"
> #include "intel_overlay.h"
> #include "intel_panel.h"
> +#include "intel_pch_display.h"
> #include "intel_pch_refclk.h"
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> @@ -454,80 +455,6 @@ static void assert_planes_disabled(struct intel_crtc *crtc)
> assert_plane_disabled(plane);
> }
>
> -void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> -{
> - u32 val;
> - bool enabled;
> -
> - val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
> - enabled = !!(val & TRANS_ENABLE);
> - I915_STATE_WARN(enabled,
> - "transcoder assertion failed, should be off on pipe %c but is still active\n",
> - pipe_name(pipe));
> -}
> -
> -static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
> - enum pipe pipe, enum port port,
> - i915_reg_t dp_reg)
> -{
> - enum pipe port_pipe;
> - bool state;
> -
> - state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
> -
> - I915_STATE_WARN(state && port_pipe == pipe,
> - "PCH DP %c enabled on transcoder %c, should be disabled\n",
> - port_name(port), pipe_name(pipe));
> -
> - I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
> - "IBX PCH DP %c still using transcoder B\n",
> - port_name(port));
> -}
> -
> -static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> - enum pipe pipe, enum port port,
> - i915_reg_t hdmi_reg)
> -{
> - enum pipe port_pipe;
> - bool state;
> -
> - state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
> -
> - I915_STATE_WARN(state && port_pipe == pipe,
> - "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
> - port_name(port), pipe_name(pipe));
> -
> - I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
> - "IBX PCH HDMI %c still using transcoder B\n",
> - port_name(port));
> -}
> -
> -static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> -{
> - enum pipe port_pipe;
> -
> - assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
> - assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
> - assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
> -
> - I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
> - port_pipe == pipe,
> - "PCH VGA enabled on transcoder %c, should be disabled\n",
> - pipe_name(pipe));
> -
> - I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
> - port_pipe == pipe,
> - "PCH LVDS enabled on transcoder %c, should be disabled\n",
> - pipe_name(pipe));
> -
> - /* PCH SDVOB multiplex with HDMIB */
> - assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
> - assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
> - assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
> -}
> -
> void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> struct intel_digital_port *dig_port,
> unsigned int expected_mask)
> @@ -562,154 +489,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> expected_mask);
> }
>
> -static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - i915_reg_t reg;
> - u32 val, pipeconf_val;
> -
> - /* Make sure PCH DPLL is enabled */
> - assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
> -
> - /* FDI must be feeding us bits for PCH ports */
> - assert_fdi_tx_enabled(dev_priv, pipe);
> - assert_fdi_rx_enabled(dev_priv, pipe);
> -
> - if (HAS_PCH_CPT(dev_priv)) {
> - reg = TRANS_CHICKEN2(pipe);
> - val = intel_de_read(dev_priv, reg);
> - /*
> - * Workaround: Set the timing override bit
> - * before enabling the pch transcoder.
> - */
> - val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> - /* Configure frame start delay to match the CPU */
> - val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> - val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
> - intel_de_write(dev_priv, reg, val);
> - }
> -
> - reg = PCH_TRANSCONF(pipe);
> - val = intel_de_read(dev_priv, reg);
> - pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
> -
> - if (HAS_PCH_IBX(dev_priv)) {
> - /* Configure frame start delay to match the CPU */
> - val &= ~TRANS_FRAME_START_DELAY_MASK;
> - val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
> -
> - /*
> - * Make the BPC in transcoder be consistent with
> - * that in pipeconf reg. For HDMI we must use 8bpc
> - * here for both 8bpc and 12bpc.
> - */
> - val &= ~PIPECONF_BPC_MASK;
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> - val |= PIPECONF_8BPC;
> - else
> - val |= pipeconf_val & PIPECONF_BPC_MASK;
> - }
> -
> - val &= ~TRANS_INTERLACE_MASK;
> - if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
> - if (HAS_PCH_IBX(dev_priv) &&
> - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> - val |= TRANS_LEGACY_INTERLACED_ILK;
> - else
> - val |= TRANS_INTERLACED;
> - } else {
> - val |= TRANS_PROGRESSIVE;
> - }
> -
> - intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
> - if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
> - drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
> - pipe_name(pipe));
> -}
> -
> -static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> - enum transcoder cpu_transcoder)
> -{
> - u32 val, pipeconf_val;
> -
> - /* FDI must be feeding us bits for PCH ports */
> - assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> - assert_fdi_rx_enabled(dev_priv, PIPE_A);
> -
> - val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
> - /* Workaround: set timing override bit. */
> - val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> - /* Configure frame start delay to match the CPU */
> - val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> - val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
> - intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
> -
> - val = TRANS_ENABLE;
> - pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
> -
> - if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> - PIPECONF_INTERLACED_ILK)
> - val |= TRANS_INTERLACED;
> - else
> - val |= TRANS_PROGRESSIVE;
> -
> - intel_de_write(dev_priv, LPT_TRANSCONF, val);
> - if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
> - TRANS_STATE_ENABLE, 100))
> - drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
> -}
> -
> -static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> -{
> - i915_reg_t reg;
> - u32 val;
> -
> - /* FDI relies on the transcoder */
> - assert_fdi_tx_disabled(dev_priv, pipe);
> - assert_fdi_rx_disabled(dev_priv, pipe);
> -
> - /* Ports must be off as well */
> - assert_pch_ports_disabled(dev_priv, pipe);
> -
> - reg = PCH_TRANSCONF(pipe);
> - val = intel_de_read(dev_priv, reg);
> - val &= ~TRANS_ENABLE;
> - intel_de_write(dev_priv, reg, val);
> - /* wait for PCH transcoder off, transcoder state */
> - if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
> - drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
> - pipe_name(pipe));
> -
> - if (HAS_PCH_CPT(dev_priv)) {
> - /* Workaround: Clear the timing override chicken bit again. */
> - reg = TRANS_CHICKEN2(pipe);
> - val = intel_de_read(dev_priv, reg);
> - val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> - intel_de_write(dev_priv, reg, val);
> - }
> -}
> -
> -void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> -
> - val = intel_de_read(dev_priv, LPT_TRANSCONF);
> - val &= ~TRANS_ENABLE;
> - intel_de_write(dev_priv, LPT_TRANSCONF, val);
> - /* wait for PCH transcoder off, transcoder state */
> - if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
> - TRANS_STATE_ENABLE, 50))
> - drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
> -
> - /* Workaround: clear timing override bit. */
> - val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
> - val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> - intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
> -}
> -
> enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1388,31 +1167,6 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
> return false;
> }
>
> -
> -static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
> - enum pipe pch_transcoder)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -
> - intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
> - intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
> - intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
> - intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
> - intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
> - intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
> -
> - intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
> - intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
> - intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
> - intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
> - intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
> - intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
> - intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
> - intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
> -}
> -
> /*
> * Finds the encoder associated with the given CRTC. This can only be
> * used when we know that the CRTC isn't feeding multiple encoders!
> @@ -1443,106 +1197,6 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
> return encoder;
> }
>
> -/*
> - * Enable PCH resources required for PCH ports:
> - * - PCH PLLs
> - * - FDI training & RX/TX
> - * - update transcoder timings
> - * - DP transcoding bits
> - * - transcoder
> - */
> -static void ilk_pch_enable(const struct intel_atomic_state *state,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - enum pipe pipe = crtc->pipe;
> - u32 temp;
> -
> - assert_pch_transcoder_disabled(dev_priv, pipe);
> -
> - /* For PCH output, training FDI link */
> - intel_fdi_link_train(crtc, crtc_state);
> -
> - /* We need to program the right clock selection before writing the pixel
> - * mutliplier into the DPLL. */
> - if (HAS_PCH_CPT(dev_priv)) {
> - u32 sel;
> -
> - temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
> - temp |= TRANS_DPLL_ENABLE(pipe);
> - sel = TRANS_DPLLB_SEL(pipe);
> - if (crtc_state->shared_dpll ==
> - intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
> - temp |= sel;
> - else
> - temp &= ~sel;
> - intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
> - }
> -
> - /* XXX: pch pll's can be enabled any time before we enable the PCH
> - * transcoder, and we actually should do this to not upset any PCH
> - * transcoder that already use the clock when we share it.
> - *
> - * Note that enable_shared_dpll tries to do the right thing, but
> - * get_shared_dpll unconditionally resets the pll - we need that to have
> - * the right LVDS enable sequence. */
> - intel_enable_shared_dpll(crtc_state);
> -
> - /* set transcoder timing, panel must allow it */
> - assert_pps_unlocked(dev_priv, pipe);
> - ilk_pch_transcoder_set_timings(crtc_state, pipe);
> -
> - intel_fdi_normal_train(crtc);
> -
> - /* For PCH DP, enable TRANS_DP_CTL */
> - if (HAS_PCH_CPT(dev_priv) &&
> - intel_crtc_has_dp_encoder(crtc_state)) {
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> - u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> - i915_reg_t reg = TRANS_DP_CTL(pipe);
> - enum port port;
> -
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~(TRANS_DP_PORT_SEL_MASK |
> - TRANS_DP_SYNC_MASK |
> - TRANS_DP_BPC_MASK);
> - temp |= TRANS_DP_OUTPUT_ENABLE;
> - temp |= bpc << 9; /* same format but at 11:9 */
> -
> - if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> - temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> - temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
> -
> - port = intel_get_crtc_new_encoder(state, crtc_state)->port;
> - drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
> - temp |= TRANS_DP_PORT_SEL(port);
> -
> - intel_de_write(dev_priv, reg, temp);
> - }
> -
> - ilk_enable_pch_transcoder(crtc_state);
> -}
> -
> -void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -
> - assert_pch_transcoder_disabled(dev_priv, PIPE_A);
> -
> - lpt_program_iclkip(crtc_state);
> -
> - /* Set transcoder timing. */
> - ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
> -
> - lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
> -}
> -
> static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 39c18b8807f9..93c84f2174b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -541,8 +541,6 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
> const char *name, u32 reg, int ref_freq);
> int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
> const char *name, u32 reg);
> -void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
> -void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
> void intel_init_display_hooks(struct drm_i915_private *dev_priv);
> unsigned int intel_fb_xy_to_linear(int x, int y,
> const struct intel_plane_state *state,
> @@ -578,9 +576,6 @@ struct drm_framebuffer *
> intel_framebuffer_create(struct drm_i915_gem_object *obj,
> struct drm_mode_fb_cmd2 *mode_cmd);
>
> -void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
> - enum pipe pipe);
> -
> bool intel_fuzzy_clock_check(int clock1, int clock2);
>
> void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> new file mode 100644
> index 000000000000..0056c2fe49ec
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -0,0 +1,365 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "g4x_dp.h"
> +#include "intel_crt.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "intel_fdi.h"
> +#include "intel_lvds.h"
> +#include "intel_pch_display.h"
> +#include "intel_pch_refclk.h"
> +#include "intel_pps.h"
> +#include "intel_sdvo.h"
> +
> +static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum port port,
> + i915_reg_t dp_reg)
> +{
> + enum pipe port_pipe;
> + bool state;
> +
> + state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
> +
> + I915_STATE_WARN(state && port_pipe == pipe,
> + "PCH DP %c enabled on transcoder %c, should be disabled\n",
> + port_name(port), pipe_name(pipe));
> +
> + I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
> + "IBX PCH DP %c still using transcoder B\n",
> + port_name(port));
> +}
> +
> +static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum port port,
> + i915_reg_t hdmi_reg)
> +{
> + enum pipe port_pipe;
> + bool state;
> +
> + state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
> +
> + I915_STATE_WARN(state && port_pipe == pipe,
> + "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
> + port_name(port), pipe_name(pipe));
> +
> + I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
> + "IBX PCH HDMI %c still using transcoder B\n",
> + port_name(port));
> +}
> +
> +static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> +{
> + enum pipe port_pipe;
> +
> + assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
> + assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
> + assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
> +
> + I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
> + port_pipe == pipe,
> + "PCH VGA enabled on transcoder %c, should be disabled\n",
> + pipe_name(pipe));
> +
> + I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
> + port_pipe == pipe,
> + "PCH LVDS enabled on transcoder %c, should be disabled\n",
> + pipe_name(pipe));
> +
> + /* PCH SDVOB multiplex with HDMIB */
> + assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
> + assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
> + assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
> +}
> +
> +static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> +{
> + u32 val;
> + bool enabled;
> +
> + val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
> + enabled = !!(val & TRANS_ENABLE);
> + I915_STATE_WARN(enabled,
> + "transcoder assertion failed, should be off on pipe %c but is still active\n",
> + pipe_name(pipe));
> +}
> +
> +static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
> + enum pipe pch_transcoder)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
> + intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
> + intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
> + intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
> + intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
> + intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
> +
> + intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
> + intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
> + intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
> + intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
> + intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
> + intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
> + intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
> + intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
> +}
> +
> +static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + i915_reg_t reg;
> + u32 val, pipeconf_val;
> +
> + /* Make sure PCH DPLL is enabled */
> + assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
> +
> + /* FDI must be feeding us bits for PCH ports */
> + assert_fdi_tx_enabled(dev_priv, pipe);
> + assert_fdi_rx_enabled(dev_priv, pipe);
> +
> + if (HAS_PCH_CPT(dev_priv)) {
> + reg = TRANS_CHICKEN2(pipe);
> + val = intel_de_read(dev_priv, reg);
> + /*
> + * Workaround: Set the timing override bit
> + * before enabling the pch transcoder.
> + */
> + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> + /* Configure frame start delay to match the CPU */
> + val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> + val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
> + intel_de_write(dev_priv, reg, val);
> + }
> +
> + reg = PCH_TRANSCONF(pipe);
> + val = intel_de_read(dev_priv, reg);
> + pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
> +
> + if (HAS_PCH_IBX(dev_priv)) {
> + /* Configure frame start delay to match the CPU */
> + val &= ~TRANS_FRAME_START_DELAY_MASK;
> + val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
> +
> + /*
> + * Make the BPC in transcoder be consistent with
> + * that in pipeconf reg. For HDMI we must use 8bpc
> + * here for both 8bpc and 12bpc.
> + */
> + val &= ~PIPECONF_BPC_MASK;
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + val |= PIPECONF_8BPC;
> + else
> + val |= pipeconf_val & PIPECONF_BPC_MASK;
> + }
> +
> + val &= ~TRANS_INTERLACE_MASK;
> + if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
> + if (HAS_PCH_IBX(dev_priv) &&
> + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> + val |= TRANS_LEGACY_INTERLACED_ILK;
> + else
> + val |= TRANS_INTERLACED;
> + } else {
> + val |= TRANS_PROGRESSIVE;
> + }
> +
> + intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
> + if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
> + drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
> + pipe_name(pipe));
> +}
> +
> +void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> +{
> + i915_reg_t reg;
> + u32 val;
> +
> + /* FDI relies on the transcoder */
> + assert_fdi_tx_disabled(dev_priv, pipe);
> + assert_fdi_rx_disabled(dev_priv, pipe);
> +
> + /* Ports must be off as well */
> + assert_pch_ports_disabled(dev_priv, pipe);
> +
> + reg = PCH_TRANSCONF(pipe);
> + val = intel_de_read(dev_priv, reg);
> + val &= ~TRANS_ENABLE;
> + intel_de_write(dev_priv, reg, val);
> + /* wait for PCH transcoder off, transcoder state */
> + if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
> + drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
> + pipe_name(pipe));
> +
> + if (HAS_PCH_CPT(dev_priv)) {
> + /* Workaround: Clear the timing override chicken bit again. */
> + reg = TRANS_CHICKEN2(pipe);
> + val = intel_de_read(dev_priv, reg);
> + val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> + intel_de_write(dev_priv, reg, val);
> + }
> +}
> +
> +/*
> + * Enable PCH resources required for PCH ports:
> + * - PCH PLLs
> + * - FDI training & RX/TX
> + * - update transcoder timings
> + * - DP transcoding bits
> + * - transcoder
> + */
> +void ilk_pch_enable(const struct intel_atomic_state *state,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum pipe pipe = crtc->pipe;
> + u32 temp;
> +
> + assert_pch_transcoder_disabled(dev_priv, pipe);
> +
> + /* For PCH output, training FDI link */
> + intel_fdi_link_train(crtc, crtc_state);
> +
> + /*
> + * We need to program the right clock selection
> + * before writing the pixel multiplier into the DPLL.
> + */
> + if (HAS_PCH_CPT(dev_priv)) {
> + u32 sel;
> +
> + temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
> + temp |= TRANS_DPLL_ENABLE(pipe);
> + sel = TRANS_DPLLB_SEL(pipe);
> + if (crtc_state->shared_dpll ==
> + intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
> + temp |= sel;
> + else
> + temp &= ~sel;
> + intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
> + }
> +
> + /*
> + * XXX: pch pll's can be enabled any time before we enable the PCH
> + * transcoder, and we actually should do this to not upset any PCH
> + * transcoder that already use the clock when we share it.
> + *
> + * Note that enable_shared_dpll tries to do the right thing, but
> + * get_shared_dpll unconditionally resets the pll - we need that
> + * to have the right LVDS enable sequence.
> + */
> + intel_enable_shared_dpll(crtc_state);
> +
> + /* set transcoder timing, panel must allow it */
> + assert_pps_unlocked(dev_priv, pipe);
> + ilk_pch_transcoder_set_timings(crtc_state, pipe);
> +
> + intel_fdi_normal_train(crtc);
> +
> + /* For PCH DP, enable TRANS_DP_CTL */
> + if (HAS_PCH_CPT(dev_priv) &&
> + intel_crtc_has_dp_encoder(crtc_state)) {
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> + i915_reg_t reg = TRANS_DP_CTL(pipe);
> + enum port port;
> +
> + temp = intel_de_read(dev_priv, reg);
> + temp &= ~(TRANS_DP_PORT_SEL_MASK |
> + TRANS_DP_SYNC_MASK |
> + TRANS_DP_BPC_MASK);
> + temp |= TRANS_DP_OUTPUT_ENABLE;
> + temp |= bpc << 9; /* same format but at 11:9 */
> +
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> + temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> + temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
> +
> + port = intel_get_crtc_new_encoder(state, crtc_state)->port;
> + drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
> + temp |= TRANS_DP_PORT_SEL(port);
> +
> + intel_de_write(dev_priv, reg, temp);
> + }
> +
> + ilk_enable_pch_transcoder(crtc_state);
> +}
> +
> +static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> + enum transcoder cpu_transcoder)
> +{
> + u32 val, pipeconf_val;
> +
> + /* FDI must be feeding us bits for PCH ports */
> + assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> + assert_fdi_rx_enabled(dev_priv, PIPE_A);
> +
> + val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
> + /* Workaround: set timing override bit. */
> + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> + /* Configure frame start delay to match the CPU */
> + val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> + val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
> + intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
> +
> + val = TRANS_ENABLE;
> + pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
> +
> + if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> + PIPECONF_INTERLACED_ILK)
> + val |= TRANS_INTERLACED;
> + else
> + val |= TRANS_PROGRESSIVE;
> +
> + intel_de_write(dev_priv, LPT_TRANSCONF, val);
> + if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
> + TRANS_STATE_ENABLE, 100))
> + drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
> +}
> +
> +void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + val = intel_de_read(dev_priv, LPT_TRANSCONF);
> + val &= ~TRANS_ENABLE;
> + intel_de_write(dev_priv, LPT_TRANSCONF, val);
> + /* wait for PCH transcoder off, transcoder state */
> + if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
> + TRANS_STATE_ENABLE, 50))
> + drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
> +
> + /* Workaround: clear timing override bit. */
> + val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
> + val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> + intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
> +}
> +
> +void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + assert_pch_transcoder_disabled(dev_priv, PIPE_A);
> +
> + lpt_program_iclkip(crtc_state);
> +
> + /* Set transcoder timing. */
> + ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
> +
> + lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
> new file mode 100644
> index 000000000000..6eba1fd667ea
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_PCH_DISPLAY_H_
> +#define _INTEL_PCH_DISPLAY_H_
> +
> +enum pipe;
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_crtc_state;
> +
> +void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> + enum pipe pipe);
> +void ilk_pch_enable(const struct intel_atomic_state *state,
> + const struct intel_crtc_state *crtc_state);
> +
> +void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
> +void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
> +
> +#endif
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 3/9] drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
2021-10-15 7:16 ` [Intel-gfx] [PATCH 1/9] drm/i915: Move PCH refclok stuff " Ville Syrjala
2021-10-15 7:16 ` [Intel-gfx] [PATCH 2/9] drm/i915: Move PCH modeset code to " Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-17 23:58 ` David Airlie
2021-10-15 7:16 ` [Intel-gfx] [PATCH 4/9] drm/i915: Move LPT PCH readout code Ville Syrjala
` (13 subsequent siblings)
16 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use the clean "atomic_state+crtc" approach of passing
arguments to the top level PCH modeset code.
And while at it we can also just pass the whole crtc to
ilk_disable_pch_transcoder().
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_pch_display.c | 23 +++++++++++--------
.../gpu/drm/i915/display/intel_pch_display.h | 12 +++++-----
4 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 54540138bd1d..4038ae342ea1 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -318,7 +318,7 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
intel_enable_transcoder(crtc_state);
- lpt_pch_enable(crtc_state);
+ lpt_pch_enable(state, crtc);
intel_crtc_vblank_on(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 69549886fe5b..2ee02c16bd1c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2020,7 +2020,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
intel_enable_transcoder(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
- ilk_pch_enable(state, new_crtc_state);
+ ilk_pch_enable(state, crtc);
intel_crtc_vblank_on(new_crtc_state);
@@ -2299,7 +2299,7 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
intel_encoders_post_disable(state, crtc);
if (old_crtc_state->has_pch_encoder) {
- ilk_disable_pch_transcoder(dev_priv, pipe);
+ ilk_disable_pch_transcoder(crtc);
if (HAS_PCH_CPT(dev_priv)) {
i915_reg_t reg;
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 0056c2fe49ec..50995c4f2aaa 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -179,9 +179,10 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
pipe_name(pipe));
}
-void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe)
+void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 val;
@@ -218,12 +219,12 @@ void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
* - DP transcoding bits
* - transcoder
*/
-void ilk_pch_enable(const struct intel_atomic_state *state,
- const struct intel_crtc_state *crtc_state)
+void ilk_pch_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
u32 temp;
@@ -289,7 +290,7 @@ void ilk_pch_enable(const struct intel_atomic_state *state,
temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
port = intel_get_crtc_new_encoder(state, crtc_state)->port;
- drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
+ drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
temp |= TRANS_DP_PORT_SEL(port);
intel_de_write(dev_priv, reg, temp);
@@ -348,10 +349,12 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
}
-void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
+void lpt_pch_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
assert_pch_transcoder_disabled(dev_priv, PIPE_A);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 6eba1fd667ea..7f9df2c13cf3 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -6,17 +6,17 @@
#ifndef _INTEL_PCH_DISPLAY_H_
#define _INTEL_PCH_DISPLAY_H_
-enum pipe;
struct drm_i915_private;
struct intel_atomic_state;
+struct intel_crtc;
struct intel_crtc_state;
-void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe);
-void ilk_pch_enable(const struct intel_atomic_state *state,
- const struct intel_crtc_state *crtc_state);
+void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
+void ilk_pch_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
-void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
+void lpt_pch_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 3/9] drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention
2021-10-15 7:16 ` [Intel-gfx] [PATCH 3/9] drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention Ville Syrjala
@ 2021-10-17 23:58 ` David Airlie
0 siblings, 0 replies; 39+ messages in thread
From: David Airlie @ 2021-10-17 23:58 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the clean "atomic_state+crtc" approach of passing
> arguments to the top level PCH modeset code.
>
> And while at it we can also just pass the whole crtc to
> ilk_disable_pch_transcoder().
Some minor whitespace:
> + intel_atomic_get_new_crtc_state(state, crtc);
There are a few of these with two spaces after the ,
with those fixed up.
Reviewed-by: Dave Airlie <airlied@redhat.com>
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> .../gpu/drm/i915/display/intel_pch_display.c | 23 +++++++++++--------
> .../gpu/drm/i915/display/intel_pch_display.h | 12 +++++-----
> 4 files changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 54540138bd1d..4038ae342ea1 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -318,7 +318,7 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
>
> intel_enable_transcoder(crtc_state);
>
> - lpt_pch_enable(crtc_state);
> + lpt_pch_enable(state, crtc);
>
> intel_crtc_vblank_on(crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 69549886fe5b..2ee02c16bd1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2020,7 +2020,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
> intel_enable_transcoder(new_crtc_state);
>
> if (new_crtc_state->has_pch_encoder)
> - ilk_pch_enable(state, new_crtc_state);
> + ilk_pch_enable(state, crtc);
>
> intel_crtc_vblank_on(new_crtc_state);
>
> @@ -2299,7 +2299,7 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
> intel_encoders_post_disable(state, crtc);
>
> if (old_crtc_state->has_pch_encoder) {
> - ilk_disable_pch_transcoder(dev_priv, pipe);
> + ilk_disable_pch_transcoder(crtc);
>
> if (HAS_PCH_CPT(dev_priv)) {
> i915_reg_t reg;
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 0056c2fe49ec..50995c4f2aaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -179,9 +179,10 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> pipe_name(pipe));
> }
>
> -void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> +void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> i915_reg_t reg;
> u32 val;
>
> @@ -218,12 +219,12 @@ void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> * - DP transcoding bits
> * - transcoder
> */
> -void ilk_pch_enable(const struct intel_atomic_state *state,
> - const struct intel_crtc_state *crtc_state)
> +void ilk_pch_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> enum pipe pipe = crtc->pipe;
> u32 temp;
>
> @@ -289,7 +290,7 @@ void ilk_pch_enable(const struct intel_atomic_state *state,
> temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
>
> port = intel_get_crtc_new_encoder(state, crtc_state)->port;
> - drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
> + drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
> temp |= TRANS_DP_PORT_SEL(port);
>
> intel_de_write(dev_priv, reg, temp);
> @@ -348,10 +349,12 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
> intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
> }
>
> -void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
> +void lpt_pch_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> assert_pch_transcoder_disabled(dev_priv, PIPE_A);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
> index 6eba1fd667ea..7f9df2c13cf3 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
> @@ -6,17 +6,17 @@
> #ifndef _INTEL_PCH_DISPLAY_H_
> #define _INTEL_PCH_DISPLAY_H_
>
> -enum pipe;
> struct drm_i915_private;
> struct intel_atomic_state;
> +struct intel_crtc;
> struct intel_crtc_state;
>
> -void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> - enum pipe pipe);
> -void ilk_pch_enable(const struct intel_atomic_state *state,
> - const struct intel_crtc_state *crtc_state);
> +void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
> +void ilk_pch_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
>
> void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
> -void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
> +void lpt_pch_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
>
> #endif
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 4/9] drm/i915: Move LPT PCH readout code
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (2 preceding siblings ...)
2021-10-15 7:16 ` [Intel-gfx] [PATCH 3/9] drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-18 0:19 ` David Airlie
2021-10-18 15:35 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-10-15 7:16 ` [Intel-gfx] [PATCH 5/9] drm/i915: Extract ilk_pch_get_config() Ville Syrjala
` (12 subsequent siblings)
16 siblings, 2 replies; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Nuke the hsw_get_ddi_port_state() eyesore by putting the
readout code into intel_pch_display.c, and calling it directly
from hsw_crt_get_config().
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 46 ++-----------------
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../gpu/drm/i915/display/intel_pch_display.c | 18 ++++++++
.../gpu/drm/i915/display/intel_pch_display.h | 1 +
5 files changed, 26 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 4038ae342ea1..03cfae46f92f 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -147,6 +147,8 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ lpt_pch_get_config(pipe_config);
+
hsw_ddi_get_config(encoder, pipe_config);
pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2ee02c16bd1c..8f65b8b6a306 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4090,8 +4090,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
&pipe_config->dp_m2_n2);
}
-static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
&pipe_config->fdi_m_n, NULL);
@@ -4486,45 +4486,6 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
return transcoder_is_dsi(pipe_config->cpu_transcoder);
}
-static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- enum port port;
- u32 tmp;
-
- if (transcoder_is_dsi(cpu_transcoder)) {
- port = (cpu_transcoder == TRANSCODER_DSI_A) ?
- PORT_A : PORT_B;
- } else {
- tmp = intel_de_read(dev_priv,
- TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if (!(tmp & TRANS_DDI_FUNC_ENABLE))
- return;
- if (DISPLAY_VER(dev_priv) >= 12)
- port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
- else
- port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
- }
-
- /*
- * Haswell has only FDI/PCH transcoder A. It is which is connected to
- * DDI E. So just check whether this pipe is wired to DDI E and whether
- * the PCH transcoder is on.
- */
- if (DISPLAY_VER(dev_priv) < 9 &&
- (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
- pipe_config->has_pch_encoder = true;
-
- tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
- FDI_DP_PORT_WIDTH_SHIFT) + 1;
-
- ilk_get_fdi_m_n_config(crtc, pipe_config);
- }
-}
-
static bool hsw_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -4562,8 +4523,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
/* we cannot read out most state, so don't bother.. */
pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
} else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
- DISPLAY_VER(dev_priv) >= 11) {
- hsw_get_ddi_port_state(crtc, pipe_config);
+ DISPLAY_VER(dev_priv) >= 11) {
intel_get_transcoder_timings(crtc, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 93c84f2174b5..5bc8d8913178 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -584,6 +584,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
enum link_m_n_set m_n);
+void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 50995c4f2aaa..df7195ed1aaa 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -366,3 +366,21 @@ void lpt_pch_enable(struct intel_atomic_state *state,
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
+
+void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 tmp;
+
+ if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
+ return;
+
+ crtc_state->has_pch_encoder = true;
+
+ tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
+ crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
+ FDI_DP_PORT_WIDTH_SHIFT) + 1;
+
+ ilk_get_fdi_m_n_config(crtc, crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 7f9df2c13cf3..e0ff331c0bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -18,5 +18,6 @@ void ilk_pch_enable(struct intel_atomic_state *state,
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
void lpt_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 4/9] drm/i915: Move LPT PCH readout code
2021-10-15 7:16 ` [Intel-gfx] [PATCH 4/9] drm/i915: Move LPT PCH readout code Ville Syrjala
@ 2021-10-18 0:19 ` David Airlie
2021-10-18 7:15 ` Ville Syrjälä
2021-10-18 15:35 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
1 sibling, 1 reply; 39+ messages in thread
From: David Airlie @ 2021-10-18 0:19 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Nuke the hsw_get_ddi_port_state() eyesore by putting the
> readout code into intel_pch_display.c, and calling it directly
> from hsw_crt_get_config().
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 46 ++-----------------
> drivers/gpu/drm/i915/display/intel_display.h | 2 +
> .../gpu/drm/i915/display/intel_pch_display.c | 18 ++++++++
> .../gpu/drm/i915/display/intel_pch_display.h | 1 +
> 5 files changed, 26 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 4038ae342ea1..03cfae46f92f 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -147,6 +147,8 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> + lpt_pch_get_config(pipe_config);
> +
> hsw_ddi_get_config(encoder, pipe_config);
>
> pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2ee02c16bd1c..8f65b8b6a306 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4090,8 +4090,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> &pipe_config->dp_m2_n2);
> }
>
> -static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> +void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> {
> intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> &pipe_config->fdi_m_n, NULL);
> @@ -4486,45 +4486,6 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
> return transcoder_is_dsi(pipe_config->cpu_transcoder);
> }
>
> -static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> - enum port port;
> - u32 tmp;
> -
> - if (transcoder_is_dsi(cpu_transcoder)) {
> - port = (cpu_transcoder == TRANSCODER_DSI_A) ?
> - PORT_A : PORT_B;
> - } else {
> - tmp = intel_de_read(dev_priv,
> - TRANS_DDI_FUNC_CTL(cpu_transcoder));
> - if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> - return;
> - if (DISPLAY_VER(dev_priv) >= 12)
> - port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> - else
> - port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> - }
Where does thie code go? is it necessary, maybe make a precursor patch
showing why this isn't needed?
or just more commentary on why it's not needed anymore, since PORT_E
is hardcoded to the crt?
This is also the only use of those two macros
*DDI_FUNC_CTL_VAL_TO_PORT(tmp), should those be nuked as well?
Dave.
> -
> - /*
> - * Haswell has only FDI/PCH transcoder A. It is which is connected to
> - * DDI E. So just check whether this pipe is wired to DDI E and whether
> - * the PCH transcoder is on.
> - */
> - if (DISPLAY_VER(dev_priv) < 9 &&
> - (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
> - pipe_config->has_pch_encoder = true;
> -
> - tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> - pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> - FDI_DP_PORT_WIDTH_SHIFT) + 1;
> -
> - ilk_get_fdi_m_n_config(crtc, pipe_config);
> - }
> -}
> -
> static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> @@ -4562,8 +4523,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> /* we cannot read out most state, so don't bother.. */
> pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> - DISPLAY_VER(dev_priv) >= 11) {
> - hsw_get_ddi_port_state(crtc, pipe_config);
> + DISPLAY_VER(dev_priv) >= 11) {
> intel_get_transcoder_timings(crtc, pipe_config);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 93c84f2174b5..5bc8d8913178 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -584,6 +584,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> enum link_m_n_set m_n);
> +void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config);
> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>
> bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 50995c4f2aaa..df7195ed1aaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -366,3 +366,21 @@ void lpt_pch_enable(struct intel_atomic_state *state,
>
> lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
> }
> +
> +void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 tmp;
> +
> + if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
> + return;
> +
> + crtc_state->has_pch_encoder = true;
> +
> + tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> + crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> + FDI_DP_PORT_WIDTH_SHIFT) + 1;
> +
> + ilk_get_fdi_m_n_config(crtc, crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
> index 7f9df2c13cf3..e0ff331c0bc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
> @@ -18,5 +18,6 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
> void lpt_pch_enable(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> +void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
>
> #endif
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 4/9] drm/i915: Move LPT PCH readout code
2021-10-18 0:19 ` David Airlie
@ 2021-10-18 7:15 ` Ville Syrjälä
0 siblings, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2021-10-18 7:15 UTC (permalink / raw)
To: David Airlie; +Cc: Development, Intel, Jani Nikula
On Mon, Oct 18, 2021 at 10:19:31AM +1000, David Airlie wrote:
> On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Nuke the hsw_get_ddi_port_state() eyesore by putting the
> > readout code into intel_pch_display.c, and calling it directly
> > from hsw_crt_get_config().
> >
> > Cc: Dave Airlie <airlied@redhat.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_crt.c | 2 +
> > drivers/gpu/drm/i915/display/intel_display.c | 46 ++-----------------
> > drivers/gpu/drm/i915/display/intel_display.h | 2 +
> > .../gpu/drm/i915/display/intel_pch_display.c | 18 ++++++++
> > .../gpu/drm/i915/display/intel_pch_display.h | 1 +
> > 5 files changed, 26 insertions(+), 43 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> > index 4038ae342ea1..03cfae46f92f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -147,6 +147,8 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
> > {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >
> > + lpt_pch_get_config(pipe_config);
> > +
> > hsw_ddi_get_config(encoder, pipe_config);
> >
> > pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 2ee02c16bd1c..8f65b8b6a306 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4090,8 +4090,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> > &pipe_config->dp_m2_n2);
> > }
> >
> > -static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
> > - struct intel_crtc_state *pipe_config)
> > +void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
> > + struct intel_crtc_state *pipe_config)
> > {
> > intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> > &pipe_config->fdi_m_n, NULL);
> > @@ -4486,45 +4486,6 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
> > return transcoder_is_dsi(pipe_config->cpu_transcoder);
> > }
> >
> > -static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> > - struct intel_crtc_state *pipe_config)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > - enum port port;
> > - u32 tmp;
> > -
> > - if (transcoder_is_dsi(cpu_transcoder)) {
> > - port = (cpu_transcoder == TRANSCODER_DSI_A) ?
> > - PORT_A : PORT_B;
> > - } else {
> > - tmp = intel_de_read(dev_priv,
> > - TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > - if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> > - return;
> > - if (DISPLAY_VER(dev_priv) >= 12)
> > - port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> > - else
> > - port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> > - }
>
> Where does thie code go? is it necessary, maybe make a precursor patch
> showing why this isn't needed?
> or just more commentary on why it's not needed anymore, since PORT_E
> is hardcoded to the crt?
Yeah, since the thing is now called from encoder->get_config() we
already know we're dealing with the correct port. This code was
called from a place where it had no idea which port we were driving
so it had to check manually. I'll amend the commit message a bit.
>
> This is also the only use of those two macros
> *DDI_FUNC_CTL_VAL_TO_PORT(tmp), should those be nuked as well?
Probably. If someone needs them in the future they can just
reimplement using REG_FIELD_GET().
Thanks.
>
> Dave.
>
> > -
> > - /*
> > - * Haswell has only FDI/PCH transcoder A. It is which is connected to
> > - * DDI E. So just check whether this pipe is wired to DDI E and whether
> > - * the PCH transcoder is on.
> > - */
> > - if (DISPLAY_VER(dev_priv) < 9 &&
> > - (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
> > - pipe_config->has_pch_encoder = true;
> > -
> > - tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> > - pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> > - FDI_DP_PORT_WIDTH_SHIFT) + 1;
> > -
> > - ilk_get_fdi_m_n_config(crtc, pipe_config);
> > - }
> > -}
> > -
> > static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > struct intel_crtc_state *pipe_config)
> > {
> > @@ -4562,8 +4523,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > /* we cannot read out most state, so don't bother.. */
> > pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> > } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > - DISPLAY_VER(dev_priv) >= 11) {
> > - hsw_get_ddi_port_state(crtc, pipe_config);
> > + DISPLAY_VER(dev_priv) >= 11) {
> > intel_get_transcoder_timings(crtc, pipe_config);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > index 93c84f2174b5..5bc8d8913178 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -584,6 +584,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> > struct intel_crtc_state *pipe_config);
> > void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> > enum link_m_n_set m_n);
> > +void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
> > + struct intel_crtc_state *pipe_config);
> > int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> >
> > bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index 50995c4f2aaa..df7195ed1aaa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -366,3 +366,21 @@ void lpt_pch_enable(struct intel_atomic_state *state,
> >
> > lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
> > }
> > +
> > +void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + u32 tmp;
> > +
> > + if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
> > + return;
> > +
> > + crtc_state->has_pch_encoder = true;
> > +
> > + tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> > + crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> > + FDI_DP_PORT_WIDTH_SHIFT) + 1;
> > +
> > + ilk_get_fdi_m_n_config(crtc, crtc_state);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
> > index 7f9df2c13cf3..e0ff331c0bc6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
> > @@ -18,5 +18,6 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> > void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
> > void lpt_pch_enable(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > +void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
> >
> > #endif
> > --
> > 2.32.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 4/9] drm/i915: Move LPT PCH readout code
2021-10-15 7:16 ` [Intel-gfx] [PATCH 4/9] drm/i915: Move LPT PCH readout code Ville Syrjala
2021-10-18 0:19 ` David Airlie
@ 2021-10-18 15:35 ` Ville Syrjala
2021-10-18 19:46 ` David Airlie
1 sibling, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-18 15:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Nuke the hsw_get_ddi_port_state() eyesore by putting the
readout code into intel_pch_display.c, and calling it directly
from hsw_crt_get_config().
Note that the nuked TRANS_DDI_FUNC_CTL readout from
hsw_get_ddi_port_state() is now etirely redundant since we
get called from the encoder->get_config() so we already know
we're dealing with the correct DDI port. Previously the
code was called from a place where that wasn't known so
it had to checked manually.
v2: Clarify the TRANS_DDI_FUNC_CTL change (Dave)
Nuke the now unused *TRANS_DDI_FUNC_CTL_VAL_TO_PORT() (Dave)
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 46 ++-----------------
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../gpu/drm/i915/display/intel_pch_display.c | 18 ++++++++
.../gpu/drm/i915/display/intel_pch_display.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 -
6 files changed, 26 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 4038ae342ea1..03cfae46f92f 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -147,6 +147,8 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ lpt_pch_get_config(pipe_config);
+
hsw_ddi_get_config(encoder, pipe_config);
pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2ee02c16bd1c..8f65b8b6a306 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4090,8 +4090,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
&pipe_config->dp_m2_n2);
}
-static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
&pipe_config->fdi_m_n, NULL);
@@ -4486,45 +4486,6 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
return transcoder_is_dsi(pipe_config->cpu_transcoder);
}
-static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- enum port port;
- u32 tmp;
-
- if (transcoder_is_dsi(cpu_transcoder)) {
- port = (cpu_transcoder == TRANSCODER_DSI_A) ?
- PORT_A : PORT_B;
- } else {
- tmp = intel_de_read(dev_priv,
- TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if (!(tmp & TRANS_DDI_FUNC_ENABLE))
- return;
- if (DISPLAY_VER(dev_priv) >= 12)
- port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
- else
- port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
- }
-
- /*
- * Haswell has only FDI/PCH transcoder A. It is which is connected to
- * DDI E. So just check whether this pipe is wired to DDI E and whether
- * the PCH transcoder is on.
- */
- if (DISPLAY_VER(dev_priv) < 9 &&
- (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
- pipe_config->has_pch_encoder = true;
-
- tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
- FDI_DP_PORT_WIDTH_SHIFT) + 1;
-
- ilk_get_fdi_m_n_config(crtc, pipe_config);
- }
-}
-
static bool hsw_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -4562,8 +4523,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
/* we cannot read out most state, so don't bother.. */
pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
} else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
- DISPLAY_VER(dev_priv) >= 11) {
- hsw_get_ddi_port_state(crtc, pipe_config);
+ DISPLAY_VER(dev_priv) >= 11) {
intel_get_transcoder_timings(crtc, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 93c84f2174b5..5bc8d8913178 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -584,6 +584,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
enum link_m_n_set m_n);
+void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 50995c4f2aaa..df7195ed1aaa 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -366,3 +366,21 @@ void lpt_pch_enable(struct intel_atomic_state *state,
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
+
+void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 tmp;
+
+ if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
+ return;
+
+ crtc_state->has_pch_encoder = true;
+
+ tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
+ crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
+ FDI_DP_PORT_WIDTH_SHIFT) + 1;
+
+ ilk_get_fdi_m_n_config(crtc, crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 7f9df2c13cf3..e0ff331c0bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -18,5 +18,6 @@ void ilk_pch_enable(struct intel_atomic_state *state,
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
void lpt_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da9055c3ebf0..9a89565fd458 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10212,8 +10212,6 @@ enum skl_power_gate {
#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
-#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
-#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: Move LPT PCH readout code
2021-10-18 15:35 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2021-10-18 19:46 ` David Airlie
2021-10-19 7:17 ` Ville Syrjälä
0 siblings, 1 reply; 39+ messages in thread
From: David Airlie @ 2021-10-18 19:46 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Tue, Oct 19, 2021 at 1:35 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Nuke the hsw_get_ddi_port_state() eyesore by putting the
> readout code into intel_pch_display.c, and calling it directly
> from hsw_crt_get_config().
>
> Note that the nuked TRANS_DDI_FUNC_CTL readout from
> hsw_get_ddi_port_state() is now etirely redundant since we
> get called from the encoder->get_config() so we already know
> we're dealing with the correct DDI port. Previously the
> code was called from a place where that wasn't known so
> it had to checked manually.
>
> v2: Clarify the TRANS_DDI_FUNC_CTL change (Dave)
> Nuke the now unused *TRANS_DDI_FUNC_CTL_VAL_TO_PORT() (Dave)
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: Move LPT PCH readout code
2021-10-18 19:46 ` David Airlie
@ 2021-10-19 7:17 ` Ville Syrjälä
0 siblings, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2021-10-19 7:17 UTC (permalink / raw)
To: David Airlie; +Cc: Development, Intel, Jani Nikula
On Tue, Oct 19, 2021 at 05:46:33AM +1000, David Airlie wrote:
> On Tue, Oct 19, 2021 at 1:35 AM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Nuke the hsw_get_ddi_port_state() eyesore by putting the
> > readout code into intel_pch_display.c, and calling it directly
> > from hsw_crt_get_config().
> >
> > Note that the nuked TRANS_DDI_FUNC_CTL readout from
> > hsw_get_ddi_port_state() is now etirely redundant since we
> > get called from the encoder->get_config() so we already know
> > we're dealing with the correct DDI port. Previously the
> > code was called from a place where that wasn't known so
> > it had to checked manually.
> >
> > v2: Clarify the TRANS_DDI_FUNC_CTL change (Dave)
> > Nuke the now unused *TRANS_DDI_FUNC_CTL_VAL_TO_PORT() (Dave)
> >
> > Cc: Dave Airlie <airlied@redhat.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Dave Airlie <airlied@redhat.com>
Thanks for the review. Fixed up all the (known) typos and robot
noises, and pushed to drm-intel-next.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 5/9] drm/i915: Extract ilk_pch_get_config()
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (3 preceding siblings ...)
2021-10-15 7:16 ` [Intel-gfx] [PATCH 4/9] drm/i915: Move LPT PCH readout code Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-18 0:22 ` David Airlie
2021-10-15 7:16 ` [Intel-gfx] [PATCH 6/9] drm/i915: Move iCLKIP readout to the pch code Ville Syrjala
` (11 subsequent siblings)
16 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the ilk+ PCH state readout into its own function and relocate
to the appropriate file.
The clock readout parts are perhaps a bit iffy since we depend
on the gmch DPLL readout code. But we can think about the clock
readout big picture later.
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 72 ++-----------------
drivers/gpu/drm/i915/display/intel_display.h | 3 +-
.../gpu/drm/i915/display/intel_pch_display.c | 68 ++++++++++++++++++
.../gpu/drm/i915/display/intel_pch_display.h | 1 +
4 files changed, 75 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8f65b8b6a306..e8f15fb3ed07 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -113,11 +113,6 @@
#include "skl_universal_plane.h"
#include "vlv_sideband.h"
-static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config);
-static void ilk_pch_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config);
-
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -4228,50 +4223,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
i9xx_get_pipe_color_config(pipe_config);
intel_color_get_config(pipe_config);
- if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
- struct intel_shared_dpll *pll;
- enum intel_dpll_id pll_id;
- bool pll_active;
+ pipe_config->pixel_multiplier = 1;
- pipe_config->has_pch_encoder = true;
-
- tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
- pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
- FDI_DP_PORT_WIDTH_SHIFT) + 1;
-
- ilk_get_fdi_m_n_config(crtc, pipe_config);
-
- if (HAS_PCH_IBX(dev_priv)) {
- /*
- * The pipe->pch transcoder and pch transcoder->pll
- * mapping is fixed.
- */
- pll_id = (enum intel_dpll_id) crtc->pipe;
- } else {
- tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
- if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
- pll_id = DPLL_ID_PCH_PLL_B;
- else
- pll_id= DPLL_ID_PCH_PLL_A;
- }
-
- pipe_config->shared_dpll =
- intel_get_shared_dpll_by_id(dev_priv, pll_id);
- pll = pipe_config->shared_dpll;
-
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
- &pipe_config->dpll_hw_state);
- drm_WARN_ON(dev, !pll_active);
-
- tmp = pipe_config->dpll_hw_state.dpll;
- pipe_config->pixel_multiplier =
- ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
- >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
-
- ilk_pch_clock_get(crtc, pipe_config);
- } else {
- pipe_config->pixel_multiplier = 1;
- }
+ ilk_pch_get_config(pipe_config);
intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
@@ -4854,8 +4808,8 @@ static int i9xx_pll_refclk(struct drm_device *dev,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4965,24 +4919,6 @@ int intel_dotclock_calculate(int link_freq,
return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
}
-static void ilk_pch_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
- /* read out port_clock from the DPLL */
- i9xx_crtc_clock_get(crtc, pipe_config);
-
- /*
- * In case there is an active pipe without active ports,
- * we may need some idea for the dotclock anyway.
- * Calculate one based on the FDI configuration.
- */
- pipe_config->hw.adjusted_mode.crtc_clock =
- intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
- &pipe_config->fdi_m_n);
-}
-
/* Returns the currently programmed mode of the given encoder. */
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 5bc8d8913178..c2efba7c6c17 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -586,8 +586,9 @@ void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
enum link_m_n_set m_n);
void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
+void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
-
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index df7195ed1aaa..f3edabdd0a4c 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -299,6 +299,74 @@ void ilk_pch_enable(struct intel_atomic_state *state,
ilk_enable_pch_transcoder(crtc_state);
}
+static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ /* read out port_clock from the DPLL */
+ i9xx_crtc_clock_get(crtc, crtc_state);
+
+ /*
+ * In case there is an active pipe without active ports,
+ * we may need some idea for the dotclock anyway.
+ * Calculate one based on the FDI configuration.
+ */
+ crtc_state->hw.adjusted_mode.crtc_clock =
+ intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
+ &crtc_state->fdi_m_n);
+}
+
+void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_shared_dpll *pll;
+ enum pipe pipe = crtc->pipe;
+ enum intel_dpll_id pll_id;
+ bool pll_active;
+ u32 tmp;
+
+ if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
+ return;
+
+ crtc_state->has_pch_encoder = true;
+
+ tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
+ crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
+ FDI_DP_PORT_WIDTH_SHIFT) + 1;
+
+ ilk_get_fdi_m_n_config(crtc, crtc_state);
+
+ if (HAS_PCH_IBX(dev_priv)) {
+ /*
+ * The pipe->pch transcoder and pch transcoder->pll
+ * mapping is fixed.
+ */
+ pll_id = (enum intel_dpll_id) pipe;
+ } else {
+ tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+ if (tmp & TRANS_DPLLB_SEL(pipe))
+ pll_id = DPLL_ID_PCH_PLL_B;
+ else
+ pll_id = DPLL_ID_PCH_PLL_A;
+ }
+
+ crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+ pll = crtc_state->shared_dpll;
+
+ pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+ &crtc_state->dpll_hw_state);
+ drm_WARN_ON(&dev_priv->drm, !pll_active);
+
+ tmp = crtc_state->dpll_hw_state.dpll;
+ crtc_state->pixel_multiplier =
+ ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
+ >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
+
+ ilk_pch_clock_get(crtc_state);
+}
+
static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder)
{
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index e0ff331c0bc6..6e834fbebd64 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -14,6 +14,7 @@ struct intel_crtc_state;
void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
void ilk_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
void lpt_pch_enable(struct intel_atomic_state *state,
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Extract ilk_pch_get_config()
2021-10-15 7:16 ` [Intel-gfx] [PATCH 5/9] drm/i915: Extract ilk_pch_get_config() Ville Syrjala
@ 2021-10-18 0:22 ` David Airlie
0 siblings, 0 replies; 39+ messages in thread
From: David Airlie @ 2021-10-18 0:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:16 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the ilk+ PCH state readout into its own function and relocate
> to the appropriate file.
>
> The clock readout parts are perhaps a bit iffy since we depend
> on the gmch DPLL readout code. But we can think about the clock
> readout big picture later.
Looks good,
Reviewed-by: Dave Airlie <airlied@redhat.com>
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 72 ++-----------------
> drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 68 ++++++++++++++++++
> .../gpu/drm/i915/display/intel_pch_display.h | 1 +
> 4 files changed, 75 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8f65b8b6a306..e8f15fb3ed07 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -113,11 +113,6 @@
> #include "skl_universal_plane.h"
> #include "vlv_sideband.h"
>
> -static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config);
> -static void ilk_pch_clock_get(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config);
> -
> static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
> static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> @@ -4228,50 +4223,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> i9xx_get_pipe_color_config(pipe_config);
> intel_color_get_config(pipe_config);
>
> - if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id pll_id;
> - bool pll_active;
> + pipe_config->pixel_multiplier = 1;
>
> - pipe_config->has_pch_encoder = true;
> -
> - tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
> - pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> - FDI_DP_PORT_WIDTH_SHIFT) + 1;
> -
> - ilk_get_fdi_m_n_config(crtc, pipe_config);
> -
> - if (HAS_PCH_IBX(dev_priv)) {
> - /*
> - * The pipe->pch transcoder and pch transcoder->pll
> - * mapping is fixed.
> - */
> - pll_id = (enum intel_dpll_id) crtc->pipe;
> - } else {
> - tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
> - if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
> - pll_id = DPLL_ID_PCH_PLL_B;
> - else
> - pll_id= DPLL_ID_PCH_PLL_A;
> - }
> -
> - pipe_config->shared_dpll =
> - intel_get_shared_dpll_by_id(dev_priv, pll_id);
> - pll = pipe_config->shared_dpll;
> -
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &pipe_config->dpll_hw_state);
> - drm_WARN_ON(dev, !pll_active);
> -
> - tmp = pipe_config->dpll_hw_state.dpll;
> - pipe_config->pixel_multiplier =
> - ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
> - >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
> -
> - ilk_pch_clock_get(crtc, pipe_config);
> - } else {
> - pipe_config->pixel_multiplier = 1;
> - }
> + ilk_pch_get_config(pipe_config);
>
> intel_get_transcoder_timings(crtc, pipe_config);
> intel_get_pipe_src_size(crtc, pipe_config);
> @@ -4854,8 +4808,8 @@ static int i9xx_pll_refclk(struct drm_device *dev,
> }
>
> /* Returns the clock of the currently programmed mode of the given pipe. */
> -static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> +void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -4965,24 +4919,6 @@ int intel_dotclock_calculate(int link_freq,
> return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
> }
>
> -static void ilk_pch_clock_get(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -
> - /* read out port_clock from the DPLL */
> - i9xx_crtc_clock_get(crtc, pipe_config);
> -
> - /*
> - * In case there is an active pipe without active ports,
> - * we may need some idea for the dotclock anyway.
> - * Calculate one based on the FDI configuration.
> - */
> - pipe_config->hw.adjusted_mode.crtc_clock =
> - intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
> - &pipe_config->fdi_m_n);
> -}
> -
> /* Returns the currently programmed mode of the given encoder. */
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 5bc8d8913178..c2efba7c6c17 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -586,8 +586,9 @@ void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> enum link_m_n_set m_n);
> void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> +void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config);
> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> -
> bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
> void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index df7195ed1aaa..f3edabdd0a4c 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -299,6 +299,74 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> ilk_enable_pch_transcoder(crtc_state);
> }
>
> +static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + /* read out port_clock from the DPLL */
> + i9xx_crtc_clock_get(crtc, crtc_state);
> +
> + /*
> + * In case there is an active pipe without active ports,
> + * we may need some idea for the dotclock anyway.
> + * Calculate one based on the FDI configuration.
> + */
> + crtc_state->hw.adjusted_mode.crtc_clock =
> + intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
> + &crtc_state->fdi_m_n);
> +}
> +
> +void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_shared_dpll *pll;
> + enum pipe pipe = crtc->pipe;
> + enum intel_dpll_id pll_id;
> + bool pll_active;
> + u32 tmp;
> +
> + if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
> + return;
> +
> + crtc_state->has_pch_encoder = true;
> +
> + tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
> + crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> + FDI_DP_PORT_WIDTH_SHIFT) + 1;
> +
> + ilk_get_fdi_m_n_config(crtc, crtc_state);
> +
> + if (HAS_PCH_IBX(dev_priv)) {
> + /*
> + * The pipe->pch transcoder and pch transcoder->pll
> + * mapping is fixed.
> + */
> + pll_id = (enum intel_dpll_id) pipe;
> + } else {
> + tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
> + if (tmp & TRANS_DPLLB_SEL(pipe))
> + pll_id = DPLL_ID_PCH_PLL_B;
> + else
> + pll_id = DPLL_ID_PCH_PLL_A;
> + }
> +
> + crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
> + pll = crtc_state->shared_dpll;
> +
> + pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> + &crtc_state->dpll_hw_state);
> + drm_WARN_ON(&dev_priv->drm, !pll_active);
> +
> + tmp = crtc_state->dpll_hw_state.dpll;
> + crtc_state->pixel_multiplier =
> + ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
> + >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
> +
> + ilk_pch_clock_get(crtc_state);
> +}
> +
> static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> enum transcoder cpu_transcoder)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
> index e0ff331c0bc6..6e834fbebd64 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
> @@ -14,6 +14,7 @@ struct intel_crtc_state;
> void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
> void ilk_pch_enable(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> +void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
>
> void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
> void lpt_pch_enable(struct intel_atomic_state *state,
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 6/9] drm/i915: Move iCLKIP readout to the pch code
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (4 preceding siblings ...)
2021-10-15 7:16 ` [Intel-gfx] [PATCH 5/9] drm/i915: Extract ilk_pch_get_config() Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-18 0:43 ` David Airlie
2021-10-15 7:16 ` [Intel-gfx] [PATCH 7/9] drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable() Ville Syrjala
` (10 subsequent siblings)
16 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the lpt_get_iclkip() call from hsw_crt_get_config()
since that's where we have the lpt_program_iclkip() call
as well.
Tehcnically this isn't perhaps quite right since iCLKIP
is providing the CRT dotclock. So one can argue all of
it should be directly in intel_crt.c. But since the CRT
port is the only one on the PCH sticking it all into the
PCH code seems OK.
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 4 ----
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 ++
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 03cfae46f92f..fe807c8e793d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -145,8 +145,6 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
static void hsw_crt_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
lpt_pch_get_config(pipe_config);
hsw_ddi_get_config(encoder, pipe_config);
@@ -156,8 +154,6 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_NVSYNC);
pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
-
- pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
}
/* Note: The caller is required to filter out dpms modes not supported by the
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1dcfe31e6c6f..8bbbeec01607 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -321,10 +321,11 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
{
int dotclock;
+ /* CRT dotclock is determined via other means */
if (pipe_config->has_pch_encoder)
- dotclock = intel_dotclock_calculate(pipe_config->port_clock,
- &pipe_config->fdi_m_n);
- else if (intel_crtc_has_dp_encoder(pipe_config))
+ return;
+
+ if (intel_crtc_has_dp_encoder(pipe_config))
dotclock = intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->dp_m_n);
else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index f3edabdd0a4c..07ec43f8a7fa 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -451,4 +451,6 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
FDI_DP_PORT_WIDTH_SHIFT) + 1;
ilk_get_fdi_m_n_config(crtc, crtc_state);
+
+ crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
}
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 6/9] drm/i915: Move iCLKIP readout to the pch code
2021-10-15 7:16 ` [Intel-gfx] [PATCH 6/9] drm/i915: Move iCLKIP readout to the pch code Ville Syrjala
@ 2021-10-18 0:43 ` David Airlie
0 siblings, 0 replies; 39+ messages in thread
From: David Airlie @ 2021-10-18 0:43 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:17 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the lpt_get_iclkip() call from hsw_crt_get_config()
> since that's where we have the lpt_program_iclkip() call
> as well.
>
> Tehcnically this isn't perhaps quite right since iCLKIP
> is providing the CRT dotclock. So one can argue all of
> it should be directly in intel_crt.c. But since the CRT
> port is the only one on the PCH sticking it all into the
> PCH code seems OK.
Looks good,
Reviewed-by: Dave Airlie <airlied@redhat.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 7/9] drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (5 preceding siblings ...)
2021-10-15 7:16 ` [Intel-gfx] [PATCH 6/9] drm/i915: Move iCLKIP readout to the pch code Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-18 0:43 ` David Airlie
2021-10-15 7:16 ` [Intel-gfx] [PATCH 8/9] drm/i915: Move intel_ddi_fdi_post_disable() to fdi code Ville Syrjala
` (9 subsequent siblings)
16 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Hoover the remaining open coded PCH modeset sequence bits
out from ilk_crtc_disable(). Somewhat annoyingly the
enable vs. disable is a bit asymmetric so we need two
functions for the disable case.
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 27 ++------------
.../gpu/drm/i915/display/intel_pch_display.c | 37 ++++++++++++++++++-
.../gpu/drm/i915/display/intel_pch_display.h | 5 ++-
3 files changed, 43 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e8f15fb3ed07..76203ce9c980 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2289,33 +2289,12 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
ilk_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ilk_fdi_disable(crtc);
+ ilk_pch_disable(state, crtc);
intel_encoders_post_disable(state, crtc);
- if (old_crtc_state->has_pch_encoder) {
- ilk_disable_pch_transcoder(crtc);
-
- if (HAS_PCH_CPT(dev_priv)) {
- i915_reg_t reg;
- u32 temp;
-
- /* disable TRANS_DP_CTL */
- reg = TRANS_DP_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~(TRANS_DP_OUTPUT_ENABLE |
- TRANS_DP_PORT_SEL_MASK);
- temp |= TRANS_DP_PORT_SEL_NONE;
- intel_de_write(dev_priv, reg, temp);
-
- /* disable DPLL_SEL */
- temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
- temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
- intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
- }
-
- ilk_fdi_pll_disable(crtc);
- }
+ if (old_crtc_state->has_pch_encoder)
+ ilk_pch_post_disable(state, crtc);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 07ec43f8a7fa..f40bdb387a68 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -179,7 +179,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
pipe_name(pipe));
}
-void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
+static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -299,6 +299,41 @@ void ilk_pch_enable(struct intel_atomic_state *state,
ilk_enable_pch_transcoder(crtc_state);
}
+void ilk_pch_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ ilk_fdi_disable(crtc);
+}
+
+void ilk_pch_post_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ ilk_disable_pch_transcoder(crtc);
+
+ if (HAS_PCH_CPT(dev_priv)) {
+ i915_reg_t reg;
+ u32 temp;
+
+ /* disable TRANS_DP_CTL */
+ reg = TRANS_DP_CTL(pipe);
+ temp = intel_de_read(dev_priv, reg);
+ temp &= ~(TRANS_DP_OUTPUT_ENABLE |
+ TRANS_DP_PORT_SEL_MASK);
+ temp |= TRANS_DP_PORT_SEL_NONE;
+ intel_de_write(dev_priv, reg, temp);
+
+ /* disable DPLL_SEL */
+ temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+ temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
+ intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+ }
+
+ ilk_fdi_pll_disable(crtc);
+}
+
static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 6e834fbebd64..a983f4d5a3b6 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -11,9 +11,12 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
-void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
void ilk_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+void ilk_pch_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void ilk_pch_post_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 7/9] drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()
2021-10-15 7:16 ` [Intel-gfx] [PATCH 7/9] drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable() Ville Syrjala
@ 2021-10-18 0:43 ` David Airlie
0 siblings, 0 replies; 39+ messages in thread
From: David Airlie @ 2021-10-18 0:43 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:17 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Hoover the remaining open coded PCH modeset sequence bits
> out from ilk_crtc_disable(). Somewhat annoyingly the
> enable vs. disable is a bit asymmetric so we need two
> functions for the disable case.
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 8/9] drm/i915: Move intel_ddi_fdi_post_disable() to fdi code
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (6 preceding siblings ...)
2021-10-15 7:16 ` [Intel-gfx] [PATCH 7/9] drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable() Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-18 0:43 ` David Airlie
2021-10-15 7:16 ` [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable() Ville Syrjala
` (8 subsequent siblings)
16 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reanme intel_ddi_fdi_post_disable() to hsw_fdi_disable() and
relocate it next to all the other code dealing with FDI_RX.
intel_ddi.c has now been cleansed of FDI_RX.
In order to avoid exposing intel_disable_ddi_buf() outside
intel_ddi.c we can just open code the DDI_BUF_CTL write. The
enable side already has all that stuff open coded so
this actually is more symmetric. But we do need to remeber
to bring the intel_wait_ddi_buf_idle() call over from
inside intel_disable_ddi_buf().
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 37 +-----------------------
drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
drivers/gpu/drm/i915/display/intel_fdi.c | 37 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fdi.h | 1 +
5 files changed, 41 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index fe807c8e793d..db27ae2a8406 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -264,7 +264,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
lpt_disable_pch_transcoder(dev_priv);
lpt_disable_iclkip(dev_priv);
- intel_ddi_fdi_post_disable(state, encoder, old_crtc_state, old_conn_state);
+ hsw_fdi_disable(encoder);
drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8bbbeec01607..ab52eab346fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1939,7 +1939,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder,
encoder->enable_clock(encoder, crtc_state);
}
-static void intel_ddi_disable_clock(struct intel_encoder *encoder)
+void intel_ddi_disable_clock(struct intel_encoder *encoder)
{
if (encoder->disable_clock)
encoder->disable_clock(encoder);
@@ -2867,41 +2867,6 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
intel_tc_port_put_link(dig_port);
}
-void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
- struct intel_encoder *encoder,
- const struct intel_crtc_state *old_crtc_state,
- const struct drm_connector_state *old_conn_state)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 val;
-
- /*
- * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
- * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
- * step 13 is the correct place for it. Step 18 is where it was
- * originally before the BUN.
- */
- val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- val &= ~FDI_RX_ENABLE;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
-
- intel_disable_ddi_buf(encoder, old_crtc_state);
- intel_ddi_disable_clock(encoder);
-
- val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
- val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
- val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
- intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
-
- val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- val &= ~FDI_PCDCLK;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
-
- val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- val &= ~FDI_RX_PLL_ENABLE;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
-}
-
static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index d6971717ef9c..6f4551c9d5b7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -30,6 +30,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
const struct drm_connector_state *old_conn_state);
void intel_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_ddi_disable_clock(struct intel_encoder *encoder);
void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index d1c1600c66cb..2b5f80f3b4e0 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -886,6 +886,43 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
DP_TP_CTL_ENABLE);
}
+void hsw_fdi_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 val;
+
+ /*
+ * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
+ * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
+ * step 13 is the correct place for it. Step 18 is where it was
+ * originally before the BUN.
+ */
+ val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
+ val &= ~FDI_RX_ENABLE;
+ intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
+
+ val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
+ val &= ~DDI_BUF_CTL_ENABLE;
+ intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
+
+ intel_wait_ddi_buf_idle(dev_priv, PORT_E);
+
+ intel_ddi_disable_clock(encoder);
+
+ val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
+ val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+ val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
+ intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
+
+ val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
+ val &= ~FDI_PCDCLK;
+ intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
+
+ val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
+ val &= ~FDI_RX_PLL_ENABLE;
+ intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
+}
+
void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
index 5a361730f80a..1cdb86172702 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -23,6 +23,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state);
void intel_fdi_init_hook(struct drm_i915_private *dev_priv);
void hsw_fdi_link_train(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void hsw_fdi_disable(struct intel_encoder *encoder);
void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
void intel_fdi_link_train(struct intel_crtc *crtc,
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 8/9] drm/i915: Move intel_ddi_fdi_post_disable() to fdi code
2021-10-15 7:16 ` [Intel-gfx] [PATCH 8/9] drm/i915: Move intel_ddi_fdi_post_disable() to fdi code Ville Syrjala
@ 2021-10-18 0:43 ` David Airlie
0 siblings, 0 replies; 39+ messages in thread
From: David Airlie @ 2021-10-18 0:43 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:17 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reanme intel_ddi_fdi_post_disable() to hsw_fdi_disable() and
> relocate it next to all the other code dealing with FDI_RX.
> intel_ddi.c has now been cleansed of FDI_RX.
>
> In order to avoid exposing intel_disable_ddi_buf() outside
> intel_ddi.c we can just open code the DDI_BUF_CTL write. The
> enable side already has all that stuff open coded so
> this actually is more symmetric. But we do need to remeber
> to bring the intel_wait_ddi_buf_idle() call over from
> inside intel_disable_ddi_buf().
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (7 preceding siblings ...)
2021-10-15 7:16 ` [Intel-gfx] [PATCH 8/9] drm/i915: Move intel_ddi_fdi_post_disable() to fdi code Ville Syrjala
@ 2021-10-15 7:16 ` Ville Syrjala
2021-10-15 12:11 ` kernel test robot
` (3 more replies)
2021-10-15 7:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move PCH modeset code into its own file Patchwork
` (7 subsequent siblings)
16 siblings, 4 replies; 39+ messages in thread
From: Ville Syrjala @ 2021-10-15 7:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's add lpt_pch_disable() as the counterpart to
lpt_pch_enable().
Note that unlike the ilk+ code the fdi_link_train()
and fdi_disable() calls are still left directly in
intel_crt.c. If we wanted to move those we'd need to
add lpt_pch_pre_enable(). But the two fdi direct fdi
calls are pretry symmetric so it doesn't seem too bad
to just keep them as is.
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 5 ++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_pch_display.h | 4 ++--
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index db27ae2a8406..f0f28572dfdc 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -46,7 +46,6 @@
#include "intel_gmbus.h"
#include "intel_hotplug.h"
#include "intel_pch_display.h"
-#include "intel_pch_refclk.h"
/* Here's the desired hotplug mode */
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
@@ -247,6 +246,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
intel_crtc_vblank_off(old_crtc_state);
@@ -261,8 +261,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
- lpt_disable_pch_transcoder(dev_priv);
- lpt_disable_iclkip(dev_priv);
+ lpt_pch_disable(state, crtc);
hsw_fdi_disable(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index f40bdb387a68..32f2319021f3 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -470,6 +470,16 @@ void lpt_pch_enable(struct intel_atomic_state *state,
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
+void lpt_pch_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ lpt_disable_pch_transcoder(dev_priv);
+
+ lpt_disable_iclkip(dev_priv);
+}
+
void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index a983f4d5a3b6..2c387fe3a467 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -6,7 +6,6 @@
#ifndef _INTEL_PCH_DISPLAY_H_
#define _INTEL_PCH_DISPLAY_H_
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
@@ -19,9 +18,10 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
-void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
void lpt_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+void lpt_pch_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
2021-10-15 7:16 ` [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable() Ville Syrjala
@ 2021-10-15 12:11 ` kernel test robot
2021-10-15 12:56 ` kernel test robot
` (2 subsequent siblings)
3 siblings, 0 replies; 39+ messages in thread
From: kernel test robot @ 2021-10-15 12:11 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: llvm, kbuild-all, Dave Airlie, Jani Nikula
[-- Attachment #1: Type: text/plain, Size: 3770 bytes --]
Hi Ville,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to airlied/drm-next v5.15-rc5 next-20211013]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a014-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff112804e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: no previous prototype for function 'lpt_disable_pch_transcoder' [-Wmissing-prototypes]
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
drivers/gpu/drm/i915/display/intel_pch_display.c:437:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
static
1 warning generated.
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea9023 Ville Syrjälä 2021-10-15 436
da423910ea9023 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea9023 Ville Syrjälä 2021-10-15 438 {
da423910ea9023 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea9023 Ville Syrjälä 2021-10-15 440
da423910ea9023 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea9023 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea9023 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea9023 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea9023 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea9023 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea9023 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea9023 Ville Syrjälä 2021-10-15 448
da423910ea9023 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea9023 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea9023 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea9023 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea9023 Ville Syrjälä 2021-10-15 453 }
da423910ea9023 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41304 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
@ 2021-10-15 12:11 ` kernel test robot
0 siblings, 0 replies; 39+ messages in thread
From: kernel test robot @ 2021-10-15 12:11 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3875 bytes --]
Hi Ville,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to airlied/drm-next v5.15-rc5 next-20211013]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a014-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff112804e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: no previous prototype for function 'lpt_disable_pch_transcoder' [-Wmissing-prototypes]
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
drivers/gpu/drm/i915/display/intel_pch_display.c:437:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
static
1 warning generated.
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea9023 Ville Syrjälä 2021-10-15 436
da423910ea9023 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea9023 Ville Syrjälä 2021-10-15 438 {
da423910ea9023 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea9023 Ville Syrjälä 2021-10-15 440
da423910ea9023 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea9023 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea9023 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea9023 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea9023 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea9023 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea9023 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea9023 Ville Syrjälä 2021-10-15 448
da423910ea9023 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea9023 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea9023 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea9023 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea9023 Ville Syrjälä 2021-10-15 453 }
da423910ea9023 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 41304 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
2021-10-15 7:16 ` [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable() Ville Syrjala
@ 2021-10-15 12:56 ` kernel test robot
2021-10-15 12:56 ` kernel test robot
` (2 subsequent siblings)
3 siblings, 0 replies; 39+ messages in thread
From: kernel test robot @ 2021-10-15 12:56 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: kbuild-all, Dave Airlie, Jani Nikula
[-- Attachment #1: Type: text/plain, Size: 3269 bytes --]
Hi Ville,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20211015]
[cannot apply to airlied/drm-next v5.15-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a005-20211014 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff112804e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: no previous prototype for 'lpt_disable_pch_transcoder' [-Wmissing-prototypes]
437 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea9023 Ville Syrjälä 2021-10-15 436
da423910ea9023 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea9023 Ville Syrjälä 2021-10-15 438 {
da423910ea9023 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea9023 Ville Syrjälä 2021-10-15 440
da423910ea9023 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea9023 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea9023 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea9023 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea9023 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea9023 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea9023 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea9023 Ville Syrjälä 2021-10-15 448
da423910ea9023 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea9023 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea9023 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea9023 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea9023 Ville Syrjälä 2021-10-15 453 }
da423910ea9023 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 35248 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
@ 2021-10-15 12:56 ` kernel test robot
0 siblings, 0 replies; 39+ messages in thread
From: kernel test robot @ 2021-10-15 12:56 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3367 bytes --]
Hi Ville,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20211015]
[cannot apply to airlied/drm-next v5.15-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a005-20211014 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff112804e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: no previous prototype for 'lpt_disable_pch_transcoder' [-Wmissing-prototypes]
437 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea9023 Ville Syrjälä 2021-10-15 436
da423910ea9023 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea9023 Ville Syrjälä 2021-10-15 438 {
da423910ea9023 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea9023 Ville Syrjälä 2021-10-15 440
da423910ea9023 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea9023 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea9023 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea9023 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea9023 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea9023 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea9023 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea9023 Ville Syrjälä 2021-10-15 448
da423910ea9023 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea9023 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea9023 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea9023 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea9023 Ville Syrjälä 2021-10-15 453 }
da423910ea9023 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 35248 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
2021-10-15 7:16 ` [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable() Ville Syrjala
@ 2021-10-15 14:38 ` kernel test robot
2021-10-15 12:56 ` kernel test robot
` (2 subsequent siblings)
3 siblings, 0 replies; 39+ messages in thread
From: kernel test robot @ 2021-10-15 14:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: llvm, kbuild-all, Dave Airlie, Jani Nikula
[-- Attachment #1: Type: text/plain, Size: 3802 bytes --]
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20211015]
[cannot apply to airlied/drm-next v5.15-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a011-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff112804e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: error: no previous prototype for function 'lpt_disable_pch_transcoder' [-Werror,-Wmissing-prototypes]
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
drivers/gpu/drm/i915/display/intel_pch_display.c:437:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
static
1 error generated.
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea902380 Ville Syrjälä 2021-10-15 436
da423910ea902380 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea902380 Ville Syrjälä 2021-10-15 438 {
da423910ea902380 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea902380 Ville Syrjälä 2021-10-15 440
da423910ea902380 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea902380 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea902380 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea902380 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea902380 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea902380 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea902380 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea902380 Ville Syrjälä 2021-10-15 448
da423910ea902380 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea902380 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea902380 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea902380 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea902380 Ville Syrjälä 2021-10-15 453 }
da423910ea902380 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 39904 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
@ 2021-10-15 14:38 ` kernel test robot
0 siblings, 0 replies; 39+ messages in thread
From: kernel test robot @ 2021-10-15 14:38 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3907 bytes --]
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20211015]
[cannot apply to airlied/drm-next v5.15-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a011-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff112804e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: error: no previous prototype for function 'lpt_disable_pch_transcoder' [-Werror,-Wmissing-prototypes]
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
drivers/gpu/drm/i915/display/intel_pch_display.c:437:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
static
1 error generated.
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea902380 Ville Syrjälä 2021-10-15 436
da423910ea902380 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea902380 Ville Syrjälä 2021-10-15 438 {
da423910ea902380 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea902380 Ville Syrjälä 2021-10-15 440
da423910ea902380 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea902380 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea902380 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea902380 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea902380 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea902380 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea902380 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea902380 Ville Syrjälä 2021-10-15 448
da423910ea902380 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea902380 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea902380 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea902380 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea902380 Ville Syrjälä 2021-10-15 453 }
da423910ea902380 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 39904 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
2021-10-15 7:16 ` [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable() Ville Syrjala
` (2 preceding siblings ...)
2021-10-15 14:38 ` kernel test robot
@ 2021-10-18 0:44 ` David Airlie
3 siblings, 0 replies; 39+ messages in thread
From: David Airlie @ 2021-10-18 0:44 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Development, Intel, Jani Nikula
On Fri, Oct 15, 2021 at 5:17 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's add lpt_pch_disable() as the counterpart to
> lpt_pch_enable().
>
> Note that unlike the ilk+ code the fdi_link_train()
> and fdi_disable() calls are still left directly in
> intel_crt.c. If we wanted to move those we'd need to
> add lpt_pch_pre_enable(). But the two fdi direct fdi
> calls are pretry symmetric so it doesn't seem too bad
> to just keep them as is.
>
> Cc: Dave Airlie <airlied@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
apart from krobot suggestions.
Reviewed-by: Dave Airlie <airlied@redhat.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move PCH modeset code into its own file
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (8 preceding siblings ...)
2021-10-15 7:16 ` [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable() Ville Syrjala
@ 2021-10-15 7:31 ` Patchwork
2021-10-15 7:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-15 7:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file
URL : https://patchwork.freedesktop.org/series/95863/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ae28f635f0fc drm/i915: Move PCH refclok stuff into its own file
-:802: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#802:
new file mode 100644
-:1002: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1002: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:196:
+ udelay(24);
-:1069: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1069: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:263:
+ udelay(24);
-:1105: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1105: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:299:
+ udelay(32);
-:1117: ERROR:SPACING: space prohibited after that open parenthesis '('
#1117: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:311:
+ [BEND_IDX( 50)] = 0x3B23,
-:1118: ERROR:SPACING: space prohibited after that open parenthesis '('
#1118: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:312:
+ [BEND_IDX( 45)] = 0x3B23,
-:1119: ERROR:SPACING: space prohibited after that open parenthesis '('
#1119: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:313:
+ [BEND_IDX( 40)] = 0x3C23,
-:1120: ERROR:SPACING: space prohibited after that open parenthesis '('
#1120: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:314:
+ [BEND_IDX( 35)] = 0x3C23,
-:1121: ERROR:SPACING: space prohibited after that open parenthesis '('
#1121: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:315:
+ [BEND_IDX( 30)] = 0x3D23,
-:1122: ERROR:SPACING: space prohibited after that open parenthesis '('
#1122: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:316:
+ [BEND_IDX( 25)] = 0x3D23,
-:1123: ERROR:SPACING: space prohibited after that open parenthesis '('
#1123: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:317:
+ [BEND_IDX( 20)] = 0x3E23,
-:1124: ERROR:SPACING: space prohibited after that open parenthesis '('
#1124: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:318:
+ [BEND_IDX( 15)] = 0x3E23,
-:1125: ERROR:SPACING: space prohibited after that open parenthesis '('
#1125: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:319:
+ [BEND_IDX( 10)] = 0x3F23,
-:1126: ERROR:SPACING: space prohibited after that open parenthesis '('
#1126: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:320:
+ [BEND_IDX( 5)] = 0x3F23,
-:1127: ERROR:SPACING: space prohibited after that open parenthesis '('
#1127: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:321:
+ [BEND_IDX( 0)] = 0x0025,
-:1128: ERROR:SPACING: space prohibited after that open parenthesis '('
#1128: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:322:
+ [BEND_IDX( -5)] = 0x0025,
-:1394: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1394: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:588:
+ udelay(200);
-:1413: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1413: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:607:
+ udelay(200);
-:1424: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1424: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:618:
+ udelay(200);
-:1438: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1438: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:632:
+ udelay(200);
-:1442: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#1442: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:636:
+ BUG_ON(val != final);
total: 12 errors, 2 warnings, 7 checks, 1411 lines checked
0a9f7351d945 drm/i915: Move PCH modeset code to its own file
-:453: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#453:
new file mode 100644
-:764: CHECK:SPACING: No space is necessary after a cast
#764: FILE: drivers/gpu/drm/i915/display/intel_pch_display.c:307:
+ assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
total: 0 errors, 1 warnings, 1 checks, 796 lines checked
03d86e18ea3e drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention
32638e909748 drm/i915: Move LPT PCH readout code
a92a0a2e979c drm/i915: Extract ilk_pch_get_config()
-:192: CHECK:SPACING: No space is necessary after a cast
#192: FILE: drivers/gpu/drm/i915/display/intel_pch_display.c:346:
+ pll_id = (enum intel_dpll_id) pipe;
total: 0 errors, 0 warnings, 1 checks, 188 lines checked
03365a324a75 drm/i915: Move iCLKIP readout to the pch code
b9dd6f1b71d4 drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()
bc37d7855c26 drm/i915: Move intel_ddi_fdi_post_disable() to fdi code
4d8f6f29f43b drm/i915: Introduce lpt_pch_disable()
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move PCH modeset code into its own file
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (9 preceding siblings ...)
2021-10-15 7:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move PCH modeset code into its own file Patchwork
@ 2021-10-15 7:32 ` Patchwork
2021-10-15 8:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-15 7:32 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file
URL : https://patchwork.freedesktop.org/series/95863/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: symbol 'lpt_disable_pch_transcoder' was not declared. Should it be static?
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move PCH modeset code into its own file
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (10 preceding siblings ...)
2021-10-15 7:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-10-15 8:02 ` Patchwork
2021-10-15 14:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-15 8:02 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6814 bytes --]
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file
URL : https://patchwork.freedesktop.org/series/95863/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10742 -> Patchwork_21346
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/index.html
Known issues
------------
Here are the changes found in Patchwork_21346 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([fdo#109315])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([fdo#109285])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#4269])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#1072]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#3301])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][13] ([i915#2940]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@kms_flip@basic-plain-flip@c-dp1:
- fi-cfl-8109u: [FAIL][15] ([i915#4165]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][17] ([i915#295]) -> [PASS][18] +14 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
Participating hosts (39 -> 37)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (3): fi-bsw-cyan bat-dg1-6 fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10742 -> Patchwork_21346
CI-20190529: 20190529
CI_DRM_10742: 22f87ae60973876dff6d4264404251fb5b93f697 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6250: 3c2ac88757f0d0ac9450487d314fcaceebc8bc26 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21346: 4d8f6f29f43b443d5102e43ee44285ad13c1ade3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4d8f6f29f43b drm/i915: Introduce lpt_pch_disable()
bc37d7855c26 drm/i915: Move intel_ddi_fdi_post_disable() to fdi code
b9dd6f1b71d4 drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()
03365a324a75 drm/i915: Move iCLKIP readout to the pch code
a92a0a2e979c drm/i915: Extract ilk_pch_get_config()
32638e909748 drm/i915: Move LPT PCH readout code
03d86e18ea3e drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention
0a9f7351d945 drm/i915: Move PCH modeset code to its own file
ae28f635f0fc drm/i915: Move PCH refclok stuff into its own file
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/index.html
[-- Attachment #2: Type: text/html, Size: 7827 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move PCH modeset code into its own file
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (11 preceding siblings ...)
2021-10-15 8:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-15 14:45 ` Patchwork
2021-10-18 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move PCH modeset code into its own file (rev2) Patchwork
` (3 subsequent siblings)
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-15 14:45 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30272 bytes --]
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file
URL : https://patchwork.freedesktop.org/series/95863/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10742_full -> Patchwork_21346_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21346_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_bw@linear-tiling-4-displays-1920x1080p}:
- shard-apl: NOTRUN -> [DMESG-FAIL][1] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl8/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html
* {igt@kms_bw@linear-tiling-4-displays-3840x2160p}:
- shard-skl: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
Known issues
------------
Here are the changes found in Patchwork_21346_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#456])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-snb2/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#280])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb8/igt@gem_eio@in-flight-contexts-1us.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb3/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#3063] / [i915#3648])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb8/igt@gem_eio@unwedge-stress.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2846])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb5/igt@gem_exec_fair@basic-deadline.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][13] -> [SKIP][14] ([i915#2848])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: NOTRUN -> [FAIL][17] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb1/igt@gem_exec_fair@basic-pace@vcs1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_nop@basic-parallel:
- shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#118]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-glk1/igt@gem_exec_nop@basic-parallel.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-glk5/igt@gem_exec_nop@basic-parallel.html
* igt@gem_exec_schedule@semaphore-codependency:
- shard-snb: NOTRUN -> [SKIP][27] ([fdo#109271]) +267 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-snb5/igt@gem_exec_schedule@semaphore-codependency.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-snb: [PASS][28] -> [INCOMPLETE][29] ([i915#2055])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-snb2/igt@gem_fenced_exec_thrash@too-many-fences.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-snb5/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#4270])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#3297])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3323])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl8/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][33] -> [DMESG-WARN][34] ([i915#1436] / [i915#716])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl9/igt@gen9_exec_parse@allowed-single.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl9/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#2856]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#1937])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: [PASS][37] -> [WARN][38] ([i915#2681])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb8/igt@i915_pm_rc6_residency@rc6-fence.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb3/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][39] ([i915#1886] / [i915#2291])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: NOTRUN -> [INCOMPLETE][40] ([i915#3921])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: [PASS][41] -> [DMESG-WARN][42] ([i915#180]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-apl2/igt@i915_suspend@fence-restore-untiled.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl2/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111614]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3777]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3777]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#111615]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][47] ([i915#3722]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#3689]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +6 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3689] / [i915#3886])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-fast:
- shard-snb: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +11 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-snb5/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +10 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +13 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109284] / [fdo#111827]) +5 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> [TIMEOUT][56] ([i915#1319])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl1/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#3319])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen:
- shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109279] / [i915#3359]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen:
- shard-tglb: NOTRUN -> [SKIP][59] ([i915#3359]) +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][62] -> [FAIL][63] ([i915#2346])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-tglb: [PASS][64] -> [FAIL][65] ([i915#2346] / [i915#533])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
- shard-tglb: NOTRUN -> [SKIP][66] ([i915#3788])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#111825]) +12 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][68] -> [FAIL][69] ([i915#79])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: NOTRUN -> [FAIL][70] ([i915#2122])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2672]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-iclb: [PASS][72] -> [SKIP][73] ([i915#3701])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-tglb: [PASS][74] -> [INCOMPLETE][75] ([i915#2411] / [i915#456]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
- shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271]) +136 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#1187])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#109289])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#533]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl3/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-snb: [PASS][80] -> [SKIP][81] ([fdo#109271])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-snb5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-snb6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][82] ([fdo#108145] / [i915#265]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-d-tiling-y:
- shard-tglb: NOTRUN -> [SKIP][84] ([i915#3536])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb6/igt@kms_plane_lowres@pipe-d-tiling-y.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#658]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#2920])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_su@frontbuffer:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl7/igt@kms_psr2_su@frontbuffer.html
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> [FAIL][88] ([i915#31])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-snb7/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271]) +184 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl3/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2437])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@kms_writeback@writeback-check-output.html
* igt@prime_nv_pcopy@test3_1:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109291]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@prime_nv_pcopy@test3_1.html
* igt@sysfs_clients@busy:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2994])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl3/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-3:
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#2994])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@split-50:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2994])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl2/igt@sysfs_clients@split-50.html
* igt@sysfs_timeslice_duration@timeout@rcs0:
- shard-skl: [PASS][95] -> [FAIL][96] ([i915#3259])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl9/igt@sysfs_timeslice_duration@timeout@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl9/igt@sysfs_timeslice_duration@timeout@rcs0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@engines-hostile@vcs0:
- shard-apl: [FAIL][97] ([i915#2410]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-apl8/igt@gem_ctx_persistence@engines-hostile@vcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl7/igt@gem_ctx_persistence@engines-hostile@vcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [FAIL][99] ([i915#2842]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][101] ([i915#2842]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_mmap_offset@clear:
- shard-tglb: [TIMEOUT][103] ([i915#2502]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb8/igt@gem_mmap_offset@clear.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb3/igt@gem_mmap_offset@clear.html
* igt@gem_softpin@allocator-fork:
- shard-glk: [DMESG-WARN][105] ([i915#118]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-glk9/igt@gem_softpin@allocator-fork.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-glk9/igt@gem_softpin@allocator-fork.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [INCOMPLETE][107] ([i915#456]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb5/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [INCOMPLETE][109] ([i915#198]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl8/igt@i915_suspend@sysfs-reader.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl7/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-tglb: [FAIL][111] ([i915#3722]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][113] ([i915#180]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][115] ([i915#72]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_dp_aux_dev:
- shard-iclb: [DMESG-WARN][117] ([i915#262]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb7/igt@kms_dp_aux_dev.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb2/igt@kms_dp_aux_dev.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk: [FAIL][119] ([i915#79]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible@a-edp1:
- shard-skl: [DMESG-WARN][121] ([i915#1982]) -> [PASS][122] +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl10/igt@kms_flip@modeset-vs-vblank-race-interruptible@a-edp1.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl8/igt@kms_flip@modeset-vs-vblank-race-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-iclb: [SKIP][123] ([i915#3701]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][125] ([i915#1188]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][127] ([fdo#109441]) -> [PASS][128] +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@perf@blocking:
- shard-tglb: [FAIL][129] ([i915#1542]) -> [PASS][130] +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-tglb8/igt@perf@blocking.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-tglb3/igt@perf@blocking.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [FAIL][131] ([i915#1731]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl3/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-skl4/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][133] ([i915#2851]) -> [FAIL][134] ([i915#2842])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-glk6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][135] ([i915#2842]) -> [FAIL][136] ([i915#2849])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [FAIL][137] ([i915#4275]) -> [SKIP][138] ([i915#4281])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][139] ([i915#1804] / [i915#2684]) -> [WARN][140] ([i915#2684]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: [FAIL][141] ([i915#3743]) -> [FAIL][142] ([i915#3722])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10742/shard-skl4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-ro
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21346/index.html
[-- Attachment #2: Type: text/html, Size: 33515 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move PCH modeset code into its own file (rev2)
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (12 preceding siblings ...)
2021-10-15 14:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-10-18 18:37 ` Patchwork
2021-10-18 18:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-18 18:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file (rev2)
URL : https://patchwork.freedesktop.org/series/95863/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fe78f7aa4624 drm/i915: Move PCH refclok stuff into its own file
-:803: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#803:
new file mode 100644
-:1003: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1003: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:196:
+ udelay(24);
-:1070: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1070: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:263:
+ udelay(24);
-:1106: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1106: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:299:
+ udelay(32);
-:1118: ERROR:SPACING: space prohibited after that open parenthesis '('
#1118: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:311:
+ [BEND_IDX( 50)] = 0x3B23,
-:1119: ERROR:SPACING: space prohibited after that open parenthesis '('
#1119: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:312:
+ [BEND_IDX( 45)] = 0x3B23,
-:1120: ERROR:SPACING: space prohibited after that open parenthesis '('
#1120: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:313:
+ [BEND_IDX( 40)] = 0x3C23,
-:1121: ERROR:SPACING: space prohibited after that open parenthesis '('
#1121: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:314:
+ [BEND_IDX( 35)] = 0x3C23,
-:1122: ERROR:SPACING: space prohibited after that open parenthesis '('
#1122: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:315:
+ [BEND_IDX( 30)] = 0x3D23,
-:1123: ERROR:SPACING: space prohibited after that open parenthesis '('
#1123: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:316:
+ [BEND_IDX( 25)] = 0x3D23,
-:1124: ERROR:SPACING: space prohibited after that open parenthesis '('
#1124: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:317:
+ [BEND_IDX( 20)] = 0x3E23,
-:1125: ERROR:SPACING: space prohibited after that open parenthesis '('
#1125: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:318:
+ [BEND_IDX( 15)] = 0x3E23,
-:1126: ERROR:SPACING: space prohibited after that open parenthesis '('
#1126: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:319:
+ [BEND_IDX( 10)] = 0x3F23,
-:1127: ERROR:SPACING: space prohibited after that open parenthesis '('
#1127: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:320:
+ [BEND_IDX( 5)] = 0x3F23,
-:1128: ERROR:SPACING: space prohibited after that open parenthesis '('
#1128: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:321:
+ [BEND_IDX( 0)] = 0x0025,
-:1129: ERROR:SPACING: space prohibited after that open parenthesis '('
#1129: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:322:
+ [BEND_IDX( -5)] = 0x0025,
-:1395: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1395: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:588:
+ udelay(200);
-:1414: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1414: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:607:
+ udelay(200);
-:1425: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1425: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:618:
+ udelay(200);
-:1439: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#1439: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:632:
+ udelay(200);
-:1443: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#1443: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.c:636:
+ BUG_ON(val != final);
total: 12 errors, 2 warnings, 7 checks, 1411 lines checked
9346281c5925 drm/i915: Move PCH modeset code to its own file
-:454: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#454:
new file mode 100644
-:765: CHECK:SPACING: No space is necessary after a cast
#765: FILE: drivers/gpu/drm/i915/display/intel_pch_display.c:307:
+ assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
total: 0 errors, 1 warnings, 1 checks, 796 lines checked
3f2c8e4d7c8e drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention
25072419a975 drm/i915: Move LPT PCH readout code
4bfd17869e11 drm/i915: Extract ilk_pch_get_config()
-:193: CHECK:SPACING: No space is necessary after a cast
#193: FILE: drivers/gpu/drm/i915/display/intel_pch_display.c:346:
+ pll_id = (enum intel_dpll_id) pipe;
total: 0 errors, 0 warnings, 1 checks, 188 lines checked
43488950420d drm/i915: Move iCLKIP readout to the pch code
4ef845baae54 drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()
39b8f7cf41e2 drm/i915: Move intel_ddi_fdi_post_disable() to fdi code
4f18cafd1f4a drm/i915: Introduce lpt_pch_disable()
-:23: WARNING:BAD_SIGN_OFF: Duplicate signature
#23:
Reported-by: kernel test robot <lkp@intel.com>
-:24: WARNING:BAD_SIGN_OFF: Duplicate signature
#24:
Reported-by: kernel test robot <lkp@intel.com>
total: 0 errors, 2 warnings, 0 checks, 57 lines checked
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move PCH modeset code into its own file (rev2)
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (13 preceding siblings ...)
2021-10-18 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move PCH modeset code into its own file (rev2) Patchwork
@ 2021-10-18 18:38 ` Patchwork
2021-10-18 19:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-19 1:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-18 18:38 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file (rev2)
URL : https://patchwork.freedesktop.org/series/95863/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: symbol 'lpt_disable_pch_transcoder' was not declared. Should it be static?
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move PCH modeset code into its own file (rev2)
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (14 preceding siblings ...)
2021-10-18 18:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-10-18 19:07 ` Patchwork
2021-10-19 1:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-18 19:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3569 bytes --]
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file (rev2)
URL : https://patchwork.freedesktop.org/series/95863/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10753 -> Patchwork_21375
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/index.html
Known issues
------------
Here are the changes found in Patchwork_21375 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/fi-bsw-n3050/igt@amdgpu/amd_cs_nop@sync-gfx0.html
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-samus: [PASS][3] -> [INCOMPLETE][4] ([i915#146])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/fi-bdw-samus/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/fi-bdw-samus/igt@gem_exec_suspend@basic-s3.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][5] ([i915#2940]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][7] ([i915#3921]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
Participating hosts (39 -> 37)
------------------------------
Missing (2): fi-bsw-cyan bat-dg1-6
Build changes
-------------
* Linux: CI_DRM_10753 -> Patchwork_21375
CI-20190529: 20190529
CI_DRM_10753: 57c1bcf63565db8d65783364c632a04a44bbd616 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6254: 51792e987da03ba2a6faf5857c12f1d173c87def @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21375: 4f18cafd1f4a074b9c608ef3bb25077ef2f88bc5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4f18cafd1f4a drm/i915: Introduce lpt_pch_disable()
39b8f7cf41e2 drm/i915: Move intel_ddi_fdi_post_disable() to fdi code
4ef845baae54 drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()
43488950420d drm/i915: Move iCLKIP readout to the pch code
4bfd17869e11 drm/i915: Extract ilk_pch_get_config()
25072419a975 drm/i915: Move LPT PCH readout code
3f2c8e4d7c8e drm/i915: Clean up the {ilk, lpt}_pch_enable() calling convention
9346281c5925 drm/i915: Move PCH modeset code to its own file
fe78f7aa4624 drm/i915: Move PCH refclok stuff into its own file
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/index.html
[-- Attachment #2: Type: text/html, Size: 4405 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move PCH modeset code into its own file (rev2)
2021-10-15 7:16 [Intel-gfx] [PATCH 0/9] drm/i915: Move PCH modeset code into its own file Ville Syrjala
` (15 preceding siblings ...)
2021-10-18 19:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-19 1:47 ` Patchwork
16 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-10-19 1:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30279 bytes --]
== Series Details ==
Series: drm/i915: Move PCH modeset code into its own file (rev2)
URL : https://patchwork.freedesktop.org/series/95863/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21375_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_21375_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl2/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-hostile:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hostile.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][5] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
- shard-kbl: NOTRUN -> [FAIL][6] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_params@no-blt:
- shard-iclb: NOTRUN -> [SKIP][9] ([fdo#109283])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@gem_exec_params@no-blt.html
* igt@gem_exec_params@secure-non-master:
- shard-iclb: NOTRUN -> [SKIP][10] ([fdo#112283])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@gem_exec_params@secure-non-master.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl4/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][12] ([fdo#111656])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@gem_mmap_gtt@coherency.html
* igt@gem_pread@exhaustion:
- shard-tglb: NOTRUN -> [WARN][13] ([i915#2658])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@gem_pread@exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#4270])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#768])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#3297])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@vma-merge:
- shard-tglb: NOTRUN -> [FAIL][17] ([i915#3318])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109289])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][19] ([i915#2681])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#1769])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111615]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#110723])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_bw@linear-tiling-3-displays-3840x2160p:
- shard-apl: NOTRUN -> [DMESG-FAIL][24] ([i915#4298])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl8/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-4-displays-2560x1440p:
- shard-kbl: NOTRUN -> [FAIL][25] ([i915#4299])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl4/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk3/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +9 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl4/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][28] ([fdo#109278] / [i915#3886]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +6 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl3/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3689]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_ccs:
- shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271]) +41 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk3/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_ccs.html
* igt@kms_chamelium@dp-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +12 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl2/igt@kms_chamelium@dp-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +14 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl3/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109284] / [fdo#111827]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-skl7/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +8 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-snb6/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-ctm-0-75:
- shard-glk: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk3/igt@kms_color_chamelium@pipe-d-ctm-0-75.html
* igt@kms_content_protection@atomic:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#111828])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding:
- shard-iclb: [PASS][40] -> [DMESG-FAIL][41] ([i915#1226])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb5/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][42] ([i915#180])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [fdo#109279])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-random:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_cursor_crc@pipe-d-cursor-64x64-random.html
* igt@kms_cursor_crc@pipe-d-cursor-max-size-offscreen:
- shard-tglb: NOTRUN -> [SKIP][46] ([i915#3359])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-max-size-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271]) +165 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109274] / [fdo#109278])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
- shard-skl: NOTRUN -> [SKIP][49] ([fdo#109271]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-skl9/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][50] -> [FAIL][51] ([i915#2346])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl2/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglb: [PASS][53] -> [INCOMPLETE][54] ([i915#2411] / [i915#456])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb3/igt@kms_fbcon_fbt@psr-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb7/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109274])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#2122]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-iclb: NOTRUN -> [SKIP][58] ([i915#2587])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2672])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2672])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> [SKIP][63] ([fdo#109271]) +198 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-snb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render:
- shard-tglb: NOTRUN -> [SKIP][64] ([fdo#111825]) +10 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109280])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_hdr@static-toggle:
- shard-iclb: NOTRUN -> [SKIP][66] ([i915#1187])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_hdr@static-toggle.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][68] -> [FAIL][69] ([fdo#108145] / [i915#265]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][71] ([i915#265])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#3536])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#2920])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#658]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_su@frontbuffer:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#1911])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][77] -> [SKIP][78] ([fdo#109441]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb2/igt@kms_psr@psr2_suspend.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb8/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][79] -> [DMESG-WARN][80] ([i915#180] / [i915#295])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][81] -> [DMESG-WARN][82] ([i915#180])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-apl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-suspend:
- shard-tglb: [PASS][83] -> [INCOMPLETE][84] ([i915#3896])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb8/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb7/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271]) +193 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl7/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-c-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#2530]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@nouveau_crc@pipe-c-ctx-flip-detection.html
* igt@prime_nv_pcopy@test3_3:
- shard-tglb: NOTRUN -> [SKIP][87] ([fdo#109291])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@prime_nv_pcopy@test3_3.html
* igt@sysfs_clients@fair-0:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2994]) +2 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl7/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@sema-50:
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#2994])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-25:
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#2994])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@sysfs_clients@split-25.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) +3 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl3/igt@sysfs_clients@split-50.html
- shard-glk: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2994])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk3/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl: [DMESG-WARN][93] ([i915#180]) -> [PASS][94] +5 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][95] ([i915#3063]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb8/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][97] ([i915#2842] / [i915#3468]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][99] ([i915#2842]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][101] ([i915#2842]) -> [PASS][102] +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [FAIL][103] ([i915#2842]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs1.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][105] ([i915#2849]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][107] ([i915#3921]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-snb2/igt@i915_selftest@live@hangcheck.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@mock@requests:
- shard-glk: [INCOMPLETE][109] -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-glk1/igt@i915_selftest@mock@requests.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk3/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0:
- shard-kbl: [DMESG-WARN][111] ([i915#62] / [i915#92]) -> [PASS][112] +13 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- shard-glk: [DMESG-WARN][113] ([i915#118]) -> [PASS][114] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-glk2/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk5/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [INCOMPLETE][115] ([i915#2411] / [i915#456]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
- shard-skl: [FAIL][117] ([i915#2122]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-skl9/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-skl5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
- shard-glk: [FAIL][119] ([i915#79]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-iclb: [SKIP][121] ([i915#3701]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][123] ([i915#1188]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][125] ([fdo#109441]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb4/igt@kms_psr@psr2_dpms.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@kms_psr@psr2_dpms.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-kbl: [INCOMPLETE][127] ([i915#3614]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf_pmu@module-unload:
- shard-kbl: [INCOMPLETE][129] ([i915#262]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl7/igt@perf_pmu@module-unload.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-kbl4/igt@perf_pmu@module-unload.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][131] ([i915#658]) -> [SKIP][132] ([i915#588])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb4/igt@i915_pm_dc@dc3co-vpb-simulation.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-iclb: [SKIP][133] ([i915#2920]) -> [SKIP][134] ([i915#658])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][135] ([i915#658]) -> [SKIP][136] ([i915#2920]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/shard
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21375/index.html
[-- Attachment #2: Type: text/html, Size: 33676 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread