From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org> Subject: [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction Date: Fri, 15 Oct 2021 15:45:37 +0800 [thread overview] Message-ID: <20211015074627.3957162-37-frank.chang@sifive.com> (raw) In-Reply-To: <20211015074627.3957162-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 ++++--- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 780cd6d995a..3b6b4788818 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1066,7 +1066,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32) DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 64c2a533b42..f12096d67de 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -669,7 +669,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r -vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm +vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ec205bfd63c..80d23e3f447 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2864,8 +2864,8 @@ GEN_MM_TRANS(vmnor_mm) GEN_MM_TRANS(vmornot_mm) GEN_MM_TRANS(vmxnor_mm) -/* Vector mask population count vmpopc */ -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +/* Vector mask population count vpopc */ +static bool trans_vpopc_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2884,11 +2884,12 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); + gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + return true; } return false; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1ef98de6b63..18c26c45731 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4416,9 +4416,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) -/* Vector mask population count vmpopc */ -target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* Vector mask population count vpopc */ +target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { target_ulong cnt = 0; uint32_t vm = vext_vm(desc); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Richard Henderson <richard.henderson@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com> Subject: [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction Date: Fri, 15 Oct 2021 15:45:37 +0800 [thread overview] Message-ID: <20211015074627.3957162-37-frank.chang@sifive.com> (raw) In-Reply-To: <20211015074627.3957162-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 ++++--- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 780cd6d995a..3b6b4788818 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1066,7 +1066,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32) DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 64c2a533b42..f12096d67de 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -669,7 +669,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r -vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm +vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ec205bfd63c..80d23e3f447 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2864,8 +2864,8 @@ GEN_MM_TRANS(vmnor_mm) GEN_MM_TRANS(vmornot_mm) GEN_MM_TRANS(vmxnor_mm) -/* Vector mask population count vmpopc */ -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +/* Vector mask population count vpopc */ +static bool trans_vpopc_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2884,11 +2884,12 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); + gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + return true; } return false; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1ef98de6b63..18c26c45731 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4416,9 +4416,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) -/* Vector mask population count vmpopc */ -target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* Vector mask population count vpopc */ +target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { target_ulong cnt = 0; uint32_t vm = vext_vm(desc); -- 2.25.1
next prev parent reply other threads:[~2021-10-15 8:17 UTC|newest] Thread overview: 237+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-15 7:45 [PATCH v8 00/78] support vector extension v1.0 frank.chang 2021-10-15 7:45 ` [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-16 3:04 ` Richard Henderson 2021-10-16 3:04 ` Richard Henderson 2021-10-17 22:55 ` Alistair Francis 2021-10-17 22:55 ` Alistair Francis 2021-10-18 5:38 ` Richard Henderson 2021-10-18 5:38 ` Richard Henderson 2021-10-18 6:01 ` Alistair Francis 2021-10-18 6:01 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus " frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH 18/76] target/riscv: rvv-1.0: configure instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-18 5:44 ` Alistair Francis 2021-10-18 5:44 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH 20/76] target/riscv: rvv-1.0: index " frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 20/78] target/riscv: rvv-1.0: stride " frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH 23/76] target/riscv: rvv-1.0: amo operations frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-18 5:46 ` Alistair Francis 2021-10-18 5:46 ` Alistair Francis 2021-10-15 7:45 ` frank.chang [this message] 2021-10-15 7:45 ` [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction frank.chang 2021-10-15 7:45 ` [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-18 5:47 ` Alistair Francis 2021-10-18 5:47 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-18 5:53 ` Alistair Francis 2021-10-18 5:53 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-18 5:49 ` Alistair Francis 2021-10-18 5:49 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-18 5:54 ` Alistair Francis 2021-10-18 5:54 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-21 4:28 ` Alistair Francis 2021-10-21 4:28 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-21 4:24 ` Alistair Francis 2021-10-21 4:24 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-21 4:26 ` Alistair Francis 2021-10-21 4:26 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 39/78] target/riscv: rvv-1.0: whole register " frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-21 4:27 ` Alistair Francis 2021-10-21 4:27 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-25 6:08 ` Alistair Francis 2021-10-25 6:08 ` Alistair Francis 2021-10-15 7:45 ` [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-15 7:45 ` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point " frank.chang 2021-10-15 7:45 ` frank.chang 2021-10-25 6:13 ` Alistair Francis 2021-10-25 6:13 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-25 6:16 ` Alistair Francis 2021-10-25 6:16 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-26 6:29 ` Alistair Francis 2021-10-26 6:29 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-26 6:30 ` Alistair Francis 2021-10-26 6:30 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-26 6:32 ` Alistair Francis 2021-10-26 6:32 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-25 6:43 ` Alistair Francis 2021-10-25 6:43 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-25 6:42 ` Alistair Francis 2021-10-25 6:42 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-26 6:50 ` Alistair Francis 2021-10-26 6:50 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-26 6:52 ` Alistair Francis 2021-10-26 6:52 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-15 7:46 ` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-26 6:55 ` Alistair Francis 2021-10-26 6:55 ` Alistair Francis 2021-10-15 7:46 ` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang 2021-10-15 7:46 ` frank.chang 2021-10-26 6:49 ` Alistair Francis 2021-10-26 6:49 ` Alistair Francis 2021-10-15 9:02 ` [PATCH v8 00/78] support vector extension v1.0 Frank Chang 2021-10-15 9:02 ` Frank Chang 2021-10-18 6:00 ` Alistair Francis 2021-10-18 6:00 ` Alistair Francis 2021-10-18 6:09 ` Frank Chang 2021-10-18 6:09 ` Frank Chang 2021-10-18 6:12 ` Alistair Francis 2021-10-18 6:12 ` Alistair Francis 2021-10-18 6:17 ` Frank Chang 2021-10-18 6:17 ` Frank Chang 2021-10-18 9:01 ` LIU Zhiwei 2021-10-18 9:34 ` LIU Zhiwei 2021-10-20 5:28 ` Alistair Francis 2021-10-20 5:28 ` Alistair Francis
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