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From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Date: Mon, 25 Oct 2021 16:43:22 +1000	[thread overview]
Message-ID: <CAKmqyKOcAFS49vqtuMoAuQi9rpnb+E9kGeLjFF=qirZvyQ7Y3A@mail.gmail.com> (raw)
In-Reply-To: <20211015074627.3957162-73-frank.chang@sifive.com>

On Fri, Oct 15, 2021 at 6:43 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> --
> ---
>  target/riscv/cpu.h                      | 2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
>  target/riscv/vector_helper.c            | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9b2af4e4d0e..49eece111e2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -101,7 +101,7 @@ typedef struct CPURISCVState CPURISCVState;
>  #include "pmp.h"
>  #endif
>
> -#define RV_VLEN_MAX 256
> +#define RV_VLEN_MAX 1024
>
>  FIELD(VTYPE, VLMUL, 0, 3)
>  FIELD(VTYPE, VSEW, 3, 3)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 92a23b52e49..dcb96c954ec 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -567,8 +567,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>      base = get_gpr(s, rs1, EXT_NONE);
>
>      /*
> -     * As simd_desc supports at most 256 bytes, and in this implementation,
> -     * the max vector group length is 2048 bytes. So split it into two parts.
> +     * As simd_desc supports at most 2048 bytes, and in this implementation,
> +     * the max vector group length is 4096 bytes. So split it into two parts.
>       *
>       * The first part is vlen in bytes, encoded in maxsz of simd_desc.
>       * The second part is lmul, encoded in data of simd_desc.
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 37b2451bd05..70ddc55e16b 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -124,7 +124,7 @@ static inline int32_t vext_lmul(uint32_t desc)
>  static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
>  {
>      /*
> -     * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
> +     * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
>       * so vlen in bytes (vlenb) is encoded as maxsz.
>       */
>      uint32_t vlenb = simd_maxsz(desc);
> --
> 2.25.1
>
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 Alistair Francis <alistair.francis@wdc.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	 Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Date: Mon, 25 Oct 2021 16:43:22 +1000	[thread overview]
Message-ID: <CAKmqyKOcAFS49vqtuMoAuQi9rpnb+E9kGeLjFF=qirZvyQ7Y3A@mail.gmail.com> (raw)
In-Reply-To: <20211015074627.3957162-73-frank.chang@sifive.com>

On Fri, Oct 15, 2021 at 6:43 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> --
> ---
>  target/riscv/cpu.h                      | 2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
>  target/riscv/vector_helper.c            | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9b2af4e4d0e..49eece111e2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -101,7 +101,7 @@ typedef struct CPURISCVState CPURISCVState;
>  #include "pmp.h"
>  #endif
>
> -#define RV_VLEN_MAX 256
> +#define RV_VLEN_MAX 1024
>
>  FIELD(VTYPE, VLMUL, 0, 3)
>  FIELD(VTYPE, VSEW, 3, 3)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 92a23b52e49..dcb96c954ec 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -567,8 +567,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>      base = get_gpr(s, rs1, EXT_NONE);
>
>      /*
> -     * As simd_desc supports at most 256 bytes, and in this implementation,
> -     * the max vector group length is 2048 bytes. So split it into two parts.
> +     * As simd_desc supports at most 2048 bytes, and in this implementation,
> +     * the max vector group length is 4096 bytes. So split it into two parts.
>       *
>       * The first part is vlen in bytes, encoded in maxsz of simd_desc.
>       * The second part is lmul, encoded in data of simd_desc.
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 37b2451bd05..70ddc55e16b 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -124,7 +124,7 @@ static inline int32_t vext_lmul(uint32_t desc)
>  static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
>  {
>      /*
> -     * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
> +     * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
>       * so vlen in bytes (vlenb) is encoded as maxsz.
>       */
>      uint32_t vlenb = simd_maxsz(desc);
> --
> 2.25.1
>
>


  reply	other threads:[~2021-10-25  6:46 UTC|newest]

Thread overview: 237+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-15  7:45 [PATCH v8 00/78] support vector extension v1.0 frank.chang
2021-10-15  7:45 ` [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-16  3:04   ` Richard Henderson
2021-10-16  3:04     ` Richard Henderson
2021-10-17 22:55   ` Alistair Francis
2021-10-17 22:55     ` Alistair Francis
2021-10-18  5:38     ` Richard Henderson
2021-10-18  5:38       ` Richard Henderson
2021-10-18  6:01   ` Alistair Francis
2021-10-18  6:01     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH 18/76] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-18  5:44   ` Alistair Francis
2021-10-18  5:44     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH 20/76] target/riscv: rvv-1.0: index " frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 20/78] target/riscv: rvv-1.0: stride " frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH 23/76] target/riscv: rvv-1.0: amo operations frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-18  5:46   ` Alistair Francis
2021-10-18  5:46     ` Alistair Francis
2021-10-15  7:45 ` [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-18  5:47   ` Alistair Francis
2021-10-18  5:47     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-18  5:53   ` Alistair Francis
2021-10-18  5:53     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-18  5:49   ` Alistair Francis
2021-10-18  5:49     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-18  5:54   ` Alistair Francis
2021-10-18  5:54     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-21  4:28   ` Alistair Francis
2021-10-21  4:28     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-21  4:24   ` Alistair Francis
2021-10-21  4:24     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-21  4:26   ` Alistair Francis
2021-10-21  4:26     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 39/78] target/riscv: rvv-1.0: whole register " frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-21  4:27   ` Alistair Francis
2021-10-21  4:27     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-25  6:08   ` Alistair Francis
2021-10-25  6:08     ` Alistair Francis
2021-10-15  7:45 ` [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-15  7:45 ` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point " frank.chang
2021-10-15  7:45   ` frank.chang
2021-10-25  6:13   ` Alistair Francis
2021-10-25  6:13     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-25  6:16   ` Alistair Francis
2021-10-25  6:16     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-26  6:29   ` Alistair Francis
2021-10-26  6:29     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-26  6:30   ` Alistair Francis
2021-10-26  6:30     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-26  6:32   ` Alistair Francis
2021-10-26  6:32     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-25  6:43   ` Alistair Francis [this message]
2021-10-25  6:43     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-25  6:42   ` Alistair Francis
2021-10-25  6:42     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-26  6:50   ` Alistair Francis
2021-10-26  6:50     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-26  6:52   ` Alistair Francis
2021-10-26  6:52     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-15  7:46 ` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-26  6:55   ` Alistair Francis
2021-10-26  6:55     ` Alistair Francis
2021-10-15  7:46 ` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang
2021-10-15  7:46   ` frank.chang
2021-10-26  6:49   ` Alistair Francis
2021-10-26  6:49     ` Alistair Francis
2021-10-15  9:02 ` [PATCH v8 00/78] support vector extension v1.0 Frank Chang
2021-10-15  9:02   ` Frank Chang
2021-10-18  6:00 ` Alistair Francis
2021-10-18  6:00   ` Alistair Francis
2021-10-18  6:09   ` Frank Chang
2021-10-18  6:09     ` Frank Chang
2021-10-18  6:12     ` Alistair Francis
2021-10-18  6:12       ` Alistair Francis
2021-10-18  6:17       ` Frank Chang
2021-10-18  6:17         ` Frank Chang
2021-10-18  9:01 ` LIU Zhiwei
2021-10-18  9:34   ` LIU Zhiwei
2021-10-20  5:28     ` Alistair Francis
2021-10-20  5:28       ` Alistair Francis

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