From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, frank.chang@sifive.com, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, frederic.petrot@univ-grenoble-alpes.fr, zhiwei_liu@c-sky.com Subject: [PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length Date: Sat, 16 Oct 2021 10:13:58 -0700 [thread overview] Message-ID: <20211016171412.3163784-1-richard.henderson@linaro.org> (raw) This is a partial patch set attempting to set things in the right direction for both the UXL and RV128 patch sets. Notable addition for v3 is the treatment of [MS]STATUS.SD. Because this bit changes position depending on XLEN, it's better to split it out. But since it's read-only and computable from [MS]STATUS.{FS,XS}, it is even better to not store it at all. I noticed this while reading Frank's RVV patches which add VS to be included in SD. r~ Changes for v3: * Fix CONFIG_ typo. * Fix ctzw typo. * Mark get_xlen unused (clang werror) * Compute MSTATUS_SD on demand. Changes for v2: * Set mxl/sxl/uxl at reset. * Set sxl/uxl in write_mstatus. Richard Henderson (14): target/riscv: Move cpu_get_tb_cpu_state out of line target/riscv: Create RISCVMXL enumeration target/riscv: Split misa.mxl and misa.ext target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Properly check SEW in amo_op target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Use gen_arith_per_ol for RVM target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_unary_per_ol for RVB target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Compute mstatus.sd on demand target/riscv/cpu.h | 73 +++------- target/riscv/cpu_bits.h | 8 +- hw/riscv/boot.c | 2 +- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 108 +++++++++------ target/riscv/cpu_helper.c | 92 ++++++++++++- target/riscv/csr.c | 104 ++++++++------ target/riscv/gdbstub.c | 10 +- target/riscv/machine.c | 10 +- target/riscv/monitor.c | 4 +- target/riscv/translate.c | 174 ++++++++++++++++++------ target/riscv/insn_trans/trans_rvb.c.inc | 140 ++++++++++--------- target/riscv/insn_trans/trans_rvi.c.inc | 44 +++--- target/riscv/insn_trans/trans_rvm.c.inc | 36 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++-- 17 files changed, 532 insertions(+), 308 deletions(-) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, fabien.portas@grenoble-inp.org, zhiwei_liu@c-sky.com, frank.chang@sifive.com Subject: [PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length Date: Sat, 16 Oct 2021 10:13:58 -0700 [thread overview] Message-ID: <20211016171412.3163784-1-richard.henderson@linaro.org> (raw) This is a partial patch set attempting to set things in the right direction for both the UXL and RV128 patch sets. Notable addition for v3 is the treatment of [MS]STATUS.SD. Because this bit changes position depending on XLEN, it's better to split it out. But since it's read-only and computable from [MS]STATUS.{FS,XS}, it is even better to not store it at all. I noticed this while reading Frank's RVV patches which add VS to be included in SD. r~ Changes for v3: * Fix CONFIG_ typo. * Fix ctzw typo. * Mark get_xlen unused (clang werror) * Compute MSTATUS_SD on demand. Changes for v2: * Set mxl/sxl/uxl at reset. * Set sxl/uxl in write_mstatus. Richard Henderson (14): target/riscv: Move cpu_get_tb_cpu_state out of line target/riscv: Create RISCVMXL enumeration target/riscv: Split misa.mxl and misa.ext target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Properly check SEW in amo_op target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Use gen_arith_per_ol for RVM target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_unary_per_ol for RVB target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Compute mstatus.sd on demand target/riscv/cpu.h | 73 +++------- target/riscv/cpu_bits.h | 8 +- hw/riscv/boot.c | 2 +- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 108 +++++++++------ target/riscv/cpu_helper.c | 92 ++++++++++++- target/riscv/csr.c | 104 ++++++++------ target/riscv/gdbstub.c | 10 +- target/riscv/machine.c | 10 +- target/riscv/monitor.c | 4 +- target/riscv/translate.c | 174 ++++++++++++++++++------ target/riscv/insn_trans/trans_rvb.c.inc | 140 ++++++++++--------- target/riscv/insn_trans/trans_rvi.c.inc | 44 +++--- target/riscv/insn_trans/trans_rvm.c.inc | 36 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++-- 17 files changed, 532 insertions(+), 308 deletions(-) -- 2.25.1
next reply other threads:[~2021-10-16 17:18 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-16 17:13 Richard Henderson [this message] 2021-10-16 17:13 ` [PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length Richard Henderson 2021-10-16 17:13 ` [PATCH v3 01/14] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson 2021-10-16 17:13 ` Richard Henderson 2021-10-16 17:14 ` [PATCH v3 02/14] target/riscv: Create RISCVMXL enumeration Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-16 17:14 ` [PATCH v3 03/14] target/riscv: Split misa.mxl and misa.ext Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-18 11:46 ` LIU Zhiwei 2021-10-18 11:46 ` LIU Zhiwei 2021-10-16 17:14 ` [PATCH v3 04/14] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-18 11:51 ` LIU Zhiwei 2021-10-18 11:51 ` LIU Zhiwei 2021-10-16 17:14 ` [PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-18 11:55 ` LIU Zhiwei 2021-10-18 11:55 ` LIU Zhiwei 2021-10-16 17:14 ` [PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-16 17:14 ` [PATCH v3 07/14] target/riscv: Properly check SEW in amo_op Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-16 17:14 ` [PATCH v3 08/14] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-16 17:14 ` [PATCH v3 09/14] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-16 17:14 ` [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-18 4:36 ` Alistair Francis 2021-10-18 4:36 ` Alistair Francis 2021-10-16 17:14 ` [PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-16 17:14 ` [PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-18 4:37 ` Alistair Francis 2021-10-18 4:37 ` Alistair Francis 2021-10-16 17:14 ` [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-18 4:43 ` Alistair Francis 2021-10-18 4:43 ` Alistair Francis 2021-10-16 17:14 ` [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand Richard Henderson 2021-10-16 17:14 ` Richard Henderson 2021-10-18 4:52 ` Alistair Francis 2021-10-18 4:52 ` Alistair Francis 2021-10-18 5:31 ` Richard Henderson 2021-10-18 5:31 ` Richard Henderson 2021-10-18 5:38 ` Alistair Francis 2021-10-18 5:38 ` Alistair Francis 2021-10-18 6:05 ` Richard Henderson 2021-10-18 6:05 ` Richard Henderson
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