From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Frank Chang" <frank.chang@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Fabien Portas" <fabien.portas@grenoble-inp.org>,
"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
Date: Sun, 17 Oct 2021 23:05:16 -0700 [thread overview]
Message-ID: <f2d38eb6-9eda-9335-fc10-86b06e374876@linaro.org> (raw)
In-Reply-To: <CAKmqyKOQ5UQgY0z2B5H+e5ra_cWz_JZKjtEmnm5er5gs7wWtQw@mail.gmail.com>
On 10/17/21 10:38 PM, Alistair Francis wrote:
> Do we get much of an advantage from this though? To me it seems
> confusing that the mstatus register doesn't actually contain the
> latest value (for example when debugging QEMU and adding my own
> printf's).
(1) We have at least 3 places that need to check the cpu state in order to set SD
correctly; we would add another couple with the VS bit that's coming in from RVV-1.0. By
setting this bit during read, we reduce that to one accessor for read.
(2) We would need to move this bit when changing MXL, once that's possible with the
various XLEN changing patch sets.
(3) The position of this bit, between MSTATUS and SSTATUS, differs if MXL != SXL, which
means that there is not really one correct setting for (2).
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"Frank Chang" <frank.chang@sifive.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Fabien Portas" <fabien.portas@grenoble-inp.org>,
"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
Date: Sun, 17 Oct 2021 23:05:16 -0700 [thread overview]
Message-ID: <f2d38eb6-9eda-9335-fc10-86b06e374876@linaro.org> (raw)
In-Reply-To: <CAKmqyKOQ5UQgY0z2B5H+e5ra_cWz_JZKjtEmnm5er5gs7wWtQw@mail.gmail.com>
On 10/17/21 10:38 PM, Alistair Francis wrote:
> Do we get much of an advantage from this though? To me it seems
> confusing that the mstatus register doesn't actually contain the
> latest value (for example when debugging QEMU and adding my own
> printf's).
(1) We have at least 3 places that need to check the cpu state in order to set SD
correctly; we would add another couple with the VS bit that's coming in from RVV-1.0. By
setting this bit during read, we reduce that to one accessor for read.
(2) We would need to move this bit when changing MXL, once that's possible with the
various XLEN changing patch sets.
(3) The position of this bit, between MSTATUS and SSTATUS, differs if MXL != SXL, which
means that there is not really one correct setting for (2).
r~
next prev parent reply other threads:[~2021-10-18 6:07 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-16 17:13 [PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-16 17:13 ` Richard Henderson
2021-10-16 17:13 ` [PATCH v3 01/14] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-16 17:13 ` Richard Henderson
2021-10-16 17:14 ` [PATCH v3 02/14] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-16 17:14 ` [PATCH v3 03/14] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-18 11:46 ` LIU Zhiwei
2021-10-18 11:46 ` LIU Zhiwei
2021-10-16 17:14 ` [PATCH v3 04/14] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-18 11:51 ` LIU Zhiwei
2021-10-18 11:51 ` LIU Zhiwei
2021-10-16 17:14 ` [PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-18 11:55 ` LIU Zhiwei
2021-10-18 11:55 ` LIU Zhiwei
2021-10-16 17:14 ` [PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-16 17:14 ` [PATCH v3 07/14] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-16 17:14 ` [PATCH v3 08/14] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-16 17:14 ` [PATCH v3 09/14] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-16 17:14 ` [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-18 4:36 ` Alistair Francis
2021-10-18 4:36 ` Alistair Francis
2021-10-16 17:14 ` [PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-16 17:14 ` [PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-18 4:37 ` Alistair Francis
2021-10-18 4:37 ` Alistair Francis
2021-10-16 17:14 ` [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-18 4:43 ` Alistair Francis
2021-10-18 4:43 ` Alistair Francis
2021-10-16 17:14 ` [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-16 17:14 ` Richard Henderson
2021-10-18 4:52 ` Alistair Francis
2021-10-18 4:52 ` Alistair Francis
2021-10-18 5:31 ` Richard Henderson
2021-10-18 5:31 ` Richard Henderson
2021-10-18 5:38 ` Alistair Francis
2021-10-18 5:38 ` Alistair Francis
2021-10-18 6:05 ` Richard Henderson [this message]
2021-10-18 6:05 ` Richard Henderson
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