* [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP
@ 2021-10-18 6:52 Vandita Kulkarni
2021-10-18 6:52 ` [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Vandita Kulkarni
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: Vandita Kulkarni @ 2021-10-18 6:52 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, imre.deak, matthew.d.roper, Vandita Kulkarni
Vandita Kulkarni (4):
drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
drm/i915/dsi/xelpd: Add DSI transcoder support
drm/i915/dsi/xelpd: Disable DC states in Video mode
drm/i915/dsi: Ungate clock before enabling the phy
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++---
.../drm/i915/display/intel_display_power.c | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 31 +++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 3 +-
4 files changed, 36 insertions(+), 11 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
@ 2021-10-18 6:52 ` Vandita Kulkarni
2021-10-19 10:05 ` Jani Nikula
2021-10-18 6:52 ` [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support Vandita Kulkarni
` (5 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Vandita Kulkarni @ 2021-10-18 6:52 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, imre.deak, matthew.d.roper, Vandita Kulkarni
Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9ee62707ec72..8c166f92f8bd 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
if (DISPLAY_VER(i915) == 13) {
for_each_dsi_port(port, intel_dsi->ports)
intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
- TGL_DSI_CHKN_LSHS_GB, 0x4);
+ TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..e4b1f80ca5eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11728,7 +11728,8 @@ enum skl_power_gate {
#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
_TGL_DSI_CHKN_REG_0, \
_TGL_DSI_CHKN_REG_1)
-#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, 4)
/* Display Stream Splitter Control */
#define DSS_CTL1 _MMIO(0x67400)
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
2021-10-18 6:52 ` [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Vandita Kulkarni
@ 2021-10-18 6:52 ` Vandita Kulkarni
2021-10-19 10:13 ` Jani Nikula
2021-10-18 6:52 ` [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode Vandita Kulkarni
` (4 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Vandita Kulkarni @ 2021-10-18 6:52 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, imre.deak, matthew.d.roper, Vandita Kulkarni
Update ADL_P device info to support DSI0, DSI1
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..a2dd5a38fdf5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info = {
#define XE_LPD_FEATURES \
.abox_mask = GENMASK(1, 0), \
.color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
.dbuf.size = 4096, \
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
BIT(DBUF_S4), \
@@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
.display.has_psr = 1, \
.display.ver = 13, \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ XE_LPD_CURSOR_OFFSETS
+
+#define ADLP_TRANSCODERS \
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
[TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
}, \
.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ } \
+
+#define DG2_TRANSCODERS \
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
}, \
- XE_LPD_CURSOR_OFFSETS
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ } \
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
XE_LPD_FEATURES,
+ ADLP_TRANSCODERS,
PLATFORM(INTEL_ALDERLAKE_P),
.require_force_probe = 1,
.display.has_cdclk_crawl = 1,
@@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
XE_HP_FEATURES,
XE_HPM_FEATURES,
XE_LPD_FEATURES,
+ DG2_TRANSCODERS,
DGFX_FEATURES,
.graphics_rel = 55,
.media_rel = 55,
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
2021-10-18 6:52 ` [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Vandita Kulkarni
2021-10-18 6:52 ` [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support Vandita Kulkarni
@ 2021-10-18 6:52 ` Vandita Kulkarni
2021-10-19 10:24 ` Jani Nikula
2021-10-18 6:52 ` [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy Vandita Kulkarni
` (3 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Vandita Kulkarni @ 2021-10-18 6:52 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, imre.deak, matthew.d.roper, Vandita Kulkarni
MIPI DSI transcoder cannot be in video mode to support any of the
display C states.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 709569211c85..8406db5e573e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+ BIT_ULL(POWER_DOMAIN_INIT)) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI)
#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
` (2 preceding siblings ...)
2021-10-18 6:52 ` [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode Vandita Kulkarni
@ 2021-10-18 6:52 ` Vandita Kulkarni
2021-10-19 10:18 ` Jani Nikula
2021-10-18 7:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Vandita Kulkarni @ 2021-10-18 6:52 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, imre.deak, matthew.d.roper, Vandita Kulkarni
For the PHY enable/disable signalling to propagate
between Dispaly and PHY, DDI clocks need to be running when
enabling the PHY.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8c166f92f8bd..77cd01ecfa80 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1135,8 +1135,6 @@ static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
/* step 4a: power up all lanes of the DDI used by DSI */
gen11_dsi_power_up_lanes(encoder);
@@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* step 4c: configure voltage swing and skew */
gen11_dsi_voltage_swing_program_seq(encoder);
+ gen11_dsi_ungate_clocks(encoder);
+
/* enable DDI buffer */
gen11_dsi_enable_ddi_buffer(encoder);
@@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
gen11_dsi_configure_transcoder(encoder, crtc_state);
- /* Step 4l: Gate DDI clocks */
- if (DISPLAY_VER(dev_priv) == 11)
- gen11_dsi_gate_clocks(encoder);
+ gen11_dsi_gate_clocks(encoder);
}
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
` (3 preceding siblings ...)
2021-10-18 6:52 ` [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy Vandita Kulkarni
@ 2021-10-18 7:13 ` Patchwork
2021-10-18 7:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-18 9:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-10-18 7:13 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
== Series Details ==
Series: Enable MIPI DSI video mode on ADLP
URL : https://patchwork.freedesktop.org/series/95928/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable MIPI DSI video mode on ADLP
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
` (4 preceding siblings ...)
2021-10-18 7:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP Patchwork
@ 2021-10-18 7:43 ` Patchwork
2021-10-18 9:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-10-18 7:43 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4791 bytes --]
== Series Details ==
Series: Enable MIPI DSI video mode on ADLP
URL : https://patchwork.freedesktop.org/series/95928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10750 -> Patchwork_21364
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/index.html
Known issues
------------
Here are the changes found in Patchwork_21364 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-kbl-soraka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-bsw-n3050/igt@amdgpu/amd_cs_nop@sync-gfx0.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
* igt@i915_module_load@reload:
- fi-kbl-soraka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/fi-kbl-soraka/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-kbl-soraka/igt@i915_module_load@reload.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][7] -> [FAIL][8] ([i915#4165]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
* igt@kms_flip@basic-plain-flip@c-dp2:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#295]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html
#### Possible fixes ####
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-n3050: [DMESG-FAIL][11] ([i915#2927] / [i915#3428]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
#### Warnings ####
* igt@kms_flip@basic-plain-flip@c-dp1:
- fi-cfl-8109u: [FAIL][13] ([i915#4165]) -> [DMESG-WARN][14] ([i915#295])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
Participating hosts (41 -> 36)
------------------------------
Missing (5): bat-dg1-6 fi-hsw-4200u bat-dg1-5 fi-bsw-cyan fi-kbl-7500u
Build changes
-------------
* Linux: CI_DRM_10750 -> Patchwork_21364
CI-20190529: 20190529
CI_DRM_10750: 7df3fd87528d6d245e5101cc32518ac649aeea98 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6251: 01b6be842d74fb86f3226acb4ddcb85231f4b161 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21364: ee4291972bfaccbc5346c168de21b715aeae867f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ee4291972bfa drm/i915/dsi: Ungate clock before enabling the phy
8aa18dc8fe29 drm/i915/dsi/xelpd: Disable DC states in Video mode
b325a854f9bc drm/i915/dsi/xelpd: Add DSI transcoder support
fded35f39772 drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/index.html
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable MIPI DSI video mode on ADLP
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
` (5 preceding siblings ...)
2021-10-18 7:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-18 9:01 ` Patchwork
6 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-10-18 9:01 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30257 bytes --]
== Series Details ==
Series: Enable MIPI DSI video mode on ADLP
URL : https://patchwork.freedesktop.org/series/95928/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10750_full -> Patchwork_21364_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21364_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21364_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21364_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb8/igt@i915_pm_rpm@modeset-lpsp-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb7/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_bw@linear-tiling-3-displays-3840x2160p:
- shard-skl: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl7/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html
Known issues
------------
Here are the changes found in Patchwork_21364_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-tglb: NOTRUN -> [SKIP][4] ([fdo#111827])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@feature_discovery@chamelium.html
* igt@feature_discovery@display-2x:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#1839])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@feature_discovery@display-2x.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +4 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-snb2/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][7] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-glk3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb5/igt@gem_exec_fair@basic-pace@bcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_store@basic:
- shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-skl1/igt@gem_exec_store@basic.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl5/igt@gem_exec_store@basic.html
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [PASS][16] -> [DMESG-WARN][17] ([i915#118])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-glk3/igt@gem_exec_whisper@basic-contexts-all.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-glk4/igt@gem_exec_whisper@basic-contexts-all.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4270])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][20] ([i915#3002])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl8/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#3297])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][22] ([i915#3318])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl7/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
* igt@gen7_exec_parse@basic-offset:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +219 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl7/igt@gen7_exec_parse@basic-offset.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl7/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#109506] / [i915#2411])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-tglb: [PASS][28] -> [INCOMPLETE][29] ([i915#456] / [i915#750])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb6/igt@i915_suspend@fence-restore-tiled2untiled.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][30] ([i915#3722])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_bw@linear-tiling-2-displays-3840x2160p:
- shard-skl: NOTRUN -> [DMESG-FAIL][33] ([i915#4298])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-4-displays-3840x2160p:
- shard-apl: NOTRUN -> [DMESG-FAIL][34] ([i915#4298])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl8/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl7/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][36] ([i915#3689] / [i915#3886])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +11 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl8/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#3689])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][40] ([fdo#109271]) +284 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-snb5/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-snb: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +17 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-snb5/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_chamelium@vga-frame-dump:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +5 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl7/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271]) +78 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +18 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl2/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-c-gamma:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@kms_color_chamelium@pipe-c-gamma.html
* igt@kms_content_protection@mei_interface:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#111828])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@kms_content_protection@mei_interface.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][48] ([i915#1319])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl8/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- shard-glk: [PASS][49] -> [FAIL][50] ([i915#3444])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-glk2/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109278])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb4/igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][52] -> [INCOMPLETE][53] ([i915#4211])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_dsc@xrgb8888-dsc-compression:
- shard-tglb: NOTRUN -> [SKIP][54] ([i915#3828])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb3/igt@kms_dsc@xrgb8888-dsc-compression.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
- shard-glk: [PASS][55] -> [FAIL][56] ([i915#2122])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-glk6/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-glk2/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-skl: NOTRUN -> [INCOMPLETE][57] ([i915#3699])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#2672])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2672]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-iclb: [PASS][60] -> [SKIP][61] ([i915#3701])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_tiling@flip-changes-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][62] ([fdo#111615])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb3/igt@kms_flip_tiling@flip-changes-tiling-yf.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#111825]) +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271]) +97 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][65] -> [FAIL][66] ([i915#1188])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-skl3/igt@kms_hdr@bpc-switch.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl5/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][67] -> [DMESG-WARN][68] ([i915#180]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
- shard-kbl: NOTRUN -> [FAIL][73] ([fdo#108145] / [i915#265]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][74] ([i915#265])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2733])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2733])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +4 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
- shard-tglb: NOTRUN -> [SKIP][79] ([i915#2920])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb5/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][83] ([IGT#2])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl6/igt@kms_sysfs_edid_timing.html
* igt@kms_tv_load_detect@load-detect:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#109309])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-tglb: [PASS][85] -> [INCOMPLETE][86] ([i915#2828] / [i915#456])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2437])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl2/igt@kms_writeback@writeback-fb-id.html
- shard-kbl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2437])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl7/igt@kms_writeback@writeback-fb-id.html
* igt@prime_nv_pcopy@test1_micro:
- shard-tglb: NOTRUN -> [SKIP][89] ([fdo#109291])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb3/igt@prime_nv_pcopy@test1_micro.html
* igt@prime_vgem@fence-write-hang:
- shard-tglb: NOTRUN -> [SKIP][90] ([fdo#109295])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@prime_vgem@fence-write-hang.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl7/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@pidname:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#2994])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@sysfs_clients@pidname.html
- shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl3/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [FAIL][94] ([i915#2842]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][98] ([i915#2842]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][100] ([i915#2849]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [DMESG-WARN][102] ([i915#118]) -> [PASS][103] +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-glk9/igt@gem_exec_whisper@basic-queues-all.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html
* igt@gem_softpin@noreloc-s3:
- shard-tglb: [INCOMPLETE][104] ([i915#1373] / [i915#456]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb7/igt@gem_softpin@noreloc-s3.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@gem_softpin@noreloc-s3.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][106] ([i915#1436] / [i915#716]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][108] ([i915#454]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@fences-dpms:
- shard-iclb: [INCOMPLETE][110] ([i915#2910]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb7/igt@i915_pm_rpm@fences-dpms.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb4/igt@i915_pm_rpm@fences-dpms.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [INCOMPLETE][112] ([i915#3614]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-kbl3/igt@i915_suspend@debugfs-reader.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl7/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][114] ([i915#180]) -> [PASS][115] +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-apl2/igt@i915_suspend@sysfs-reader.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-apl7/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +5 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglb: [INCOMPLETE][118] ([i915#456]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb7/igt@kms_fbcon_fbt@psr-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb3/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-iclb: [FAIL][120] ([i915#79]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-tglb: [INCOMPLETE][122] ([i915#2411] / [i915#456]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-tglb8/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][124] ([i915#2122]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][126] ([fdo#108145] / [i915#265]) -> [PASS][127] +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][128] ([fdo#109441]) -> [PASS][129] +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@perf@blocking:
- shard-skl: [FAIL][130] ([i915#1542]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-skl8/igt@perf@blocking.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl2/igt@perf@blocking.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][132] ([i915#2684]) -> [WARN][133] ([i915#1804] / [i915#2684])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: [FAIL][134] ([i915#3743]) -> [FAIL][135] ([i915#3722])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][136] ([i915#2920]) -> [SKIP][137] ([i915#658])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][138] ([i915#658]) -> [SKIP][139] ([i915#2920]) +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10750/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@runner@aborted:
- sha
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21364/index.html
[-- Attachment #2: Type: text/html, Size: 33591 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
2021-10-18 6:52 ` [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Vandita Kulkarni
@ 2021-10-19 10:05 ` Jani Nikula
2021-10-19 10:15 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-10-19 10:05 UTC (permalink / raw)
To: Vandita Kulkarni, intel-gfx; +Cc: imre.deak, matthew.d.roper, Vandita Kulkarni
On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
Commit message goes here.
> Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 9ee62707ec72..8c166f92f8bd 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
> if (DISPLAY_VER(i915) == 13) {
> for_each_dsi_port(port, intel_dsi->ports)
> intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> - TGL_DSI_CHKN_LSHS_GB, 0x4);
> + TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
BR,
Jani.
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c..e4b1f80ca5eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11728,7 +11728,8 @@ enum skl_power_gate {
> #define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
> _TGL_DSI_CHKN_REG_0, \
> _TGL_DSI_CHKN_REG_1)
> -#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, 4)
>
> /* Display Stream Splitter Control */
> #define DSS_CTL1 _MMIO(0x67400)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
2021-10-18 6:52 ` [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support Vandita Kulkarni
@ 2021-10-19 10:13 ` Jani Nikula
2021-10-19 11:40 ` Kulkarni, Vandita
0 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-10-19 10:13 UTC (permalink / raw)
To: Vandita Kulkarni, intel-gfx; +Cc: imre.deak, matthew.d.roper, Vandita Kulkarni
On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Update ADL_P device info to support DSI0, DSI1
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..a2dd5a38fdf5 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info = {
> #define XE_LPD_FEATURES \
> .abox_mask = GENMASK(1, 0), \
> .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
> .dbuf.size = 4096, \
> .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
> BIT(DBUF_S4), \
> @@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
> .display.has_psr = 1, \
> .display.ver = 13, \
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + XE_LPD_CURSOR_OFFSETS
> +
> +#define ADLP_TRANSCODERS \
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> [TRANSCODER_C] = PIPE_C_OFFSET, \
> [TRANSCODER_D] = PIPE_D_OFFSET, \
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> }, \
> .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
I think you could just add these changes to XE_LPD_FEATURES, and have
separate .cpu_transcoder_mask initialization for ADLP and DG2.
Compare GEN12_FEATURES.
BR,
Jani.
> + } \
> +
> +#define DG2_TRANSCODERS \
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + [TRANSCODER_D] = PIPE_D_OFFSET, \
> }, \
> - XE_LPD_CURSOR_OFFSETS
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> + } \
>
> static const struct intel_device_info adl_p_info = {
> GEN12_FEATURES,
> XE_LPD_FEATURES,
> + ADLP_TRANSCODERS,
> PLATFORM(INTEL_ALDERLAKE_P),
> .require_force_probe = 1,
> .display.has_cdclk_crawl = 1,
> @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
> XE_HP_FEATURES,
> XE_HPM_FEATURES,
> XE_LPD_FEATURES,
> + DG2_TRANSCODERS,
> DGFX_FEATURES,
> .graphics_rel = 55,
> .media_rel = 55,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
2021-10-19 10:05 ` Jani Nikula
@ 2021-10-19 10:15 ` Ville Syrjälä
2021-10-19 10:28 ` Jani Nikula
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2021-10-19 10:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: Vandita Kulkarni, intel-gfx, imre.deak, matthew.d.roper
On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>
> Commit message goes here.
>
> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> > 2 files changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 9ee62707ec72..8c166f92f8bd 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
> > if (DISPLAY_VER(i915) == 13) {
> > for_each_dsi_port(port, intel_dsi->ports)
> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
> > + TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
>
> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
IMO the value should never be named that. It should be
TGL_DSI_CHKN_LSHS_GB_<something>.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
2021-10-18 6:52 ` [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy Vandita Kulkarni
@ 2021-10-19 10:18 ` Jani Nikula
2021-10-19 11:32 ` Kulkarni, Vandita
0 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-10-19 10:18 UTC (permalink / raw)
To: Vandita Kulkarni, intel-gfx; +Cc: imre.deak, matthew.d.roper, Vandita Kulkarni
On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> For the PHY enable/disable signalling to propagate
> between Dispaly and PHY, DDI clocks need to be running when
> enabling the PHY.
>
A bspec reference would be useful:
Bspec: NNN
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 8c166f92f8bd..77cd01ecfa80 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1135,8 +1135,6 @@ static void
> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -
> /* step 4a: power up all lanes of the DDI used by DSI */
> gen11_dsi_power_up_lanes(encoder);
>
> @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> /* step 4c: configure voltage swing and skew */
> gen11_dsi_voltage_swing_program_seq(encoder);
>
> + gen11_dsi_ungate_clocks(encoder);
> +
> /* enable DDI buffer */
> gen11_dsi_enable_ddi_buffer(encoder);
>
> @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> gen11_dsi_configure_transcoder(encoder, crtc_state);
>
> - /* Step 4l: Gate DDI clocks */
> - if (DISPLAY_VER(dev_priv) == 11)
> - gen11_dsi_gate_clocks(encoder);
> + gen11_dsi_gate_clocks(encoder);
So how does this relate to
991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
> }
>
> static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
2021-10-18 6:52 ` [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode Vandita Kulkarni
@ 2021-10-19 10:24 ` Jani Nikula
2021-10-19 12:08 ` Imre Deak
0 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-10-19 10:24 UTC (permalink / raw)
To: Vandita Kulkarni, intel-gfx; +Cc: imre.deak, matthew.d.roper, Vandita Kulkarni
On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> MIPI DSI transcoder cannot be in video mode to support any of the
> display C states.
Imre, could you review this one please?
The added confusion is that POWER_DOMAIN_TRANSCODER_DSI_A and
POWER_DOMAIN_TRANSCODER_DSI_C are never used anywhere and
POWER_DOMAIN_TRANSCODER() does not take DSI transcoders into account.
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 709569211c85..8406db5e573e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_INIT)) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DSI)
Everywhere else POWER_DOMAIN_INIT is last in the list.
BR,
Jani.
>
> #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
2021-10-19 10:15 ` Ville Syrjälä
@ 2021-10-19 10:28 ` Jani Nikula
2021-10-19 10:41 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-10-19 10:28 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Vandita Kulkarni, intel-gfx, imre.deak, matthew.d.roper
On Tue, 19 Oct 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
>> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>>
>> Commit message goes here.
>>
>> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
>> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
>> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
>> > 2 files changed, 3 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > index 9ee62707ec72..8c166f92f8bd 100644
>> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
>> > if (DISPLAY_VER(i915) == 13) {
>> > for_each_dsi_port(port, intel_dsi->ports)
>> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
>> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
>> > + TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
>>
>> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
>
> IMO the value should never be named that. It should be
> TGL_DSI_CHKN_LSHS_GB_<something>.
Alternatively,
#define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
and
intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
?
We're using the value in a specific place that references a w/a, so the
magic 4 isn't too bad.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
2021-10-19 10:28 ` Jani Nikula
@ 2021-10-19 10:41 ` Ville Syrjälä
2021-10-19 10:50 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2021-10-19 10:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: Vandita Kulkarni, intel-gfx, imre.deak, matthew.d.roper
On Tue, Oct 19, 2021 at 01:28:10PM +0300, Jani Nikula wrote:
> On Tue, 19 Oct 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> >> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> >>
> >> Commit message goes here.
> >>
> >> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
> >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> >> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> >> > 2 files changed, 3 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > index 9ee62707ec72..8c166f92f8bd 100644
> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
> >> > if (DISPLAY_VER(i915) == 13) {
> >> > for_each_dsi_port(port, intel_dsi->ports)
> >> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> >> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
> >> > + TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
> >>
> >> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
> >
> > IMO the value should never be named that. It should be
> > TGL_DSI_CHKN_LSHS_GB_<something>.
>
> Alternatively,
>
> #define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
>
> and
>
> intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
>
> ?
>
> We're using the value in a specific place that references a w/a, so the
> magic 4 isn't too bad.
Yeah, for parametrized defines I think the "_<something>" is
not needed. Probably not even desired. The argument passed in
is the "_<something>" essentially.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
2021-10-19 10:41 ` Ville Syrjälä
@ 2021-10-19 10:50 ` Ville Syrjälä
2021-10-19 11:27 ` Kulkarni, Vandita
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2021-10-19 10:50 UTC (permalink / raw)
To: Jani Nikula; +Cc: Vandita Kulkarni, intel-gfx, imre.deak, matthew.d.roper
On Tue, Oct 19, 2021 at 01:41:50PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 19, 2021 at 01:28:10PM +0300, Jani Nikula wrote:
> > On Tue, 19 Oct 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > > On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> > >> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> > >>
> > >> Commit message goes here.
> > >>
> > >> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
> > >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > >> > ---
> > >> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > >> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> > >> > 2 files changed, 3 insertions(+), 2 deletions(-)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> > index 9ee62707ec72..8c166f92f8bd 100644
> > >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
> > >> > if (DISPLAY_VER(i915) == 13) {
> > >> > for_each_dsi_port(port, intel_dsi->ports)
> > >> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > >> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
> > >> > + TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
> > >>
> > >> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
> > >
> > > IMO the value should never be named that. It should be
> > > TGL_DSI_CHKN_LSHS_GB_<something>.
> >
> > Alternatively,
> >
> > #define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
> >
> > and
> >
> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
> >
> > ?
> >
> > We're using the value in a specific place that references a w/a, so the
> > magic 4 isn't too bad.
>
> Yeah, for parametrized defines I think the "_<something>" is
> not needed. Probably not even desired. The argument passed in
> is the "_<something>" essentially.
Oh and, yes, I think having the magic number in the code is fine
for cases like this. I'd say I probably even prefer it that way.
As long as the whole register value isn't a single magic hex constant
that I have to decode by hand to see what bitfields are getting what
values.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
2021-10-19 10:50 ` Ville Syrjälä
@ 2021-10-19 11:27 ` Kulkarni, Vandita
0 siblings, 0 replies; 24+ messages in thread
From: Kulkarni, Vandita @ 2021-10-19 11:27 UTC (permalink / raw)
To: Ville Syrjälä, Nikula, Jani
Cc: intel-gfx, Deak, Imre, Roper, Matthew D
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, October 19, 2021 4:21 PM
> To: Nikula, Jani <jani.nikula@intel.com>
> Cc: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org; Deak, Imre <imre.deak@intel.com>; Roper,
> Matthew D <matthew.d.roper@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for
> wakeup GB
>
> On Tue, Oct 19, 2021 at 01:41:50PM +0300, Ville Syrjälä wrote:
> > On Tue, Oct 19, 2021 at 01:28:10PM +0300, Jani Nikula wrote:
> > > On Tue, 19 Oct 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > > > On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> > > >> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com>
> wrote:
> > > >>
> > > >> Commit message goes here.
> > > >>
> > > >> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP
> > > >> > to HS wakeup guardband")
> > > >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > >> > ---
> > > >> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > > >> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> > > >> > 2 files changed, 3 insertions(+), 2 deletions(-)
> > > >> >
> > > >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > index 9ee62707ec72..8c166f92f8bd 100644
> > > >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > @@ -1271,7 +1271,7 @@ static void
> adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
> > > >> > if (DISPLAY_VER(i915) == 13) {
> > > >> > for_each_dsi_port(port, intel_dsi->ports)
> > > >> > intel_de_rmw(i915,
> TGL_DSI_CHKN_REG(port),
> > > >> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
> > > >> > + TGL_DSI_CHKN_LSHS_GB_MASK,
> > > >> > +TGL_DSI_CHKN_LSHS_GB_MASK);
> > > >>
> > > >> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
Yes, my bad.
> > > >
> > > > IMO the value should never be named that. It should be
> > > > TGL_DSI_CHKN_LSHS_GB_<something>.
> > >
> > > Alternatively,
> > >
> > > #define TGL_DSI_CHKN_LSHS_GB(byte_clocks)
> REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
> > >
> > > and
> > >
> > > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > > TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
> > >
> > > ?
> > >
> > > We're using the value in a specific place that references a w/a, so
> > > the magic 4 isn't too bad.
This seems more appropriate will make this change.
Thanks.
> >
> > Yeah, for parametrized defines I think the "_<something>" is not
> > needed. Probably not even desired. The argument passed in is the
> > "_<something>" essentially.
>
> Oh and, yes, I think having the magic number in the code is fine for cases like
> this. I'd say I probably even prefer it that way.
> As long as the whole register value isn't a single magic hex constant that I
> have to decode by hand to see what bitfields are getting what values.
Thanks, will use the hardcoding in icl_dsi.
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
2021-10-19 10:18 ` Jani Nikula
@ 2021-10-19 11:32 ` Kulkarni, Vandita
2021-10-19 11:43 ` Kulkarni, Vandita
2021-10-19 11:46 ` Jani Nikula
0 siblings, 2 replies; 24+ messages in thread
From: Kulkarni, Vandita @ 2021-10-19 11:32 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Deak, Imre, Roper, Matthew D
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, October 19, 2021 3:48 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>
> Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>
> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> > For the PHY enable/disable signalling to propagate between Dispaly and
> > PHY, DDI clocks need to be running when enabling the PHY.
> >
>
> A bspec reference would be useful:
>
> Bspec: NNN
>
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> > 1 file changed, 3 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 8c166f92f8bd..77cd01ecfa80 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1135,8 +1135,6 @@ static void
> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > -
> > /* step 4a: power up all lanes of the DDI used by DSI */
> > gen11_dsi_power_up_lanes(encoder);
> >
> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
> > /* step 4c: configure voltage swing and skew */
> > gen11_dsi_voltage_swing_program_seq(encoder);
> >
> > + gen11_dsi_ungate_clocks(encoder);
> > +
> > /* enable DDI buffer */
> > gen11_dsi_enable_ddi_buffer(encoder);
> >
> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
> > /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> > gen11_dsi_configure_transcoder(encoder, crtc_state);
> >
> > - /* Step 4l: Gate DDI clocks */
> > - if (DISPLAY_VER(dev_priv) == 11)
> > - gen11_dsi_gate_clocks(encoder);
> > + gen11_dsi_gate_clocks(encoder);
>
> So how does this relate to
> 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
As per the latest bspec, this change doesn't seem to be valid anymore.
It is marked with removed tag.
When TGL got added this change came in.
But now with ADL the whole thing is marked as removed.
So, Do you suggest that I submit a revert for this change ?
Thanks,
Vandita
>
> > }
> >
> > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
2021-10-19 10:13 ` Jani Nikula
@ 2021-10-19 11:40 ` Kulkarni, Vandita
2021-10-19 11:45 ` Jani Nikula
0 siblings, 1 reply; 24+ messages in thread
From: Kulkarni, Vandita @ 2021-10-19 11:40 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Deak, Imre, Roper, Matthew D
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, October 19, 2021 3:44 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>
> Subject: Re: [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
>
> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> > Update ADL_P device info to support DSI0, DSI1
> >
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 31 ++++++++++++++++++++++++++++-
> --
> > 1 file changed, 28 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c index 169837de395d..a2dd5a38fdf5
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info =
> > { #define XE_LPD_FEATURES \
> > .abox_mask = GENMASK(1, 0),
> \
> > .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
> \
> > - .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) | \
> > - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> > .dbuf.size = 4096,
> \
> > .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
> \
> > BIT(DBUF_S4),
> \
> > @@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
> > .display.has_psr = 1,
> \
> > .display.ver = 13,
> \
> > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> \
> > + XE_LPD_CURSOR_OFFSETS
> > +
> > +#define ADLP_TRANSCODERS \
> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) | \
> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> \
> > + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> \
> > .pipe_offsets = {
> \
> > [TRANSCODER_A] = PIPE_A_OFFSET,
> \
> > [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> > [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> > [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> \
> > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> \
> > },
> \
> > .trans_offsets = {
> \
> > [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> > [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> > [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> > [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> \
> > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> \
>
> I think you could just add these changes to XE_LPD_FEATURES, and have
> separate .cpu_transcoder_mask initialization for ADLP and DG2.
Okay got it. So its ok to have the pipe_offsets or transcoder offsets added unless we are not defining it in the .cpu_transcoder_mask
Will make this change.
Thanks,
Vandita
>
> Compare GEN12_FEATURES.
>
> BR,
> Jani.
>
> > + }
> \
> > +
> > +#define DG2_TRANSCODERS \
> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) | \
> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> > + .pipe_offsets = {
> \
> > + [TRANSCODER_A] = PIPE_A_OFFSET,
> \
> > + [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> > + [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> > + [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> > },
> \
> > - XE_LPD_CURSOR_OFFSETS
> > + .trans_offsets = {
> \
> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> > + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> > + [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> > + }
> \
> >
> > static const struct intel_device_info adl_p_info = {
> > GEN12_FEATURES,
> > XE_LPD_FEATURES,
> > + ADLP_TRANSCODERS,
> > PLATFORM(INTEL_ALDERLAKE_P),
> > .require_force_probe = 1,
> > .display.has_cdclk_crawl = 1,
> > @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
> > XE_HP_FEATURES,
> > XE_HPM_FEATURES,
> > XE_LPD_FEATURES,
> > + DG2_TRANSCODERS,
> > DGFX_FEATURES,
> > .graphics_rel = 55,
> > .media_rel = 55,
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
2021-10-19 11:32 ` Kulkarni, Vandita
@ 2021-10-19 11:43 ` Kulkarni, Vandita
2021-10-19 11:46 ` Jani Nikula
1 sibling, 0 replies; 24+ messages in thread
From: Kulkarni, Vandita @ 2021-10-19 11:43 UTC (permalink / raw)
To: Kulkarni, Vandita, Nikula, Jani, intel-gfx; +Cc: Deak, Imre, Roper, Matthew D
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Kulkarni, Vandita
> Sent: Tuesday, October 19, 2021 5:03 PM
> To: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before
> enabling the phy
>
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Tuesday, October 19, 2021 3:48 PM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>; Kulkarni, Vandita
> > <vandita.kulkarni@intel.com>
> > Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling
> > the phy
> >
> > On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com>
> wrote:
> > > For the PHY enable/disable signalling to propagate between Dispaly
> > > and PHY, DDI clocks need to be running when enabling the PHY.
> > >
> >
> > A bspec reference would be useful:
> >
> > Bspec: NNN
Bspec: 49187
> >
> > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> > > 1 file changed, 3 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > index 8c166f92f8bd..77cd01ecfa80 100644
> > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > @@ -1135,8 +1135,6 @@ static void
> > > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state) {
> > > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > -
> > > /* step 4a: power up all lanes of the DDI used by DSI */
> > > gen11_dsi_power_up_lanes(encoder);
> > >
> > > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> > intel_encoder *encoder,
> > > /* step 4c: configure voltage swing and skew */
> > > gen11_dsi_voltage_swing_program_seq(encoder);
> > >
> > > + gen11_dsi_ungate_clocks(encoder);
> > > +
> > > /* enable DDI buffer */
> > > gen11_dsi_enable_ddi_buffer(encoder);
> > >
> > > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> > intel_encoder *encoder,
> > > /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> > > gen11_dsi_configure_transcoder(encoder, crtc_state);
> > >
> > > - /* Step 4l: Gate DDI clocks */
> > > - if (DISPLAY_VER(dev_priv) == 11)
> > > - gen11_dsi_gate_clocks(encoder);
> > > + gen11_dsi_gate_clocks(encoder);
> >
> > So how does this relate to
> > 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll
> > mapping")
>
> As per the latest bspec, this change doesn't seem to be valid anymore.
> It is marked with removed tag.
> When TGL got added this change came in.
>
> But now with ADL the whole thing is marked as removed.
And the gating is now added after enabling DDI Buffer
> So, Do you suggest that I submit a revert for this change ?
>
> Thanks,
> Vandita
> >
> > > }
> > >
> > > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
2021-10-19 11:40 ` Kulkarni, Vandita
@ 2021-10-19 11:45 ` Jani Nikula
0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2021-10-19 11:45 UTC (permalink / raw)
To: Kulkarni, Vandita, intel-gfx; +Cc: Deak, Imre, Roper, Matthew D
On Tue, 19 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, October 19, 2021 3:44 PM
>> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>
>> Subject: Re: [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
>>
>> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>> > Update ADL_P device info to support DSI0, DSI1
>> >
>> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_pci.c | 31 ++++++++++++++++++++++++++++-
>> --
>> > 1 file changed, 28 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> > b/drivers/gpu/drm/i915/i915_pci.c index 169837de395d..a2dd5a38fdf5
>> > 100644
>> > --- a/drivers/gpu/drm/i915/i915_pci.c
>> > +++ b/drivers/gpu/drm/i915/i915_pci.c
>> > @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info =
>> > { #define XE_LPD_FEATURES \
>> > .abox_mask = GENMASK(1, 0),
>> \
>> > .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
>> \
>> > - .cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) | \
>> > - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> \
>> > .dbuf.size = 4096,
>> \
>> > .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
>> \
>> > BIT(DBUF_S4),
>> \
>> > @@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
>> > .display.has_psr = 1,
>> \
>> > .display.ver = 13,
>> \
>> > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>> \
>> > + XE_LPD_CURSOR_OFFSETS
>> > +
>> > +#define ADLP_TRANSCODERS \
>> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) | \
>> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
>> \
>> > + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
>> \
>> > .pipe_offsets = {
>> \
>> > [TRANSCODER_A] = PIPE_A_OFFSET,
>> \
>> > [TRANSCODER_B] = PIPE_B_OFFSET,
>> \
>> > [TRANSCODER_C] = PIPE_C_OFFSET,
>> \
>> > [TRANSCODER_D] = PIPE_D_OFFSET,
>> \
>> > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
>> \
>> > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
>> \
>> > },
>> \
>> > .trans_offsets = {
>> \
>> > [TRANSCODER_A] = TRANSCODER_A_OFFSET,
>> \
>> > [TRANSCODER_B] = TRANSCODER_B_OFFSET,
>> \
>> > [TRANSCODER_C] = TRANSCODER_C_OFFSET,
>> \
>> > [TRANSCODER_D] = TRANSCODER_D_OFFSET,
>> \
>> > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
>> \
>> > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
>> \
>>
>> I think you could just add these changes to XE_LPD_FEATURES, and have
>> separate .cpu_transcoder_mask initialization for ADLP and DG2.
>
> Okay got it. So its ok to have the pipe_offsets or transcoder offsets added unless we are not defining it in the .cpu_transcoder_mask
> Will make this change.
Yeah, the *_offsets are only used if referenced, and having them should
not make a difference. It's the .cpu_transcoder_mask and .pipe_mask that
matter.
BR,
Hani.
>
> Thanks,
> Vandita
>>
>> Compare GEN12_FEATURES.
>>
>> BR,
>> Jani.
>>
>> > + }
>> \
>> > +
>> > +#define DG2_TRANSCODERS \
>> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) | \
>> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> \
>> > + .pipe_offsets = {
>> \
>> > + [TRANSCODER_A] = PIPE_A_OFFSET,
>> \
>> > + [TRANSCODER_B] = PIPE_B_OFFSET,
>> \
>> > + [TRANSCODER_C] = PIPE_C_OFFSET,
>> \
>> > + [TRANSCODER_D] = PIPE_D_OFFSET,
>> \
>> > },
>> \
>> > - XE_LPD_CURSOR_OFFSETS
>> > + .trans_offsets = {
>> \
>> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
>> \
>> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
>> \
>> > + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
>> \
>> > + [TRANSCODER_D] = TRANSCODER_D_OFFSET,
>> \
>> > + }
>> \
>> >
>> > static const struct intel_device_info adl_p_info = {
>> > GEN12_FEATURES,
>> > XE_LPD_FEATURES,
>> > + ADLP_TRANSCODERS,
>> > PLATFORM(INTEL_ALDERLAKE_P),
>> > .require_force_probe = 1,
>> > .display.has_cdclk_crawl = 1,
>> > @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
>> > XE_HP_FEATURES,
>> > XE_HPM_FEATURES,
>> > XE_LPD_FEATURES,
>> > + DG2_TRANSCODERS,
>> > DGFX_FEATURES,
>> > .graphics_rel = 55,
>> > .media_rel = 55,
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
2021-10-19 11:32 ` Kulkarni, Vandita
2021-10-19 11:43 ` Kulkarni, Vandita
@ 2021-10-19 11:46 ` Jani Nikula
2021-10-19 11:48 ` Kulkarni, Vandita
1 sibling, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-10-19 11:46 UTC (permalink / raw)
To: Kulkarni, Vandita, intel-gfx; +Cc: Deak, Imre, Roper, Matthew D
On Tue, 19 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, October 19, 2021 3:48 PM
>> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>
>> Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>>
>> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>> > For the PHY enable/disable signalling to propagate between Dispaly and
>> > PHY, DDI clocks need to be running when enabling the PHY.
>> >
>>
>> A bspec reference would be useful:
>>
>> Bspec: NNN
>>
>> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
>> > 1 file changed, 3 insertions(+), 5 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > index 8c166f92f8bd..77cd01ecfa80 100644
>> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > @@ -1135,8 +1135,6 @@ static void
>> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> > const struct intel_crtc_state *crtc_state)
>> > {
>> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > -
>> > /* step 4a: power up all lanes of the DDI used by DSI */
>> > gen11_dsi_power_up_lanes(encoder);
>> >
>> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>> > /* step 4c: configure voltage swing and skew */
>> > gen11_dsi_voltage_swing_program_seq(encoder);
>> >
>> > + gen11_dsi_ungate_clocks(encoder);
>> > +
>> > /* enable DDI buffer */
>> > gen11_dsi_enable_ddi_buffer(encoder);
>> >
>> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>> > /* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> > gen11_dsi_configure_transcoder(encoder, crtc_state);
>> >
>> > - /* Step 4l: Gate DDI clocks */
>> > - if (DISPLAY_VER(dev_priv) == 11)
>> > - gen11_dsi_gate_clocks(encoder);
>> > + gen11_dsi_gate_clocks(encoder);
>>
>> So how does this relate to
>> 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
>
> As per the latest bspec, this change doesn't seem to be valid anymore.
> It is marked with removed tag.
> When TGL got added this change came in.
>
> But now with ADL the whole thing is marked as removed.
> So, Do you suggest that I submit a revert for this change ?
No, just an explanation and maybe that commit reference in the commit
message.
BR,
Jani.
>
> Thanks,
> Vandita
>>
>> > }
>> >
>> > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
2021-10-19 11:46 ` Jani Nikula
@ 2021-10-19 11:48 ` Kulkarni, Vandita
0 siblings, 0 replies; 24+ messages in thread
From: Kulkarni, Vandita @ 2021-10-19 11:48 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Deak, Imre, Roper, Matthew D
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, October 19, 2021 5:16 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: RE: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>
> On Tue, 19 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Tuesday, October 19, 2021 3:48 PM
> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> >> <matthew.d.roper@intel.com>; Kulkarni, Vandita
> >> <vandita.kulkarni@intel.com>
> >> Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling
> >> the phy
> >>
> >> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com>
> wrote:
> >> > For the PHY enable/disable signalling to propagate between Dispaly
> >> > and PHY, DDI clocks need to be running when enabling the PHY.
> >> >
> >>
> >> A bspec reference would be useful:
> >>
> >> Bspec: NNN
> >>
> >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> >> > 1 file changed, 3 insertions(+), 5 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > index 8c166f92f8bd..77cd01ecfa80 100644
> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > @@ -1135,8 +1135,6 @@ static void
> >> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> >> > const struct intel_crtc_state *crtc_state) {
> >> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >> > -
> >> > /* step 4a: power up all lanes of the DDI used by DSI */
> >> > gen11_dsi_power_up_lanes(encoder);
> >> >
> >> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> >> intel_encoder *encoder,
> >> > /* step 4c: configure voltage swing and skew */
> >> > gen11_dsi_voltage_swing_program_seq(encoder);
> >> >
> >> > + gen11_dsi_ungate_clocks(encoder);
> >> > +
> >> > /* enable DDI buffer */
> >> > gen11_dsi_enable_ddi_buffer(encoder);
> >> >
> >> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> >> intel_encoder *encoder,
> >> > /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> >> > gen11_dsi_configure_transcoder(encoder, crtc_state);
> >> >
> >> > - /* Step 4l: Gate DDI clocks */
> >> > - if (DISPLAY_VER(dev_priv) == 11)
> >> > - gen11_dsi_gate_clocks(encoder);
> >> > + gen11_dsi_gate_clocks(encoder);
> >>
> >> So how does this relate to
> >> 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll
> >> mapping")
> >
> > As per the latest bspec, this change doesn't seem to be valid anymore.
> > It is marked with removed tag.
> > When TGL got added this change came in.
> >
> > But now with ADL the whole thing is marked as removed.
> > So, Do you suggest that I submit a revert for this change ?
>
> No, just an explanation and maybe that commit reference in the commit
> message.
Okay, will do that.
Thanks,
Vandita
>
> BR,
> Jani.
>
> >
> > Thanks,
> > Vandita
> >>
> >> > }
> >> >
> >> > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
2021-10-19 10:24 ` Jani Nikula
@ 2021-10-19 12:08 ` Imre Deak
0 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-10-19 12:08 UTC (permalink / raw)
To: Jani Nikula; +Cc: Vandita Kulkarni, intel-gfx, matthew.d.roper
On Tue, Oct 19, 2021 at 01:24:51PM +0300, Jani Nikula wrote:
> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> > MIPI DSI transcoder cannot be in video mode to support any of the
> > display C states.
>
> Imre, could you review this one please?
>
> The added confusion is that POWER_DOMAIN_TRANSCODER_DSI_A and
> POWER_DOMAIN_TRANSCODER_DSI_C are never used anywhere and
> POWER_DOMAIN_TRANSCODER() does not take DSI transcoders into account.
<tl;dr>
You mean they are not listed in the power_domain->power_well mappings.
Those power domains don't use any power wells above PW#1. PW#0/1 is
handled "automatically" by DMC, so we don't have to toggle the power for
those manually. However they still need a runtime PM reference, since
whatever HW domain you want to use, the PCI device must be in the runtime
resumed state. This is ensured by the always-on power well, which every
domain has a dependency on.
<tl;dr>
The transcoder power domains are acquired in get_crtc_power_domains(),
doesn't the DSI encoder using the DSI_A/C transcoders?
Yes, POWER_DOMAIN_TRANSCODER is now broken wrt. DSI due to
POWER_DOMAIN_TRANSCODER_VDSC_PW2. So that would need to be moved after
the TRANSCODER_DSI_C. And the POWER_DOMAIN_TRANSCODER macro could be
also simplified afaics.
Otherwise this patch looks ok to me, just the bspec links would be good
to have here too.
>
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 709569211c85..8406db5e573e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_MODESET) | \
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > + BIT_ULL(POWER_DOMAIN_INIT)) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DSI)
>
> Everywhere else POWER_DOMAIN_INIT is last in the list.
>
> BR,
> Jani.
>
> >
> > #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> > #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2021-10-19 12:09 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
2021-10-18 6:52 ` [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Vandita Kulkarni
2021-10-19 10:05 ` Jani Nikula
2021-10-19 10:15 ` Ville Syrjälä
2021-10-19 10:28 ` Jani Nikula
2021-10-19 10:41 ` Ville Syrjälä
2021-10-19 10:50 ` Ville Syrjälä
2021-10-19 11:27 ` Kulkarni, Vandita
2021-10-18 6:52 ` [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support Vandita Kulkarni
2021-10-19 10:13 ` Jani Nikula
2021-10-19 11:40 ` Kulkarni, Vandita
2021-10-19 11:45 ` Jani Nikula
2021-10-18 6:52 ` [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode Vandita Kulkarni
2021-10-19 10:24 ` Jani Nikula
2021-10-19 12:08 ` Imre Deak
2021-10-18 6:52 ` [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy Vandita Kulkarni
2021-10-19 10:18 ` Jani Nikula
2021-10-19 11:32 ` Kulkarni, Vandita
2021-10-19 11:43 ` Kulkarni, Vandita
2021-10-19 11:46 ` Jani Nikula
2021-10-19 11:48 ` Kulkarni, Vandita
2021-10-18 7:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP Patchwork
2021-10-18 7:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-18 9:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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