From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis <alistair.francis@wdc.com>, kupokupokupopo@gmail.com, palmer@dabbelt.com, Bin Meng <bmeng.cn@gmail.com> Subject: [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on Date: Mon, 25 Oct 2021 20:36:09 +0300 [thread overview] Message-ID: <20211025173609.2724490-9-space.monkey.delivers@gmail.com> (raw) In-Reply-To: <20211025173609.2724490-1-space.monkey.delivers@gmail.com> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16fac64806..7d53125dbc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,6 +562,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_j) { + ext |= RVJ; + } set_misa(env, env->misa_mxl, ext); } @@ -637,6 +640,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on Date: Mon, 25 Oct 2021 20:36:09 +0300 [thread overview] Message-ID: <20211025173609.2724490-9-space.monkey.delivers@gmail.com> (raw) In-Reply-To: <20211025173609.2724490-1-space.monkey.delivers@gmail.com> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16fac64806..7d53125dbc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,6 +562,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_j) { + ext |= RVJ; + } set_misa(env, env->misa_mxl, ext); } @@ -637,6 +640,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), -- 2.30.2
next prev parent reply other threads:[~2021-10-25 17:52 UTC|newest] Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-25 17:36 [PATCH v17 0/8] RISC-V Pointer Masking implementation Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 17:36 ` [PATCH v17 1/8] target/riscv: Add J-extension into RISC-V Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 17:36 ` [PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 17:36 ` [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 18:46 ` Richard Henderson 2021-10-25 18:46 ` Richard Henderson 2021-10-25 17:36 ` [PATCH v17 4/8] target/riscv: Add J extension state description Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 17:36 ` [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 22:32 ` Alistair Francis 2021-10-25 17:36 ` [PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 17:36 ` [PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo 2021-10-25 17:36 ` Alexey Baturo [this message] 2021-10-25 17:36 ` [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on Alexey Baturo
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