From: Richard Henderson <richard.henderson@linaro.org>
To: Alexey Baturo <baturo.alexey@gmail.com>
Cc: qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com,
kupokupokupopo@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
Date: Mon, 25 Oct 2021 11:46:55 -0700 [thread overview]
Message-ID: <9143ada5-eaf5-c790-ba60-7572809bf732@linaro.org> (raw)
In-Reply-To: <20211025173609.2724490-4-space.monkey.delivers@gmail.com>
On 10/25/21 10:36 AM, Alexey Baturo wrote:
> + /* User Pointer Masking */
> + [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
> + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
> + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
> + /* Machine Pointer Masking */
> + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
> + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
> + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
> + /* Supervisor Pointer Masking */
> + [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
> + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
> + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
Surely the S-mode and U-mode csrs surely also depend on RVS and RVU respectively?
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Alexey Baturo <baturo.alexey@gmail.com>
Cc: space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com,
palmer@dabbelt.com, Alistair.Francis@wdc.com,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
Date: Mon, 25 Oct 2021 11:46:55 -0700 [thread overview]
Message-ID: <9143ada5-eaf5-c790-ba60-7572809bf732@linaro.org> (raw)
In-Reply-To: <20211025173609.2724490-4-space.monkey.delivers@gmail.com>
On 10/25/21 10:36 AM, Alexey Baturo wrote:
> + /* User Pointer Masking */
> + [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
> + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
> + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
> + /* Machine Pointer Masking */
> + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
> + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
> + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
> + /* Supervisor Pointer Masking */
> + [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
> + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
> + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
Surely the S-mode and U-mode csrs surely also depend on RVS and RVU respectively?
r~
next prev parent reply other threads:[~2021-10-25 18:49 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 17:36 [PATCH v17 0/8] RISC-V Pointer Masking implementation Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 1/8] target/riscv: Add J-extension into RISC-V Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 18:46 ` Richard Henderson [this message]
2021-10-25 18:46 ` Richard Henderson
2021-10-25 17:36 ` [PATCH v17 4/8] target/riscv: Add J extension state description Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 22:32 ` Alistair Francis
2021-10-25 17:36 ` [PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo
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