From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
Date: Fri, 29 Oct 2021 16:58:27 +0800 [thread overview]
Message-ID: <20211029085922.255197-23-frank.chang@sifive.com> (raw)
In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index df45c1620c1..3da4f3b1e62 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -374,10 +374,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
Date: Fri, 29 Oct 2021 16:58:27 +0800 [thread overview]
Message-ID: <20211029085922.255197-23-frank.chang@sifive.com> (raw)
In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index df45c1620c1..3da4f3b1e62 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -374,10 +374,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.25.1
next prev parent reply other threads:[~2021-10-29 9:39 UTC|newest]
Thread overview: 168+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 8:58 [PATCH v9 00/76] support vector extension v1.0 frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-10-29 8:58 ` frank.chang
2021-11-01 6:45 ` Bin Meng
2021-11-01 6:45 ` Bin Meng
2021-10-29 8:58 ` [PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 19:46 ` Richard Henderson
2021-10-29 19:46 ` Richard Henderson
2021-10-29 8:58 ` [PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 15/76] target/riscv: rvv-1.0: update check functions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 16/76] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 18/76] target/riscv: rvv-1.0: remove amo operations instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 19/76] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 20/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 21/76] target/riscv: rvv-1.0: index " frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` frank.chang [this message]
2021-10-29 8:58 ` [PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-29 8:58 ` [PATCH v9 23/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 24/76] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 27/76] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 29/76] target/riscv: rvv-1.0: count population in mask instruction frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 32/76] target/riscv: rvv-1.0: iota instruction frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 34/76] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 35/76] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 37/76] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 39/76] target/riscv: rvv-1.0: whole register " frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 40/76] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 47/76] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 51/76] target/riscv: rvv-1.0: floating-point " frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 53/76] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:58 ` [PATCH v9 54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-10-29 8:58 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 55/76] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 59/76] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 63/76] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-10-29 8:59 ` frank.chang
2021-11-15 23:54 ` Alistair Francis
2021-11-15 23:54 ` Alistair Francis
2021-10-29 8:59 ` [PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-10-29 8:59 ` frank.chang
2021-11-15 23:55 ` Alistair Francis
2021-11-15 23:55 ` Alistair Francis
2021-10-29 8:59 ` [PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-10-29 8:59 ` frank.chang
2021-11-16 0:12 ` Alistair Francis
2021-11-16 0:12 ` Alistair Francis
2021-10-29 8:59 ` [PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 70/76] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 72/76] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-10-29 8:59 ` frank.chang
2021-11-15 23:59 ` Alistair Francis
2021-11-15 23:59 ` Alistair Francis
2021-10-29 8:59 ` [PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
2021-10-29 8:59 ` frank.chang
2021-11-16 0:00 ` Alistair Francis
2021-11-16 0:00 ` Alistair Francis
2021-10-29 8:59 ` [PATCH v9 75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang
2021-10-29 8:59 ` frank.chang
2021-10-29 8:59 ` [PATCH v9 76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang
2021-10-29 8:59 ` frank.chang
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