From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Date: Fri, 29 Oct 2021 16:59:14 +0800 [thread overview] Message-ID: <20211029085922.255197-70-frank.chang@sifive.com> (raw) In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 183 ++++++++++++++++++++++++ 4 files changed, 189 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a717a87a0e0..bdf06dfb24d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -841,6 +841,10 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32) + DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c4fdc76a269..6e5f288943a 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -560,6 +560,7 @@ vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm +vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 53c8573f117..8fe718610a9 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2407,6 +2407,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ } GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point MIN/MAX Instructions */ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 22848d6b683..d5f3229bcb4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" +#include "qemu/bitops.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -3404,6 +3405,188 @@ GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2) GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4) GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8) +/* + * Vector Floating-Point Reciprocal Square-Root Estimate Instruction + * + * Adapted from riscv-v-spec recip.c: + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c + */ +static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size) +{ + uint64_t sign = extract64(f, frac_size + exp_size, 1); + uint64_t exp = extract64(f, frac_size, exp_size); + uint64_t frac = extract64(f, 0, frac_size); + + const uint8_t lookup_table[] = { + 52, 51, 50, 48, 47, 46, 44, 43, + 42, 41, 40, 39, 38, 36, 35, 34, + 33, 32, 31, 30, 30, 29, 28, 27, + 26, 25, 24, 23, 23, 22, 21, 20, + 19, 19, 18, 17, 16, 16, 15, 14, + 14, 13, 12, 12, 11, 10, 10, 9, + 9, 8, 7, 7, 6, 6, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0, + 127, 125, 123, 121, 119, 118, 116, 114, + 113, 111, 109, 108, 106, 105, 103, 102, + 100, 99, 97, 96, 95, 93, 92, 91, + 90, 88, 87, 86, 85, 84, 83, 82, + 80, 79, 78, 77, 76, 75, 74, 73, + 72, 71, 70, 70, 69, 68, 67, 66, + 65, 64, 63, 63, 62, 61, 60, 59, + 59, 58, 57, 56, 56, 55, 54, 53 + }; + const int precision = 7; + + if (exp == 0 && frac != 0) { /* subnormal */ + /* Normalize the subnormal. */ + while (extract64(frac, frac_size - 1, 1) == 0) { + exp--; + frac <<= 1; + } + + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size); + } + + int idx = ((exp & 1) << (precision - 1)) | + (frac >> (frac_size - precision + 1)); + uint64_t out_frac = (uint64_t)(lookup_table[idx]) << + (frac_size - precision); + uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2; + + uint64_t val = 0; + val = deposit64(val, 0, frac_size, out_frac); + val = deposit64(val, frac_size, exp_size, out_exp); + val = deposit64(val, frac_size + exp_size, 1, sign); + return val; +} + +static float16 frsqrt7_h(float16 f, float_status *s) +{ + int exp_size = 5, frac_size = 10; + bool sign = float16_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float16_is_signaling_nan(f, s) || + (float16_is_infinity(f) && sign) || + (float16_is_normal(f) && sign) || + (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float16_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float16_is_quiet_nan(f, s)) { + return float16_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float16_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float16_set_sign(float16_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float16_is_infinity(f) && !sign) { + return float16_set_sign(float16_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float16(val); +} + +static float32 frsqrt7_s(float32 f, float_status *s) +{ + int exp_size = 8, frac_size = 23; + bool sign = float32_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float32_is_signaling_nan(f, s) || + (float32_is_infinity(f) && sign) || + (float32_is_normal(f) && sign) || + (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float32_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float32_is_quiet_nan(f, s)) { + return float32_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float32_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float32_set_sign(float32_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float32_is_infinity(f) && !sign) { + return float32_set_sign(float32_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float32(val); +} + +static float64 frsqrt7_d(float64 f, float_status *s) +{ + int exp_size = 11, frac_size = 52; + bool sign = float64_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float64_is_signaling_nan(f, s) || + (float64_is_infinity(f) && sign) || + (float64_is_normal(f) && sign) || + (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float64_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float64_is_quiet_nan(f, s)) { + return float64_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float64_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float64_set_sign(float64_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float64_is_infinity(f) && !sign) { + return float64_set_sign(float64_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float64(val); +} + +RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h) +RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s) +RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d) +GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2) +GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4) +GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8) + /* Vector Floating-Point MIN/MAX Instructions */ RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number) RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Date: Fri, 29 Oct 2021 16:59:14 +0800 [thread overview] Message-ID: <20211029085922.255197-70-frank.chang@sifive.com> (raw) In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 183 ++++++++++++++++++++++++ 4 files changed, 189 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a717a87a0e0..bdf06dfb24d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -841,6 +841,10 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32) + DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c4fdc76a269..6e5f288943a 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -560,6 +560,7 @@ vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm +vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 53c8573f117..8fe718610a9 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2407,6 +2407,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ } GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point MIN/MAX Instructions */ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 22848d6b683..d5f3229bcb4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" +#include "qemu/bitops.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -3404,6 +3405,188 @@ GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2) GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4) GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8) +/* + * Vector Floating-Point Reciprocal Square-Root Estimate Instruction + * + * Adapted from riscv-v-spec recip.c: + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c + */ +static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size) +{ + uint64_t sign = extract64(f, frac_size + exp_size, 1); + uint64_t exp = extract64(f, frac_size, exp_size); + uint64_t frac = extract64(f, 0, frac_size); + + const uint8_t lookup_table[] = { + 52, 51, 50, 48, 47, 46, 44, 43, + 42, 41, 40, 39, 38, 36, 35, 34, + 33, 32, 31, 30, 30, 29, 28, 27, + 26, 25, 24, 23, 23, 22, 21, 20, + 19, 19, 18, 17, 16, 16, 15, 14, + 14, 13, 12, 12, 11, 10, 10, 9, + 9, 8, 7, 7, 6, 6, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0, + 127, 125, 123, 121, 119, 118, 116, 114, + 113, 111, 109, 108, 106, 105, 103, 102, + 100, 99, 97, 96, 95, 93, 92, 91, + 90, 88, 87, 86, 85, 84, 83, 82, + 80, 79, 78, 77, 76, 75, 74, 73, + 72, 71, 70, 70, 69, 68, 67, 66, + 65, 64, 63, 63, 62, 61, 60, 59, + 59, 58, 57, 56, 56, 55, 54, 53 + }; + const int precision = 7; + + if (exp == 0 && frac != 0) { /* subnormal */ + /* Normalize the subnormal. */ + while (extract64(frac, frac_size - 1, 1) == 0) { + exp--; + frac <<= 1; + } + + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size); + } + + int idx = ((exp & 1) << (precision - 1)) | + (frac >> (frac_size - precision + 1)); + uint64_t out_frac = (uint64_t)(lookup_table[idx]) << + (frac_size - precision); + uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2; + + uint64_t val = 0; + val = deposit64(val, 0, frac_size, out_frac); + val = deposit64(val, frac_size, exp_size, out_exp); + val = deposit64(val, frac_size + exp_size, 1, sign); + return val; +} + +static float16 frsqrt7_h(float16 f, float_status *s) +{ + int exp_size = 5, frac_size = 10; + bool sign = float16_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float16_is_signaling_nan(f, s) || + (float16_is_infinity(f) && sign) || + (float16_is_normal(f) && sign) || + (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float16_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float16_is_quiet_nan(f, s)) { + return float16_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float16_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float16_set_sign(float16_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float16_is_infinity(f) && !sign) { + return float16_set_sign(float16_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float16(val); +} + +static float32 frsqrt7_s(float32 f, float_status *s) +{ + int exp_size = 8, frac_size = 23; + bool sign = float32_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float32_is_signaling_nan(f, s) || + (float32_is_infinity(f) && sign) || + (float32_is_normal(f) && sign) || + (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float32_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float32_is_quiet_nan(f, s)) { + return float32_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float32_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float32_set_sign(float32_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float32_is_infinity(f) && !sign) { + return float32_set_sign(float32_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float32(val); +} + +static float64 frsqrt7_d(float64 f, float_status *s) +{ + int exp_size = 11, frac_size = 52; + bool sign = float64_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float64_is_signaling_nan(f, s) || + (float64_is_infinity(f) && sign) || + (float64_is_normal(f) && sign) || + (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float64_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float64_is_quiet_nan(f, s)) { + return float64_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float64_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float64_set_sign(float64_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float64_is_infinity(f) && !sign) { + return float64_set_sign(float64_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float64(val); +} + +RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h) +RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s) +RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d) +GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2) +GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4) +GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8) + /* Vector Floating-Point MIN/MAX Instructions */ RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number) RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number) -- 2.25.1
next prev parent reply other threads:[~2021-10-29 10:03 UTC|newest] Thread overview: 168+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-29 8:58 [PATCH v9 00/76] support vector extension v1.0 frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang 2021-10-29 8:58 ` frank.chang 2021-11-01 6:45 ` Bin Meng 2021-11-01 6:45 ` Bin Meng 2021-10-29 8:58 ` [PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 19:46 ` Richard Henderson 2021-10-29 19:46 ` Richard Henderson 2021-10-29 8:58 ` [PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 15/76] target/riscv: rvv-1.0: update check functions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 16/76] target/riscv: introduce more imm value modes in translator functions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 18/76] target/riscv: rvv-1.0: remove amo operations instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 19/76] target/riscv: rvv-1.0: configure instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 20/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 21/76] target/riscv: rvv-1.0: index " frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 23/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 24/76] target/riscv: rvv-1.0: load/store whole register instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 27/76] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 29/76] target/riscv: rvv-1.0: count population in mask instruction frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 32/76] target/riscv: rvv-1.0: iota instruction frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 34/76] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 35/76] target/riscv: rvv-1.0: register gather instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 37/76] target/riscv: rvv-1.0: floating-point move instruction frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 39/76] target/riscv: rvv-1.0: whole register " frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 40/76] target/riscv: rvv-1.0: integer extension instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 47/76] target/riscv: rvv-1.0: integer comparison instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 51/76] target/riscv: rvv-1.0: floating-point " frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 53/76] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:58 ` [PATCH v9 54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang 2021-10-29 8:58 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 55/76] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 59/76] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 63/76] target/riscv: add "set round to odd" rounding mode helper function frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR frank.chang 2021-10-29 8:59 ` frank.chang 2021-11-15 23:54 ` Alistair Francis 2021-11-15 23:54 ` Alistair Francis 2021-10-29 8:59 ` [PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang 2021-10-29 8:59 ` frank.chang 2021-11-15 23:55 ` Alistair Francis 2021-11-15 23:55 ` Alistair Francis 2021-10-29 8:59 ` [PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang 2021-10-29 8:59 ` frank.chang 2021-11-16 0:12 ` Alistair Francis 2021-11-16 0:12 ` Alistair Francis 2021-10-29 8:59 ` frank.chang [this message] 2021-10-29 8:59 ` [PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang 2021-10-29 8:59 ` [PATCH v9 70/76] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 72/76] target/riscv: rvv-1.0: add vsetivli instruction frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang 2021-10-29 8:59 ` frank.chang 2021-11-15 23:59 ` Alistair Francis 2021-11-15 23:59 ` Alistair Francis 2021-10-29 8:59 ` [PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang 2021-10-29 8:59 ` frank.chang 2021-11-16 0:00 ` Alistair Francis 2021-11-16 0:00 ` Alistair Francis 2021-10-29 8:59 ` [PATCH v9 75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang 2021-10-29 8:59 ` frank.chang 2021-10-29 8:59 ` [PATCH v9 76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang 2021-10-29 8:59 ` frank.chang
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