* [PATCH v2 01/34] target/ppc: introduce do_ea_calc
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-29 20:23 ` [PATCH v2 02/34] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
` (33 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Fernando Eckhardt Valle, lucas.castro, richard.henderson, groug,
luis.pires, Matheus Ferst, david
From: Fernando Eckhardt Valle <phervalle@gmail.com>
The do_ea_calc function will calculate the effective address(EA)
according to PowerIsa 3.1. With that, it was replaced part of
do_ldst() that calculates the EA by this new function.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle (pherde) <phervalle@gmail.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Allocate and return ea
- inline attribute removed
---
target/ppc/translate.c | 14 ++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 10 +---------
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 62414adb75..cc809341e4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3197,6 +3197,20 @@ static inline void gen_align_no_le(DisasContext *ctx)
(ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
}
+static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ)
+{
+ TCGv ea = tcg_temp_new();
+ if (ra) {
+ tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
+ } else {
+ tcg_gen_mov_tl(ea, displ);
+ }
+ if (NARROW_MODE(ctx)) {
+ tcg_gen_ext32u_tl(ea, ea);
+ }
+ return ea;
+}
+
/*** Integer load ***/
#define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
#define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 2e2518ee15..caef5d89cd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -51,15 +51,7 @@ static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
}
gen_set_access_type(ctx, ACCESS_INT);
- ea = tcg_temp_new();
- if (ra) {
- tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
- } else {
- tcg_gen_mov_tl(ea, displ);
- }
- if (NARROW_MODE(ctx)) {
- tcg_gen_ext32u_tl(ea, ea);
- }
+ ea = do_ea_calc(ctx, ra, displ);
mop ^= ctx->default_tcg_memop_mask;
if (store) {
tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 02/34] target/ppc: move resolve_PLS_D to translate.c
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
2021-10-29 20:23 ` [PATCH v2 01/34] target/ppc: introduce do_ea_calc matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-29 20:23 ` [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
` (32 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Fernando Eckhardt Valle, lucas.castro, richard.henderson, groug,
luis.pires, Matheus Ferst, david
From: Fernando Eckhardt Valle <phervalle@gmail.com>
Move resolve_PLS_D from fixedpoint-impl.c.inc to translate.c
because this way the function can be used not only by fixed
point instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle <phervalle@gmail.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 19 +++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 19 -------------------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index cc809341e4..4828456d34 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7523,6 +7523,25 @@ static int times_4(DisasContext *ctx, int x)
#include "decode-insn64.c.inc"
#include "power8-pmu-regs.c.inc"
+/*
+ * Incorporate CIA into the constant when R=1.
+ * Validate that when R=1, RA=0.
+ */
+static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
+{
+ d->rt = a->rt;
+ d->ra = a->ra;
+ d->si = a->si;
+ if (a->r) {
+ if (unlikely(a->ra != 0)) {
+ gen_invalid(ctx);
+ return false;
+ }
+ d->si += ctx->cia;
+ }
+ return true;
+}
+
#include "translate/fixedpoint-impl.c.inc"
#include "translate/fp-impl.c.inc"
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index caef5d89cd..812b7ddd0a 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -17,25 +17,6 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-/*
- * Incorporate CIA into the constant when R=1.
- * Validate that when R=1, RA=0.
- */
-static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
-{
- d->rt = a->rt;
- d->ra = a->ra;
- d->si = a->si;
- if (a->r) {
- if (unlikely(a->ra != 0)) {
- gen_invalid(ctx);
- return false;
- }
- d->si += ctx->cia;
- }
- return true;
-}
-
/*
* Fixed-Point Load/Store Instructions
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
2021-10-29 20:23 ` [PATCH v2 01/34] target/ppc: introduce do_ea_calc matheus.ferst
2021-10-29 20:23 ` [PATCH v2 02/34] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-11-09 13:43 ` Mark Cave-Ayland
2021-10-29 20:23 ` [PATCH v2 04/34] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
` (31 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Fernando Eckhardt Valle, lucas.castro, richard.henderson, groug,
luis.pires, Fernando Eckhardt Valle, Matheus Ferst, david
From: Fernando Eckhardt Valle <phervalle@gmail.com>
Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
stfdux) from legacy system to decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- if instead of top-level ternary operator
---
target/ppc/insn32.decode | 24 +++
target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
target/ppc/translate/fp-ops.c.inc | 29 ----
3 files changed, 95 insertions(+), 205 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 6aec1c0728..3837b799c8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -193,6 +193,30 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
+### Float-Point Load Instructions
+
+LFS 110000 ..... ..... ................ @D
+LFSU 110001 ..... ..... ................ @D
+LFSX 011111 ..... ..... ..... 1000010111 - @X
+LFSUX 011111 ..... ..... ..... 1000110111 - @X
+
+LFD 110010 ..... ..... ................ @D
+LFDU 110011 ..... ..... ................ @D
+LFDX 011111 ..... ..... ..... 1001010111 - @X
+LFDUX 011111 ..... ..... ..... 1001110111 - @X
+
+### Float-Point Store Instructions
+
+STFS 110100 ..... ...... ............... @D
+STFSU 110101 ..... ...... ............... @D
+STFSX 011111 ..... ...... .... 1010010111 - @X
+STFSUX 011111 ..... ...... .... 1010110111 - @X
+
+STFD 110110 ..... ...... ............... @D
+STFDU 110111 ..... ...... ............... @D
+STFDX 011111 ..... ...... .... 1011010111 - @X
+STFDUX 011111 ..... ...... .... 1011110111 - @X
+
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 9f7868ee28..57a799db1c 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -854,99 +854,6 @@ static void gen_mtfsfi(DisasContext *ctx)
gen_helper_float_check_status(cpu_env);
}
-/*** Floating-point load ***/
-#define GEN_LDF(name, ldop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDUF(name, ldop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDUXF(name, ldop, opc, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDXF(name, ldop, opc2, opc3, type) \
-static void glue(gen_, name##x)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDFS(name, ldop, op, type) \
-GEN_LDF(name, ldop, op | 0x20, type); \
-GEN_LDUF(name, ldop, op | 0x21, type); \
-GEN_LDUXF(name, ldop, op | 0x01, type); \
-GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-
static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
{
TCGv_i32 tmp = tcg_temp_new_i32();
@@ -955,11 +862,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
tcg_temp_free_i32(tmp);
}
- /* lfd lfdu lfdux lfdx */
-GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
- /* lfs lfsu lfsux lfsx */
-GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
-
/* lfdepx (external PID lfdx) */
static void gen_lfdepx(DisasContext *ctx)
{
@@ -1089,73 +991,6 @@ static void gen_lfiwzx(DisasContext *ctx)
tcg_temp_free(EA);
tcg_temp_free_i64(t0);
}
-/*** Floating-point store ***/
-#define GEN_STF(name, stop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STUF(name, stop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STUXF(name, stop, opc, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_reg_index(ctx, EA); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
#define GEN_STXF(name, stop, opc2, opc3, type) \
static void glue(gen_, name##x)(DisasContext *ctx) \
@@ -1176,12 +1011,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
tcg_temp_free_i64(t0); \
}
-#define GEN_STFS(name, stop, op, type) \
-GEN_STF(name, stop, op | 0x20, type); \
-GEN_STUF(name, stop, op | 0x21, type); \
-GEN_STUXF(name, stop, op | 0x01, type); \
-GEN_STXF(name, stop, 0x17, op | 0x00, type)
-
static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
{
TCGv_i32 tmp = tcg_temp_new_i32();
@@ -1190,11 +1019,6 @@ static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
tcg_temp_free_i32(tmp);
}
-/* stfd stfdu stfdux stfdx */
-GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
-/* stfs stfsu stfsux stfsx */
-GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
-
/* stfdepx (external PID lfdx) */
static void gen_stfdepx(DisasContext *ctx)
{
@@ -1473,6 +1297,77 @@ static void gen_stfqx(DisasContext *ctx)
tcg_temp_free_i64(t1);
}
+/* Floating-point Load/Store Instructions */
+static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
+ bool update, bool store, bool single)
+{
+ TCGv ea;
+ TCGv_i64 t0;
+ REQUIRE_INSNS_FLAGS(ctx, FLOAT);
+ REQUIRE_FPU(ctx);
+ if (update && ra == 0) {
+ gen_invalid(ctx);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t0 = tcg_temp_new_i64();
+ ea = do_ea_calc(ctx, ra, displ);
+ if (store) {
+ get_fpr(t0, rt);
+ if (single) {
+ gen_qemu_st32fs(ctx, t0, ea);
+ } else {
+ gen_qemu_st64_i64(ctx, t0, ea);
+ }
+ } else {
+ if (single) {
+ gen_qemu_ld32fs(ctx, t0, ea);
+ } else {
+ gen_qemu_ld64_i64(ctx, t0, ea);
+ }
+ set_fpr(rt, t0);
+ }
+ if (update) {
+ tcg_gen_mov_tl(cpu_gpr[rt], ea);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free(ea);
+ return true;
+}
+
+static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store,
+ bool single)
+{
+ return do_lsfpsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store,
+ single);
+}
+
+static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
+ bool store, bool single)
+{
+ return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single);
+}
+
+TRANS(LFS, do_lsfp_D, false, false, true)
+TRANS(LFSU, do_lsfp_D, true, false, true)
+TRANS(LFSX, do_lsfp_X, false, false, true)
+TRANS(LFSUX, do_lsfp_X, true, false, true)
+
+TRANS(LFD, do_lsfp_D, false, false, false)
+TRANS(LFDU, do_lsfp_D, true, false, false)
+TRANS(LFDX, do_lsfp_X, false, false, false)
+TRANS(LFDUX, do_lsfp_X, true, false, false)
+
+TRANS(STFS, do_lsfp_D, false, true, true)
+TRANS(STFSU, do_lsfp_D, true, true, true)
+TRANS(STFSX, do_lsfp_X, false, true, true)
+TRANS(STFSUX, do_lsfp_X, true, true, true)
+
+TRANS(STFD, do_lsfp_D, false, true, false)
+TRANS(STFDU, do_lsfp_D, true, true, false)
+TRANS(STFDX, do_lsfp_X, false, true, false)
+TRANS(STFDUX, do_lsfp_X, true, true, false)
+
#undef _GEN_FLOAT_ACB
#undef GEN_FLOAT_ACB
#undef _GEN_FLOAT_AB
diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc
index 88fab65628..4260635a12 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -50,43 +50,14 @@ GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
-#define GEN_LDF(name, ldop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUF(name, ldop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUXF(name, ldop, opc, type) \
-GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
-#define GEN_LDXF(name, ldop, opc2, opc3, type) \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_LDFS(name, ldop, op, type) \
-GEN_LDF(name, ldop, op | 0x20, type) \
-GEN_LDUF(name, ldop, op | 0x21, type) \
-GEN_LDUXF(name, ldop, op | 0x01, type) \
-GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-
-GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
-GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
-#define GEN_STF(name, stop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUF(name, stop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUXF(name, stop, opc, type) \
-GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
#define GEN_STXF(name, stop, opc2, opc3, type) \
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_STFS(name, stop, op, type) \
-GEN_STF(name, stop, op | 0x20, type) \
-GEN_STUF(name, stop, op | 0x21, type) \
-GEN_STUXF(name, stop, op | 0x01, type) \
-GEN_STXF(name, stop, 0x17, op | 0x00, type)
-GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
-GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree
2021-10-29 20:23 ` [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
@ 2021-11-09 13:43 ` Mark Cave-Ayland
2021-11-09 17:32 ` Matheus K. Ferst
0 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2021-11-09 13:43 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: Fernando Eckhardt Valle, lucas.castro, richard.henderson, groug,
luis.pires, Fernando Eckhardt Valle, david
[-- Attachment #1: Type: text/plain, Size: 22748 bytes --]
On 29/10/2021 21:23, matheus.ferst@eldorado.org.br wrote:
> From: Fernando Eckhardt Valle <phervalle@gmail.com>
>
> Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
> and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
> stfdux) from legacy system to decodetree.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
> v2:
> - if instead of top-level ternary operator
> ---
> target/ppc/insn32.decode | 24 +++
> target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
> target/ppc/translate/fp-ops.c.inc | 29 ----
> 3 files changed, 95 insertions(+), 205 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 6aec1c0728..3837b799c8 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -193,6 +193,30 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
>
> CFUGED 011111 ..... ..... ..... 0011011100 - @X
>
> +### Float-Point Load Instructions
> +
> +LFS 110000 ..... ..... ................ @D
> +LFSU 110001 ..... ..... ................ @D
> +LFSX 011111 ..... ..... ..... 1000010111 - @X
> +LFSUX 011111 ..... ..... ..... 1000110111 - @X
> +
> +LFD 110010 ..... ..... ................ @D
> +LFDU 110011 ..... ..... ................ @D
> +LFDX 011111 ..... ..... ..... 1001010111 - @X
> +LFDUX 011111 ..... ..... ..... 1001110111 - @X
> +
> +### Float-Point Store Instructions
> +
> +STFS 110100 ..... ...... ............... @D
> +STFSU 110101 ..... ...... ............... @D
> +STFSX 011111 ..... ...... .... 1010010111 - @X
> +STFSUX 011111 ..... ...... .... 1010110111 - @X
> +
> +STFD 110110 ..... ...... ............... @D
> +STFDU 110111 ..... ...... ............... @D
> +STFDX 011111 ..... ...... .... 1011010111 - @X
> +STFDUX 011111 ..... ...... .... 1011110111 - @X
> +
> ### Move To/From System Register Instructions
>
> SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
> diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
> index 9f7868ee28..57a799db1c 100644
> --- a/target/ppc/translate/fp-impl.c.inc
> +++ b/target/ppc/translate/fp-impl.c.inc
> @@ -854,99 +854,6 @@ static void gen_mtfsfi(DisasContext *ctx)
> gen_helper_float_check_status(cpu_env);
> }
>
> -/*** Floating-point load ***/
> -#define GEN_LDF(name, ldop, opc, type) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - TCGv_i64 t0; \
> - if (unlikely(!ctx->fpu_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_FPU); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_FLOAT); \
> - EA = tcg_temp_new(); \
> - t0 = tcg_temp_new_i64(); \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##ldop(ctx, t0, EA); \
> - set_fpr(rD(ctx->opcode), t0); \
> - tcg_temp_free(EA); \
> - tcg_temp_free_i64(t0); \
> -}
> -
> -#define GEN_LDUF(name, ldop, opc, type) \
> -static void glue(gen_, name##u)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - TCGv_i64 t0; \
> - if (unlikely(!ctx->fpu_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_FPU); \
> - return; \
> - } \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_FLOAT); \
> - EA = tcg_temp_new(); \
> - t0 = tcg_temp_new_i64(); \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##ldop(ctx, t0, EA); \
> - set_fpr(rD(ctx->opcode), t0); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> - tcg_temp_free_i64(t0); \
> -}
> -
> -#define GEN_LDUXF(name, ldop, opc, type) \
> -static void glue(gen_, name##ux)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - TCGv_i64 t0; \
> - if (unlikely(!ctx->fpu_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_FPU); \
> - return; \
> - } \
> - t0 = tcg_temp_new_i64(); \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_FLOAT); \
> - EA = tcg_temp_new(); \
> - gen_addr_reg_index(ctx, EA); \
> - gen_qemu_##ldop(ctx, t0, EA); \
> - set_fpr(rD(ctx->opcode), t0); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> - tcg_temp_free_i64(t0); \
> -}
> -
> -#define GEN_LDXF(name, ldop, opc2, opc3, type) \
> -static void glue(gen_, name##x)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - TCGv_i64 t0; \
> - if (unlikely(!ctx->fpu_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_FPU); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_FLOAT); \
> - EA = tcg_temp_new(); \
> - t0 = tcg_temp_new_i64(); \
> - gen_addr_reg_index(ctx, EA); \
> - gen_qemu_##ldop(ctx, t0, EA); \
> - set_fpr(rD(ctx->opcode), t0); \
> - tcg_temp_free(EA); \
> - tcg_temp_free_i64(t0); \
> -}
> -
> -#define GEN_LDFS(name, ldop, op, type) \
> -GEN_LDF(name, ldop, op | 0x20, type); \
> -GEN_LDUF(name, ldop, op | 0x21, type); \
> -GEN_LDUXF(name, ldop, op | 0x01, type); \
> -GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
> -
> static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
> {
> TCGv_i32 tmp = tcg_temp_new_i32();
> @@ -955,11 +862,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
> tcg_temp_free_i32(tmp);
> }
>
> - /* lfd lfdu lfdux lfdx */
> -GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
> - /* lfs lfsu lfsux lfsx */
> -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
> -
> /* lfdepx (external PID lfdx) */
> static void gen_lfdepx(DisasContext *ctx)
> {
> @@ -1089,73 +991,6 @@ static void gen_lfiwzx(DisasContext *ctx)
> tcg_temp_free(EA);
> tcg_temp_free_i64(t0);
> }
> -/*** Floating-point store ***/
> -#define GEN_STF(name, stop, opc, type) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - TCGv_i64 t0; \
> - if (unlikely(!ctx->fpu_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_FPU); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_FLOAT); \
> - EA = tcg_temp_new(); \
> - t0 = tcg_temp_new_i64(); \
> - gen_addr_imm_index(ctx, EA, 0); \
> - get_fpr(t0, rS(ctx->opcode)); \
> - gen_qemu_##stop(ctx, t0, EA); \
> - tcg_temp_free(EA); \
> - tcg_temp_free_i64(t0); \
> -}
> -
> -#define GEN_STUF(name, stop, opc, type) \
> -static void glue(gen_, name##u)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - TCGv_i64 t0; \
> - if (unlikely(!ctx->fpu_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_FPU); \
> - return; \
> - } \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_FLOAT); \
> - EA = tcg_temp_new(); \
> - t0 = tcg_temp_new_i64(); \
> - gen_addr_imm_index(ctx, EA, 0); \
> - get_fpr(t0, rS(ctx->opcode)); \
> - gen_qemu_##stop(ctx, t0, EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> - tcg_temp_free_i64(t0); \
> -}
> -
> -#define GEN_STUXF(name, stop, opc, type) \
> -static void glue(gen_, name##ux)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - TCGv_i64 t0; \
> - if (unlikely(!ctx->fpu_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_FPU); \
> - return; \
> - } \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_FLOAT); \
> - EA = tcg_temp_new(); \
> - t0 = tcg_temp_new_i64(); \
> - gen_addr_reg_index(ctx, EA); \
> - get_fpr(t0, rS(ctx->opcode)); \
> - gen_qemu_##stop(ctx, t0, EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> - tcg_temp_free_i64(t0); \
> -}
>
> #define GEN_STXF(name, stop, opc2, opc3, type) \
> static void glue(gen_, name##x)(DisasContext *ctx) \
> @@ -1176,12 +1011,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
> tcg_temp_free_i64(t0); \
> }
>
> -#define GEN_STFS(name, stop, op, type) \
> -GEN_STF(name, stop, op | 0x20, type); \
> -GEN_STUF(name, stop, op | 0x21, type); \
> -GEN_STUXF(name, stop, op | 0x01, type); \
> -GEN_STXF(name, stop, 0x17, op | 0x00, type)
> -
> static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
> {
> TCGv_i32 tmp = tcg_temp_new_i32();
> @@ -1190,11 +1019,6 @@ static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
> tcg_temp_free_i32(tmp);
> }
>
> -/* stfd stfdu stfdux stfdx */
> -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
> -/* stfs stfsu stfsux stfsx */
> -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
> -
> /* stfdepx (external PID lfdx) */
> static void gen_stfdepx(DisasContext *ctx)
> {
> @@ -1473,6 +1297,77 @@ static void gen_stfqx(DisasContext *ctx)
> tcg_temp_free_i64(t1);
> }
>
> +/* Floating-point Load/Store Instructions */
> +static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
> + bool update, bool store, bool single)
> +{
> + TCGv ea;
> + TCGv_i64 t0;
> + REQUIRE_INSNS_FLAGS(ctx, FLOAT);
> + REQUIRE_FPU(ctx);
> + if (update && ra == 0) {
> + gen_invalid(ctx);
> + return true;
> + }
> + gen_set_access_type(ctx, ACCESS_FLOAT);
> + t0 = tcg_temp_new_i64();
> + ea = do_ea_calc(ctx, ra, displ);
> + if (store) {
> + get_fpr(t0, rt);
> + if (single) {
> + gen_qemu_st32fs(ctx, t0, ea);
> + } else {
> + gen_qemu_st64_i64(ctx, t0, ea);
> + }
> + } else {
> + if (single) {
> + gen_qemu_ld32fs(ctx, t0, ea);
> + } else {
> + gen_qemu_ld64_i64(ctx, t0, ea);
> + }
> + set_fpr(rt, t0);
> + }
> + if (update) {
> + tcg_gen_mov_tl(cpu_gpr[rt], ea);
> + }
> + tcg_temp_free_i64(t0);
> + tcg_temp_free(ea);
> + return true;
> +}
> +
> +static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store,
> + bool single)
> +{
> + return do_lsfpsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store,
> + single);
> +}
> +
> +static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
> + bool store, bool single)
> +{
> + return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single);
> +}
> +
> +TRANS(LFS, do_lsfp_D, false, false, true)
> +TRANS(LFSU, do_lsfp_D, true, false, true)
> +TRANS(LFSX, do_lsfp_X, false, false, true)
> +TRANS(LFSUX, do_lsfp_X, true, false, true)
> +
> +TRANS(LFD, do_lsfp_D, false, false, false)
> +TRANS(LFDU, do_lsfp_D, true, false, false)
> +TRANS(LFDX, do_lsfp_X, false, false, false)
> +TRANS(LFDUX, do_lsfp_X, true, false, false)
> +
> +TRANS(STFS, do_lsfp_D, false, true, true)
> +TRANS(STFSU, do_lsfp_D, true, true, true)
> +TRANS(STFSX, do_lsfp_X, false, true, true)
> +TRANS(STFSUX, do_lsfp_X, true, true, true)
> +
> +TRANS(STFD, do_lsfp_D, false, true, false)
> +TRANS(STFDU, do_lsfp_D, true, true, false)
> +TRANS(STFDX, do_lsfp_X, false, true, false)
> +TRANS(STFDUX, do_lsfp_X, true, true, false)
> +
> #undef _GEN_FLOAT_ACB
> #undef GEN_FLOAT_ACB
> #undef _GEN_FLOAT_AB
> diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc
> index 88fab65628..4260635a12 100644
> --- a/target/ppc/translate/fp-ops.c.inc
> +++ b/target/ppc/translate/fp-ops.c.inc
> @@ -50,43 +50,14 @@ GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
> GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
> GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
>
> -#define GEN_LDF(name, ldop, opc, type) \
> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_LDUF(name, ldop, opc, type) \
> -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_LDUXF(name, ldop, opc, type) \
> -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
> -#define GEN_LDXF(name, ldop, opc2, opc3, type) \
> -GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
> -#define GEN_LDFS(name, ldop, op, type) \
> -GEN_LDF(name, ldop, op | 0x20, type) \
> -GEN_LDUF(name, ldop, op | 0x21, type) \
> -GEN_LDUXF(name, ldop, op | 0x01, type) \
> -GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
> -
> -GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
> -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
> GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
> GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
> GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
> GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
>
> -#define GEN_STF(name, stop, opc, type) \
> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_STUF(name, stop, opc, type) \
> -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_STUXF(name, stop, opc, type) \
> -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
> #define GEN_STXF(name, stop, opc2, opc3, type) \
> GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
> -#define GEN_STFS(name, stop, op, type) \
> -GEN_STF(name, stop, op | 0x20, type) \
> -GEN_STUF(name, stop, op | 0x21, type) \
> -GEN_STUXF(name, stop, op | 0x01, type) \
> -GEN_STXF(name, stop, 0x17, op | 0x00, type)
>
> -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
> -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
> GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
> GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
> GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
This commit appears to break both MacOS 9 and OS X under qemu-system-ppc in my boot
tests: MacOS 9 hangs early on startup, whilst OS X now has black box artifacts on
some GUI widgets (see attached).
Any idea what could be happening here? Note that this series isn't bisectable - it is
necessary to forward-port the REQUIRE_FPU macro in order to build this commit for
PPC32, and I also found errors relating to undefined times_* functions during bisection.
ATB,
Mark.
[-- Attachment #2: macos-bad.png --]
[-- Type: image/png, Size: 74699 bytes --]
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree
2021-11-09 13:43 ` Mark Cave-Ayland
@ 2021-11-09 17:32 ` Matheus K. Ferst
2021-11-09 18:24 ` Mark Cave-Ayland
0 siblings, 1 reply; 54+ messages in thread
From: Matheus K. Ferst @ 2021-11-09 17:32 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, qemu-ppc
Cc: Fernando Eckhardt Valle, lucas.castro, richard.henderson, groug,
luis.pires, Fernando Eckhardt Valle, david
[-- Attachment #1: Type: text/plain, Size: 31301 bytes --]
On 09/11/2021 10:43, Mark Cave-Ayland wrote:
> On 29/10/2021 21:23, matheus.ferst@eldorado.org.br wrote:
>
>> From: Fernando Eckhardt Valle <phervalle@gmail.com>
>>
>> Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd,
>> lfdu, lfdx, lfdux)
>> and store floating point instructions(stfs, stfsu, stfsx, stfsux,
>> stfd, stfdu, stfdx,
>> stfdux) from legacy system to decodetree.
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
>> ---
>> v2:
>> - if instead of top-level ternary operator
>> ---
>> target/ppc/insn32.decode | 24 +++
>> target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
>> target/ppc/translate/fp-ops.c.inc | 29 ----
>> 3 files changed, 95 insertions(+), 205 deletions(-)
>>
>> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
>> index 6aec1c0728..3837b799c8 100644
>> --- a/target/ppc/insn32.decode
>> +++ b/target/ppc/insn32.decode
>> @@ -193,6 +193,30 @@ ADDPCIS 010011 ..... ..... ..........
>> 00010 . @DX
>>
>> CFUGED 011111 ..... ..... ..... 0011011100 - @X
>>
>> +### Float-Point Load Instructions
>> +
>> +LFS 110000 ..... ..... ................ @D
>> +LFSU 110001 ..... ..... ................ @D
>> +LFSX 011111 ..... ..... ..... 1000010111 - @X
>> +LFSUX 011111 ..... ..... ..... 1000110111 - @X
>> +
>> +LFD 110010 ..... ..... ................ @D
>> +LFDU 110011 ..... ..... ................ @D
>> +LFDX 011111 ..... ..... ..... 1001010111 - @X
>> +LFDUX 011111 ..... ..... ..... 1001110111 - @X
>> +
>> +### Float-Point Store Instructions
>> +
>> +STFS 110100 ..... ...... ............... @D
>> +STFSU 110101 ..... ...... ............... @D
>> +STFSX 011111 ..... ...... .... 1010010111 - @X
>> +STFSUX 011111 ..... ...... .... 1010110111 - @X
>> +
>> +STFD 110110 ..... ...... ............... @D
>> +STFDU 110111 ..... ...... ............... @D
>> +STFDX 011111 ..... ...... .... 1011010111 - @X
>> +STFDUX 011111 ..... ...... .... 1011110111 - @X
>> +
>> ### Move To/From System Register Instructions
>>
>> SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
>> diff --git a/target/ppc/translate/fp-impl.c.inc
>> b/target/ppc/translate/fp-impl.c.inc
>> index 9f7868ee28..57a799db1c 100644
>> --- a/target/ppc/translate/fp-impl.c.inc
>> +++ b/target/ppc/translate/fp-impl.c.inc
>> @@ -854,99 +854,6 @@ static void gen_mtfsfi(DisasContext *ctx)
>> gen_helper_float_check_status(cpu_env);
>> }
>>
>> -/*** Floating-point
>> load ***/
>> -#define GEN_LDF(name, ldop, opc,
>> type) \
>> -static void glue(gen_, name)(DisasContext
>> *ctx) \
>> -{
>> \
>> - TCGv
>> EA; \
>> - TCGv_i64
>> t0; \
>> - if (unlikely(!ctx->fpu_enabled))
>> { \
>> - gen_exception(ctx,
>> POWERPC_EXCP_FPU); \
>> -
>> return; \
>> -
>> }
>> \
>> - gen_set_access_type(ctx,
>> ACCESS_FLOAT); \
>> - EA =
>> tcg_temp_new(); \
>> - t0 =
>> tcg_temp_new_i64(); \
>> - gen_addr_imm_index(ctx, EA,
>> 0); \
>> - gen_qemu_##ldop(ctx, t0,
>> EA); \
>> - set_fpr(rD(ctx->opcode),
>> t0); \
>> -
>> tcg_temp_free(EA);
>> \
>> -
>> tcg_temp_free_i64(t0);
>> \
>> -}
>> -
>> -#define GEN_LDUF(name, ldop, opc,
>> type) \
>> -static void glue(gen_, name##u)(DisasContext
>> *ctx) \
>> -{
>> \
>> - TCGv
>> EA; \
>> - TCGv_i64
>> t0; \
>> - if (unlikely(!ctx->fpu_enabled))
>> { \
>> - gen_exception(ctx,
>> POWERPC_EXCP_FPU); \
>> -
>> return; \
>> -
>> }
>> \
>> - if (unlikely(rA(ctx->opcode) == 0))
>> { \
>> - gen_inval_exception(ctx,
>> POWERPC_EXCP_INVAL_INVAL); \
>> -
>> return; \
>> -
>> }
>> \
>> - gen_set_access_type(ctx,
>> ACCESS_FLOAT); \
>> - EA =
>> tcg_temp_new(); \
>> - t0 =
>> tcg_temp_new_i64(); \
>> - gen_addr_imm_index(ctx, EA,
>> 0); \
>> - gen_qemu_##ldop(ctx, t0,
>> EA); \
>> - set_fpr(rD(ctx->opcode),
>> t0); \
>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)],
>> EA); \
>> -
>> tcg_temp_free(EA);
>> \
>> -
>> tcg_temp_free_i64(t0);
>> \
>> -}
>> -
>> -#define GEN_LDUXF(name, ldop, opc,
>> type) \
>> -static void glue(gen_, name##ux)(DisasContext
>> *ctx) \
>> -{
>> \
>> - TCGv
>> EA; \
>> - TCGv_i64
>> t0; \
>> - if (unlikely(!ctx->fpu_enabled))
>> { \
>> - gen_exception(ctx,
>> POWERPC_EXCP_FPU); \
>> -
>> return; \
>> -
>> }
>> \
>> - t0 =
>> tcg_temp_new_i64(); \
>> - if (unlikely(rA(ctx->opcode) == 0))
>> { \
>> - gen_inval_exception(ctx,
>> POWERPC_EXCP_INVAL_INVAL); \
>> -
>> return; \
>> -
>> }
>> \
>> - gen_set_access_type(ctx,
>> ACCESS_FLOAT); \
>> - EA =
>> tcg_temp_new(); \
>> - gen_addr_reg_index(ctx,
>> EA); \
>> - gen_qemu_##ldop(ctx, t0,
>> EA); \
>> - set_fpr(rD(ctx->opcode),
>> t0); \
>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)],
>> EA); \
>> -
>> tcg_temp_free(EA);
>> \
>> -
>> tcg_temp_free_i64(t0);
>> \
>> -}
>> -
>> -#define GEN_LDXF(name, ldop, opc2, opc3,
>> type) \
>> -static void glue(gen_, name##x)(DisasContext
>> *ctx) \
>> -{
>> \
>> - TCGv
>> EA; \
>> - TCGv_i64
>> t0; \
>> - if (unlikely(!ctx->fpu_enabled))
>> { \
>> - gen_exception(ctx,
>> POWERPC_EXCP_FPU); \
>> -
>> return; \
>> -
>> }
>> \
>> - gen_set_access_type(ctx,
>> ACCESS_FLOAT); \
>> - EA =
>> tcg_temp_new(); \
>> - t0 =
>> tcg_temp_new_i64(); \
>> - gen_addr_reg_index(ctx,
>> EA); \
>> - gen_qemu_##ldop(ctx, t0,
>> EA); \
>> - set_fpr(rD(ctx->opcode),
>> t0); \
>> -
>> tcg_temp_free(EA);
>> \
>> -
>> tcg_temp_free_i64(t0);
>> \
>> -}
>> -
>> -#define GEN_LDFS(name, ldop, op,
>> type) \
>> -GEN_LDF(name, ldop, op | 0x20,
>> type); \
>> -GEN_LDUF(name, ldop, op | 0x21,
>> type); \
>> -GEN_LDUXF(name, ldop, op | 0x01,
>> type); \
>> -GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
>> -
>> static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv
>> addr)
>> {
>> TCGv_i32 tmp = tcg_temp_new_i32();
>> @@ -955,11 +862,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx,
>> TCGv_i64 dest, TCGv addr)
>> tcg_temp_free_i32(tmp);
>> }
>>
>> - /* lfd lfdu lfdux lfdx */
>> -GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
>> - /* lfs lfsu lfsux lfsx */
>> -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
>> -
>> /* lfdepx (external PID lfdx) */
>> static void gen_lfdepx(DisasContext *ctx)
>> {
>> @@ -1089,73 +991,6 @@ static void gen_lfiwzx(DisasContext *ctx)
>> tcg_temp_free(EA);
>> tcg_temp_free_i64(t0);
>> }
>> -/*** Floating-point
>> store ***/
>> -#define GEN_STF(name, stop, opc,
>> type) \
>> -static void glue(gen_, name)(DisasContext
>> *ctx) \
>> -{
>> \
>> - TCGv
>> EA; \
>> - TCGv_i64
>> t0; \
>> - if (unlikely(!ctx->fpu_enabled))
>> { \
>> - gen_exception(ctx,
>> POWERPC_EXCP_FPU); \
>> -
>> return; \
>> -
>> }
>> \
>> - gen_set_access_type(ctx,
>> ACCESS_FLOAT); \
>> - EA =
>> tcg_temp_new(); \
>> - t0 =
>> tcg_temp_new_i64(); \
>> - gen_addr_imm_index(ctx, EA,
>> 0); \
>> - get_fpr(t0,
>> rS(ctx->opcode)); \
>> - gen_qemu_##stop(ctx, t0,
>> EA); \
>> -
>> tcg_temp_free(EA);
>> \
>> -
>> tcg_temp_free_i64(t0);
>> \
>> -}
>> -
>> -#define GEN_STUF(name, stop, opc,
>> type) \
>> -static void glue(gen_, name##u)(DisasContext
>> *ctx) \
>> -{
>> \
>> - TCGv
>> EA; \
>> - TCGv_i64
>> t0; \
>> - if (unlikely(!ctx->fpu_enabled))
>> { \
>> - gen_exception(ctx,
>> POWERPC_EXCP_FPU); \
>> -
>> return; \
>> -
>> }
>> \
>> - if (unlikely(rA(ctx->opcode) == 0))
>> { \
>> - gen_inval_exception(ctx,
>> POWERPC_EXCP_INVAL_INVAL); \
>> -
>> return; \
>> -
>> }
>> \
>> - gen_set_access_type(ctx,
>> ACCESS_FLOAT); \
>> - EA =
>> tcg_temp_new(); \
>> - t0 =
>> tcg_temp_new_i64(); \
>> - gen_addr_imm_index(ctx, EA,
>> 0); \
>> - get_fpr(t0,
>> rS(ctx->opcode)); \
>> - gen_qemu_##stop(ctx, t0,
>> EA); \
>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)],
>> EA); \
>> -
>> tcg_temp_free(EA);
>> \
>> -
>> tcg_temp_free_i64(t0);
>> \
>> -}
>> -
>> -#define GEN_STUXF(name, stop, opc,
>> type) \
>> -static void glue(gen_, name##ux)(DisasContext
>> *ctx) \
>> -{
>> \
>> - TCGv
>> EA; \
>> - TCGv_i64
>> t0; \
>> - if (unlikely(!ctx->fpu_enabled))
>> { \
>> - gen_exception(ctx,
>> POWERPC_EXCP_FPU); \
>> -
>> return; \
>> -
>> }
>> \
>> - if (unlikely(rA(ctx->opcode) == 0))
>> { \
>> - gen_inval_exception(ctx,
>> POWERPC_EXCP_INVAL_INVAL); \
>> -
>> return; \
>> -
>> }
>> \
>> - gen_set_access_type(ctx,
>> ACCESS_FLOAT); \
>> - EA =
>> tcg_temp_new(); \
>> - t0 =
>> tcg_temp_new_i64(); \
>> - gen_addr_reg_index(ctx,
>> EA); \
>> - get_fpr(t0,
>> rS(ctx->opcode)); \
>> - gen_qemu_##stop(ctx, t0,
>> EA); \
>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)],
>> EA); \
>> -
>> tcg_temp_free(EA);
>> \
>> -
>> tcg_temp_free_i64(t0);
>> \
>> -}
>>
>> #define GEN_STXF(name, stop, opc2, opc3,
>> type) \
>> static void glue(gen_, name##x)(DisasContext
>> *ctx) \
>> @@ -1176,12 +1011,6 @@ static void glue(gen_, name##x)(DisasContext
>> *ctx) \
>>
>> tcg_temp_free_i64(t0);
>> \
>> }
>>
>> -#define GEN_STFS(name, stop, op,
>> type) \
>> -GEN_STF(name, stop, op | 0x20,
>> type); \
>> -GEN_STUF(name, stop, op | 0x21,
>> type); \
>> -GEN_STUXF(name, stop, op | 0x01,
>> type); \
>> -GEN_STXF(name, stop, 0x17, op | 0x00, type)
>> -
>> static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
>> {
>> TCGv_i32 tmp = tcg_temp_new_i32();
>> @@ -1190,11 +1019,6 @@ static void gen_qemu_st32fs(DisasContext *ctx,
>> TCGv_i64 src, TCGv addr)
>> tcg_temp_free_i32(tmp);
>> }
>>
>> -/* stfd stfdu stfdux stfdx */
>> -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
>> -/* stfs stfsu stfsux stfsx */
>> -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
>> -
>> /* stfdepx (external PID lfdx) */
>> static void gen_stfdepx(DisasContext *ctx)
>> {
>> @@ -1473,6 +1297,77 @@ static void gen_stfqx(DisasContext *ctx)
>> tcg_temp_free_i64(t1);
>> }
>>
>> +/* Floating-point Load/Store
>> Instructions */
>> +static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
>> + bool update, bool store, bool single)
>> +{
>> + TCGv ea;
>> + TCGv_i64 t0;
>> + REQUIRE_INSNS_FLAGS(ctx, FLOAT);
>> + REQUIRE_FPU(ctx);
>> + if (update && ra == 0) {
>> + gen_invalid(ctx);
>> + return true;
>> + }
>> + gen_set_access_type(ctx, ACCESS_FLOAT);
>> + t0 = tcg_temp_new_i64();
>> + ea = do_ea_calc(ctx, ra, displ);
>> + if (store) {
>> + get_fpr(t0, rt);
>> + if (single) {
>> + gen_qemu_st32fs(ctx, t0, ea);
>> + } else {
>> + gen_qemu_st64_i64(ctx, t0, ea);
>> + }
>> + } else {
>> + if (single) {
>> + gen_qemu_ld32fs(ctx, t0, ea);
>> + } else {
>> + gen_qemu_ld64_i64(ctx, t0, ea);
>> + }
>> + set_fpr(rt, t0);
>> + }
>> + if (update) {
>> + tcg_gen_mov_tl(cpu_gpr[rt], ea);
>> + }
>> + tcg_temp_free_i64(t0);
>> + tcg_temp_free(ea);
>> + return true;
>> +}
>> +
>> +static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool
>> store,
>> + bool single)
>> +{
>> + return do_lsfpsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si),
>> update, store,
>> + single);
>> +}
>> +
>> +static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
>> + bool store, bool single)
>> +{
>> + return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update,
>> store, single);
>> +}
>> +
>> +TRANS(LFS, do_lsfp_D, false, false, true)
>> +TRANS(LFSU, do_lsfp_D, true, false, true)
>> +TRANS(LFSX, do_lsfp_X, false, false, true)
>> +TRANS(LFSUX, do_lsfp_X, true, false, true)
>> +
>> +TRANS(LFD, do_lsfp_D, false, false, false)
>> +TRANS(LFDU, do_lsfp_D, true, false, false)
>> +TRANS(LFDX, do_lsfp_X, false, false, false)
>> +TRANS(LFDUX, do_lsfp_X, true, false, false)
>> +
>> +TRANS(STFS, do_lsfp_D, false, true, true)
>> +TRANS(STFSU, do_lsfp_D, true, true, true)
>> +TRANS(STFSX, do_lsfp_X, false, true, true)
>> +TRANS(STFSUX, do_lsfp_X, true, true, true)
>> +
>> +TRANS(STFD, do_lsfp_D, false, true, false)
>> +TRANS(STFDU, do_lsfp_D, true, true, false)
>> +TRANS(STFDX, do_lsfp_X, false, true, false)
>> +TRANS(STFDUX, do_lsfp_X, true, true, false)
>> +
>> #undef _GEN_FLOAT_ACB
>> #undef GEN_FLOAT_ACB
>> #undef _GEN_FLOAT_AB
>> diff --git a/target/ppc/translate/fp-ops.c.inc
>> b/target/ppc/translate/fp-ops.c.inc
>> index 88fab65628..4260635a12 100644
>> --- a/target/ppc/translate/fp-ops.c.inc
>> +++ b/target/ppc/translate/fp-ops.c.inc
>> @@ -50,43 +50,14 @@ GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
>> GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
>> GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
>>
>> -#define GEN_LDF(name, ldop, opc,
>> type) \
>> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
>> -#define GEN_LDUF(name, ldop, opc,
>> type) \
>> -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
>> -#define GEN_LDUXF(name, ldop, opc,
>> type) \
>> -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
>> -#define GEN_LDXF(name, ldop, opc2, opc3,
>> type) \
>> -GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
>> -#define GEN_LDFS(name, ldop, op,
>> type) \
>> -GEN_LDF(name, ldop, op | 0x20,
>> type) \
>> -GEN_LDUF(name, ldop, op | 0x21,
>> type) \
>> -GEN_LDUXF(name, ldop, op | 0x01,
>> type) \
>> -GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
>> -
>> -GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
>> -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
>> GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE,
>> PPC2_BOOKE206),
>> GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE,
>> PPC2_ISA205),
>> GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE,
>> PPC2_FP_CVT_ISA206),
>> GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE,
>> PPC2_ISA205),
>>
>> -#define GEN_STF(name, stop, opc,
>> type) \
>> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
>> -#define GEN_STUF(name, stop, opc,
>> type) \
>> -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
>> -#define GEN_STUXF(name, stop, opc,
>> type) \
>> -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
>> #define GEN_STXF(name, stop, opc2, opc3,
>> type) \
>> GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
>> -#define GEN_STFS(name, stop, op,
>> type) \
>> -GEN_STF(name, stop, op | 0x20,
>> type) \
>> -GEN_STUF(name, stop, op | 0x21,
>> type) \
>> -GEN_STUXF(name, stop, op | 0x01,
>> type) \
>> -GEN_STXF(name, stop, 0x17, op | 0x00, type)
>>
>> -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
>> -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
>> GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
>> GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE,
>> PPC2_BOOKE206),
>> GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE,
>> PPC2_ISA205),
>
> This commit appears to break both MacOS 9 and OS X under qemu-system-ppc
> in my boot
> tests: MacOS 9 hangs early on startup, whilst OS X now has black box
> artifacts on
> some GUI widgets (see attached).
It seems that we're updating the wrong register (RT instead of RA). Can
you test the attached patch?
> Any idea what could be happening here? Note that this series isn't
> bisectable - it is
> necessary to forward-port the REQUIRE_FPU macro in order to build this
> commit for
> PPC32, and I also found errors relating to undefined times_* functions
> during bisection.
REQUIRE_FPU and the times_* functions come from the DFP patch series, in
which this series is based-on, so "target/ppc: Introduce REQUIRE_FPU"
was supposed to be merged before this patch. Maybe something went wrong
when these series were partially applied
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
[-- Attachment #2: 0001-fixup-target-ppc-Move-load-and-store-floating-point-.patch --]
[-- Type: text/x-patch, Size: 916 bytes --]
From 0ae11665ca66f3c304f3027513a140fab28d4bc2 Mon Sep 17 00:00:00 2001
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: Tue, 9 Nov 2021 13:57:30 -0300
Subject: [PATCH] fixup! target/ppc: Move load and store floating point instructions to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate/fp-impl.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index d1dbb1b96b..c9e05201d9 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -1328,7 +1328,7 @@ static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
set_fpr(rt, t0);
}
if (update) {
- tcg_gen_mov_tl(cpu_gpr[rt], ea);
+ tcg_gen_mov_tl(cpu_gpr[ra], ea);
}
tcg_temp_free_i64(t0);
tcg_temp_free(ea);
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree
2021-11-09 17:32 ` Matheus K. Ferst
@ 2021-11-09 18:24 ` Mark Cave-Ayland
0 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2021-11-09 18:24 UTC (permalink / raw)
To: Matheus K. Ferst, qemu-devel, qemu-ppc
Cc: Fernando Eckhardt Valle, lucas.castro, richard.henderson, groug,
luis.pires, Fernando Eckhardt Valle, david
On 09/11/2021 17:32, Matheus K. Ferst wrote:
> On 09/11/2021 10:43, Mark Cave-Ayland wrote:
>> On 29/10/2021 21:23, matheus.ferst@eldorado.org.br wrote:
>>
>>> From: Fernando Eckhardt Valle <phervalle@gmail.com>
>>>
>>> Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx,
>>> lfdux)
>>> and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
>>> stfdux) from legacy system to decodetree.
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
>>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
>>> ---
>>> v2:
>>> - if instead of top-level ternary operator
>>> ---
>>> target/ppc/insn32.decode | 24 +++
>>> target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
>>> target/ppc/translate/fp-ops.c.inc | 29 ----
>>> 3 files changed, 95 insertions(+), 205 deletions(-)
>>>
>>> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
>>> index 6aec1c0728..3837b799c8 100644
>>> --- a/target/ppc/insn32.decode
>>> +++ b/target/ppc/insn32.decode
>>> @@ -193,6 +193,30 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
>>>
>>> CFUGED 011111 ..... ..... ..... 0011011100 - @X
>>>
>>> +### Float-Point Load Instructions
>>> +
>>> +LFS 110000 ..... ..... ................ @D
>>> +LFSU 110001 ..... ..... ................ @D
>>> +LFSX 011111 ..... ..... ..... 1000010111 - @X
>>> +LFSUX 011111 ..... ..... ..... 1000110111 - @X
>>> +
>>> +LFD 110010 ..... ..... ................ @D
>>> +LFDU 110011 ..... ..... ................ @D
>>> +LFDX 011111 ..... ..... ..... 1001010111 - @X
>>> +LFDUX 011111 ..... ..... ..... 1001110111 - @X
>>> +
>>> +### Float-Point Store Instructions
>>> +
>>> +STFS 110100 ..... ...... ............... @D
>>> +STFSU 110101 ..... ...... ............... @D
>>> +STFSX 011111 ..... ...... .... 1010010111 - @X
>>> +STFSUX 011111 ..... ...... .... 1010110111 - @X
>>> +
>>> +STFD 110110 ..... ...... ............... @D
>>> +STFDU 110111 ..... ...... ............... @D
>>> +STFDX 011111 ..... ...... .... 1011010111 - @X
>>> +STFDUX 011111 ..... ...... .... 1011110111 - @X
>>> +
>>> ### Move To/From System Register Instructions
>>>
>>> SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
>>> diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
>>> index 9f7868ee28..57a799db1c 100644
>>> --- a/target/ppc/translate/fp-impl.c.inc
>>> +++ b/target/ppc/translate/fp-impl.c.inc
>>> @@ -854,99 +854,6 @@ static void gen_mtfsfi(DisasContext *ctx)
>>> gen_helper_float_check_status(cpu_env);
>>> }
>>>
>>> -/*** Floating-point load ***/
>>> -#define GEN_LDF(name, ldop, opc, type) \
>>> -static void glue(gen_, name)(DisasContext *ctx) \
>>> -{ \
>>> - TCGv EA; \
>>> - TCGv_i64 t0; \
>>> - if (unlikely(!ctx->fpu_enabled)) { \
>>> - gen_exception(ctx, POWERPC_EXCP_FPU); \
>>> - return; \
>>> - } \
>>> - gen_set_access_type(ctx, ACCESS_FLOAT); \
>>> - EA = tcg_temp_new(); \
>>> - t0 = tcg_temp_new_i64(); \
>>> - gen_addr_imm_index(ctx, EA, 0); \
>>> - gen_qemu_##ldop(ctx, t0, EA); \
>>> - set_fpr(rD(ctx->opcode), t0); \
>>> - tcg_temp_free(EA); \
>>> - tcg_temp_free_i64(t0); \
>>> -}
>>> -
>>> -#define GEN_LDUF(name, ldop, opc, type) \
>>> -static void glue(gen_, name##u)(DisasContext *ctx) \
>>> -{ \
>>> - TCGv EA; \
>>> - TCGv_i64 t0; \
>>> - if (unlikely(!ctx->fpu_enabled)) { \
>>> - gen_exception(ctx, POWERPC_EXCP_FPU); \
>>> - return; \
>>> - } \
>>> - if (unlikely(rA(ctx->opcode) == 0)) { \
>>> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
>>> - return; \
>>> - } \
>>> - gen_set_access_type(ctx, ACCESS_FLOAT); \
>>> - EA = tcg_temp_new(); \
>>> - t0 = tcg_temp_new_i64(); \
>>> - gen_addr_imm_index(ctx, EA, 0); \
>>> - gen_qemu_##ldop(ctx, t0, EA); \
>>> - set_fpr(rD(ctx->opcode), t0); \
>>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
>>> - tcg_temp_free(EA); \
>>> - tcg_temp_free_i64(t0); \
>>> -}
>>> -
>>> -#define GEN_LDUXF(name, ldop, opc, type) \
>>> -static void glue(gen_, name##ux)(DisasContext *ctx) \
>>> -{ \
>>> - TCGv EA; \
>>> - TCGv_i64 t0; \
>>> - if (unlikely(!ctx->fpu_enabled)) { \
>>> - gen_exception(ctx, POWERPC_EXCP_FPU); \
>>> - return; \
>>> - } \
>>> - t0 = tcg_temp_new_i64(); \
>>> - if (unlikely(rA(ctx->opcode) == 0)) { \
>>> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
>>> - return; \
>>> - } \
>>> - gen_set_access_type(ctx, ACCESS_FLOAT); \
>>> - EA = tcg_temp_new(); \
>>> - gen_addr_reg_index(ctx, EA); \
>>> - gen_qemu_##ldop(ctx, t0, EA); \
>>> - set_fpr(rD(ctx->opcode), t0); \
>>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
>>> - tcg_temp_free(EA); \
>>> - tcg_temp_free_i64(t0); \
>>> -}
>>> -
>>> -#define GEN_LDXF(name, ldop, opc2, opc3, type) \
>>> -static void glue(gen_, name##x)(DisasContext *ctx) \
>>> -{ \
>>> - TCGv EA; \
>>> - TCGv_i64 t0; \
>>> - if (unlikely(!ctx->fpu_enabled)) { \
>>> - gen_exception(ctx, POWERPC_EXCP_FPU); \
>>> - return; \
>>> - } \
>>> - gen_set_access_type(ctx, ACCESS_FLOAT); \
>>> - EA = tcg_temp_new(); \
>>> - t0 = tcg_temp_new_i64(); \
>>> - gen_addr_reg_index(ctx, EA); \
>>> - gen_qemu_##ldop(ctx, t0, EA); \
>>> - set_fpr(rD(ctx->opcode), t0); \
>>> - tcg_temp_free(EA); \
>>> - tcg_temp_free_i64(t0); \
>>> -}
>>> -
>>> -#define GEN_LDFS(name, ldop, op, type) \
>>> -GEN_LDF(name, ldop, op | 0x20, type); \
>>> -GEN_LDUF(name, ldop, op | 0x21, type); \
>>> -GEN_LDUXF(name, ldop, op | 0x01, type); \
>>> -GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
>>> -
>>> static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
>>> {
>>> TCGv_i32 tmp = tcg_temp_new_i32();
>>> @@ -955,11 +862,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest,
>>> TCGv addr)
>>> tcg_temp_free_i32(tmp);
>>> }
>>>
>>> - /* lfd lfdu lfdux lfdx */
>>> -GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
>>> - /* lfs lfsu lfsux lfsx */
>>> -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
>>> -
>>> /* lfdepx (external PID lfdx) */
>>> static void gen_lfdepx(DisasContext *ctx)
>>> {
>>> @@ -1089,73 +991,6 @@ static void gen_lfiwzx(DisasContext *ctx)
>>> tcg_temp_free(EA);
>>> tcg_temp_free_i64(t0);
>>> }
>>> -/*** Floating-point store ***/
>>> -#define GEN_STF(name, stop, opc, type) \
>>> -static void glue(gen_, name)(DisasContext *ctx) \
>>> -{ \
>>> - TCGv EA; \
>>> - TCGv_i64 t0; \
>>> - if (unlikely(!ctx->fpu_enabled)) { \
>>> - gen_exception(ctx, POWERPC_EXCP_FPU); \
>>> - return; \
>>> - } \
>>> - gen_set_access_type(ctx, ACCESS_FLOAT); \
>>> - EA = tcg_temp_new(); \
>>> - t0 = tcg_temp_new_i64(); \
>>> - gen_addr_imm_index(ctx, EA, 0); \
>>> - get_fpr(t0, rS(ctx->opcode)); \
>>> - gen_qemu_##stop(ctx, t0, EA); \
>>> - tcg_temp_free(EA); \
>>> - tcg_temp_free_i64(t0); \
>>> -}
>>> -
>>> -#define GEN_STUF(name, stop, opc, type) \
>>> -static void glue(gen_, name##u)(DisasContext *ctx) \
>>> -{ \
>>> - TCGv EA; \
>>> - TCGv_i64 t0; \
>>> - if (unlikely(!ctx->fpu_enabled)) { \
>>> - gen_exception(ctx, POWERPC_EXCP_FPU); \
>>> - return; \
>>> - } \
>>> - if (unlikely(rA(ctx->opcode) == 0)) { \
>>> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
>>> - return; \
>>> - } \
>>> - gen_set_access_type(ctx, ACCESS_FLOAT); \
>>> - EA = tcg_temp_new(); \
>>> - t0 = tcg_temp_new_i64(); \
>>> - gen_addr_imm_index(ctx, EA, 0); \
>>> - get_fpr(t0, rS(ctx->opcode)); \
>>> - gen_qemu_##stop(ctx, t0, EA); \
>>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
>>> - tcg_temp_free(EA); \
>>> - tcg_temp_free_i64(t0); \
>>> -}
>>> -
>>> -#define GEN_STUXF(name, stop, opc, type) \
>>> -static void glue(gen_, name##ux)(DisasContext *ctx) \
>>> -{ \
>>> - TCGv EA; \
>>> - TCGv_i64 t0; \
>>> - if (unlikely(!ctx->fpu_enabled)) { \
>>> - gen_exception(ctx, POWERPC_EXCP_FPU); \
>>> - return; \
>>> - } \
>>> - if (unlikely(rA(ctx->opcode) == 0)) { \
>>> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
>>> - return; \
>>> - } \
>>> - gen_set_access_type(ctx, ACCESS_FLOAT); \
>>> - EA = tcg_temp_new(); \
>>> - t0 = tcg_temp_new_i64(); \
>>> - gen_addr_reg_index(ctx, EA); \
>>> - get_fpr(t0, rS(ctx->opcode)); \
>>> - gen_qemu_##stop(ctx, t0, EA); \
>>> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
>>> - tcg_temp_free(EA); \
>>> - tcg_temp_free_i64(t0); \
>>> -}
>>>
>>> #define GEN_STXF(name, stop, opc2, opc3, type) \
>>> static void glue(gen_, name##x)(DisasContext *ctx) \
>>> @@ -1176,12 +1011,6 @@ static void glue(gen_, name##x)(DisasContext
>>> *ctx) \
>>> tcg_temp_free_i64(t0); \
>>> }
>>>
>>> -#define GEN_STFS(name, stop, op, type) \
>>> -GEN_STF(name, stop, op | 0x20, type); \
>>> -GEN_STUF(name, stop, op | 0x21, type); \
>>> -GEN_STUXF(name, stop, op | 0x01, type); \
>>> -GEN_STXF(name, stop, 0x17, op | 0x00, type)
>>> -
>>> static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
>>> {
>>> TCGv_i32 tmp = tcg_temp_new_i32();
>>> @@ -1190,11 +1019,6 @@ static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64
>>> src, TCGv addr)
>>> tcg_temp_free_i32(tmp);
>>> }
>>>
>>> -/* stfd stfdu stfdux stfdx */
>>> -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
>>> -/* stfs stfsu stfsux stfsx */
>>> -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
>>> -
>>> /* stfdepx (external PID lfdx) */
>>> static void gen_stfdepx(DisasContext *ctx)
>>> {
>>> @@ -1473,6 +1297,77 @@ static void gen_stfqx(DisasContext *ctx)
>>> tcg_temp_free_i64(t1);
>>> }
>>>
>>> +/* Floating-point Load/Store Instructions */
>>> +static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
>>> + bool update, bool store, bool single)
>>> +{
>>> + TCGv ea;
>>> + TCGv_i64 t0;
>>> + REQUIRE_INSNS_FLAGS(ctx, FLOAT);
>>> + REQUIRE_FPU(ctx);
>>> + if (update && ra == 0) {
>>> + gen_invalid(ctx);
>>> + return true;
>>> + }
>>> + gen_set_access_type(ctx, ACCESS_FLOAT);
>>> + t0 = tcg_temp_new_i64();
>>> + ea = do_ea_calc(ctx, ra, displ);
>>> + if (store) {
>>> + get_fpr(t0, rt);
>>> + if (single) {
>>> + gen_qemu_st32fs(ctx, t0, ea);
>>> + } else {
>>> + gen_qemu_st64_i64(ctx, t0, ea);
>>> + }
>>> + } else {
>>> + if (single) {
>>> + gen_qemu_ld32fs(ctx, t0, ea);
>>> + } else {
>>> + gen_qemu_ld64_i64(ctx, t0, ea);
>>> + }
>>> + set_fpr(rt, t0);
>>> + }
>>> + if (update) {
>>> + tcg_gen_mov_tl(cpu_gpr[rt], ea);
>>> + }
>>> + tcg_temp_free_i64(t0);
>>> + tcg_temp_free(ea);
>>> + return true;
>>> +}
>>> +
>>> +static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store,
>>> + bool single)
>>> +{
>>> + return do_lsfpsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store,
>>> + single);
>>> +}
>>> +
>>> +static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
>>> + bool store, bool single)
>>> +{
>>> + return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single);
>>> +}
>>> +
>>> +TRANS(LFS, do_lsfp_D, false, false, true)
>>> +TRANS(LFSU, do_lsfp_D, true, false, true)
>>> +TRANS(LFSX, do_lsfp_X, false, false, true)
>>> +TRANS(LFSUX, do_lsfp_X, true, false, true)
>>> +
>>> +TRANS(LFD, do_lsfp_D, false, false, false)
>>> +TRANS(LFDU, do_lsfp_D, true, false, false)
>>> +TRANS(LFDX, do_lsfp_X, false, false, false)
>>> +TRANS(LFDUX, do_lsfp_X, true, false, false)
>>> +
>>> +TRANS(STFS, do_lsfp_D, false, true, true)
>>> +TRANS(STFSU, do_lsfp_D, true, true, true)
>>> +TRANS(STFSX, do_lsfp_X, false, true, true)
>>> +TRANS(STFSUX, do_lsfp_X, true, true, true)
>>> +
>>> +TRANS(STFD, do_lsfp_D, false, true, false)
>>> +TRANS(STFDU, do_lsfp_D, true, true, false)
>>> +TRANS(STFDX, do_lsfp_X, false, true, false)
>>> +TRANS(STFDUX, do_lsfp_X, true, true, false)
>>> +
>>> #undef _GEN_FLOAT_ACB
>>> #undef GEN_FLOAT_ACB
>>> #undef _GEN_FLOAT_AB
>>> diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc
>>> index 88fab65628..4260635a12 100644
>>> --- a/target/ppc/translate/fp-ops.c.inc
>>> +++ b/target/ppc/translate/fp-ops.c.inc
>>> @@ -50,43 +50,14 @@ GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
>>> GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
>>> GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
>>>
>>> -#define GEN_LDF(name, ldop, opc, type) \
>>> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
>>> -#define GEN_LDUF(name, ldop, opc, type) \
>>> -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
>>> -#define GEN_LDUXF(name, ldop, opc, type) \
>>> -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
>>> -#define GEN_LDXF(name, ldop, opc2, opc3, type) \
>>> -GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
>>> -#define GEN_LDFS(name, ldop, op, type) \
>>> -GEN_LDF(name, ldop, op | 0x20, type) \
>>> -GEN_LDUF(name, ldop, op | 0x21, type) \
>>> -GEN_LDUXF(name, ldop, op | 0x01, type) \
>>> -GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
>>> -
>>> -GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
>>> -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
>>> GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
>>> GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
>>> GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
>>> GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
>>>
>>> -#define GEN_STF(name, stop, opc, type) \
>>> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
>>> -#define GEN_STUF(name, stop, opc, type) \
>>> -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
>>> -#define GEN_STUXF(name, stop, opc, type) \
>>> -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
>>> #define GEN_STXF(name, stop, opc2, opc3, type) \
>>> GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
>>> -#define GEN_STFS(name, stop, op, type) \
>>> -GEN_STF(name, stop, op | 0x20, type) \
>>> -GEN_STUF(name, stop, op | 0x21, type) \
>>> -GEN_STUXF(name, stop, op | 0x01, type) \
>>> -GEN_STXF(name, stop, 0x17, op | 0x00, type)
>>>
>>> -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
>>> -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
>>> GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
>>> GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
>>> GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
>>
>> This commit appears to break both MacOS 9 and OS X under qemu-system-ppc in my boot
>> tests: MacOS 9 hangs early on startup, whilst OS X now has black box artifacts on
>> some GUI widgets (see attached).
>
> It seems that we're updating the wrong register (RT instead of RA). Can you test the
> attached patch?
Thanks Matheus! I've just done a quick test with both MacOS 9 and OS X and your patch
seems to fix the issue for me, so:
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Any idea what could be happening here? Note that this series isn't bisectable - it is
>> necessary to forward-port the REQUIRE_FPU macro in order to build this commit for
>> PPC32, and I also found errors relating to undefined times_* functions during
>> bisection.
>
> REQUIRE_FPU and the times_* functions come from the DFP patch series, in which this
> series is based-on, so "target/ppc: Introduce REQUIRE_FPU" was supposed to be merged
> before this patch. Maybe something went wrong when these series were partially applied
I see, or possibly something got mixed-up in a rebase somewhere? Anyhow it shouldn't
be an issue unless any other regressions appear during testing...
ATB,
Mark.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 04/34] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (2 preceding siblings ...)
2021-10-29 20:23 ` [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-29 20:23 ` [PATCH v2 05/34] target/ppc: Move LQ and STQ to decodetree matheus.ferst
` (30 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Fernando Eckhardt Valle, lucas.castro, richard.henderson, groug,
luis.pires, Fernando Eckhardt Valle, Matheus Ferst, david
From: Fernando Eckhardt Valle <phervalle@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 11 +++++++++++
target/ppc/translate/fp-impl.c.inc | 14 ++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 72c5944a53..11e5ea81d6 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -56,6 +56,17 @@ PSTD 000001 00 0--.-- .................. \
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
+### Float-Point Load and Store Instructions
+
+PLFS 000001 10 0--.-- .................. \
+ 110000 ..... ..... ................ @PLS_D
+PLFD 000001 10 0--.-- .................. \
+ 110010 ..... ..... ................ @PLS_D
+PSTFS 000001 10 0--.-- .................. \
+ 110100 ..... ..... ................ @PLS_D
+PSTFD 000001 10 0--.-- .................. \
+ 110110 ..... ..... ................ @PLS_D
+
### Prefixed No-operation Instruction
@PNOP 000001 11 0000-- 000000000000000000 \
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 57a799db1c..d1dbb1b96b 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -1342,6 +1342,16 @@ static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store,
single);
}
+static bool do_lsfp_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
+ bool store, bool single)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return do_lsfp_D(ctx, &d, update, store, single);
+}
+
static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
bool store, bool single)
{
@@ -1352,21 +1362,25 @@ TRANS(LFS, do_lsfp_D, false, false, true)
TRANS(LFSU, do_lsfp_D, true, false, true)
TRANS(LFSX, do_lsfp_X, false, false, true)
TRANS(LFSUX, do_lsfp_X, true, false, true)
+TRANS(PLFS, do_lsfp_PLS_D, false, false, true)
TRANS(LFD, do_lsfp_D, false, false, false)
TRANS(LFDU, do_lsfp_D, true, false, false)
TRANS(LFDX, do_lsfp_X, false, false, false)
TRANS(LFDUX, do_lsfp_X, true, false, false)
+TRANS(PLFD, do_lsfp_PLS_D, false, false, false)
TRANS(STFS, do_lsfp_D, false, true, true)
TRANS(STFSU, do_lsfp_D, true, true, true)
TRANS(STFSX, do_lsfp_X, false, true, true)
TRANS(STFSUX, do_lsfp_X, true, true, true)
+TRANS(PSTFS, do_lsfp_PLS_D, false, true, true)
TRANS(STFD, do_lsfp_D, false, true, false)
TRANS(STFDU, do_lsfp_D, true, true, false)
TRANS(STFDX, do_lsfp_X, false, true, false)
TRANS(STFDUX, do_lsfp_X, true, true, false)
+TRANS(PSTFD, do_lsfp_PLS_D, false, true, false)
#undef _GEN_FLOAT_ACB
#undef GEN_FLOAT_ACB
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 05/34] target/ppc: Move LQ and STQ to decodetree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (3 preceding siblings ...)
2021-10-29 20:23 ` [PATCH v2 04/34] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-29 20:23 ` [PATCH v2 06/34] target/ppc: Implement PLQ and PSTQ matheus.ferst
` (29 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 11 ++
target/ppc/translate.c | 156 +--------------------
target/ppc/translate/fixedpoint-impl.c.inc | 97 +++++++++++++
3 files changed, 113 insertions(+), 151 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3837b799c8..9cb9fc00b8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -24,9 +24,16 @@
@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
+%dq_si 4:s12 !function=times_16
+%dq_rtp 22:4 !function=times_2
+@DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+%ds_rtp 22:4 !function=times_2
+@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
+
&DX rt d
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
@@ -153,6 +160,8 @@ LDU 111010 ..... ..... ..............01 @DS
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
+LQ 111000 ..... ..... ............ ---- @DQ_rtp
+
### Fixed-Point Store Instructions
STB 100110 ..... ..... ................ @D
@@ -175,6 +184,8 @@ STDU 111110 ..... ..... ..............01 @DS
STDX 011111 ..... ..... ..... 0010010101 - @X
STDUX 011111 ..... ..... ..... 0010110101 - @X
+STQ 111110 ..... ..... ..............10 @DS_rtp
+
### Fixed-Point Compare Instructions
CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4828456d34..659859ff5f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3327,69 +3327,6 @@ GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
-
-/* lq */
-static void gen_lq(DisasContext *ctx)
-{
- int ra, rd;
- TCGv EA, hi, lo;
-
- /* lq is a legal user mode instruction starting in ISA 2.07 */
- bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
- bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
-
- if (!legal_in_user_mode && ctx->pr) {
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
- return;
- }
-
- if (!le_is_supported && ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
- ra = rA(ctx->opcode);
- rd = rD(ctx->opcode);
- if (unlikely((rd & 1) || rd == ra)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
-
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x0F);
-
- /* Note that the low part is always in RD+1, even in LE mode. */
- lo = cpu_gpr[rd + 1];
- hi = cpu_gpr[rd];
-
- if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
- if (HAVE_ATOMIC128) {
- TCGv_i32 oi = tcg_temp_new_i32();
- if (ctx->le_mode) {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
- gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
- } else {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
- gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
- }
- tcg_temp_free_i32(oi);
- tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
- } else {
- /* Restart with exclusive lock. */
- gen_helper_exit_atomic(cpu_env);
- ctx->base.is_jmp = DISAS_NORETURN;
- }
- } else if (ctx->le_mode) {
- tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
- } else {
- tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
- }
- tcg_temp_free(EA);
-}
#endif
/*** Integer store ***/
@@ -3435,90 +3372,6 @@ GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
-
-static void gen_std(DisasContext *ctx)
-{
- int rs;
- TCGv EA;
-
- rs = rS(ctx->opcode);
- if ((ctx->opcode & 0x3) == 0x2) { /* stq */
- bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
- bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
- TCGv hi, lo;
-
- if (!(ctx->insns_flags & PPC_64BX)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- }
-
- if (!legal_in_user_mode && ctx->pr) {
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
- return;
- }
-
- if (!le_is_supported && ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
-
- if (unlikely(rs & 1)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x03);
-
- /* Note that the low part is always in RS+1, even in LE mode. */
- lo = cpu_gpr[rs + 1];
- hi = cpu_gpr[rs];
-
- if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
- if (HAVE_ATOMIC128) {
- TCGv_i32 oi = tcg_temp_new_i32();
- if (ctx->le_mode) {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128,
- ctx->mem_idx));
- gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
- } else {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128,
- ctx->mem_idx));
- gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
- }
- tcg_temp_free_i32(oi);
- } else {
- /* Restart with exclusive lock. */
- gen_helper_exit_atomic(cpu_env);
- ctx->base.is_jmp = DISAS_NORETURN;
- }
- } else if (ctx->le_mode) {
- tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
- } else {
- tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
- }
- tcg_temp_free(EA);
- } else {
- /* std / stdu */
- if (Rc(ctx->opcode)) {
- if (unlikely(rA(ctx->opcode) == 0)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x03);
- gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
- if (Rc(ctx->opcode)) {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
- }
- tcg_temp_free(EA);
- }
-}
#endif
/*** Integer load and store with byte reverse ***/
@@ -7462,6 +7315,11 @@ static int times_4(DisasContext *ctx, int x)
return x * 4;
}
+static int times_16(DisasContext *ctx, int x)
+{
+ return x * 16;
+}
+
/*
* Helpers for trans_* functions to check for specific insns flags.
* Use token pasting to ensure that we use the proper flag with the
@@ -7717,10 +7575,6 @@ GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
PPC_NONE, PPC2_ISA300),
#endif
-#if defined(TARGET_PPC64)
-GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
-GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
-#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
/* handles stfdp, lxv, stxsd, stxssp, stxv */
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 812b7ddd0a..ff35a96459 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -69,6 +69,97 @@ static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
}
+static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
+{
+#if defined(TARGET_PPC64)
+ TCGv ea;
+ TCGv_i64 low_addr_gpr, high_addr_gpr;
+ MemOp mop;
+
+ REQUIRE_INSNS_FLAGS(ctx, 64BX);
+
+ if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
+ if (ctx->pr) {
+ /* lq and stq were privileged prior to V. 2.07 */
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+ return true;
+ }
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return true;
+ }
+ }
+
+ if (!store && unlikely(a->ra == a->rt)) {
+ gen_invalid(ctx);
+ return true;
+ }
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si));
+
+ if (prefixed || !ctx->le_mode) {
+ low_addr_gpr = cpu_gpr[a->rt];
+ high_addr_gpr = cpu_gpr[a->rt + 1];
+ } else {
+ low_addr_gpr = cpu_gpr[a->rt + 1];
+ high_addr_gpr = cpu_gpr[a->rt];
+ }
+
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ if (HAVE_ATOMIC128) {
+ mop = DEF_MEMOP(MO_128);
+ TCGv_i32 oi = tcg_constant_i32(make_memop_idx(mop, ctx->mem_idx));
+ if (store) {
+ if (ctx->le_mode) {
+ gen_helper_stq_le_parallel(cpu_env, ea, low_addr_gpr,
+ high_addr_gpr, oi);
+ } else {
+ gen_helper_stq_be_parallel(cpu_env, ea, high_addr_gpr,
+ low_addr_gpr, oi);
+
+ }
+ } else {
+ if (ctx->le_mode) {
+ gen_helper_lq_le_parallel(low_addr_gpr, cpu_env, ea, oi);
+ tcg_gen_ld_i64(high_addr_gpr, cpu_env,
+ offsetof(CPUPPCState, retxh));
+ } else {
+ gen_helper_lq_be_parallel(high_addr_gpr, cpu_env, ea, oi);
+ tcg_gen_ld_i64(low_addr_gpr, cpu_env,
+ offsetof(CPUPPCState, retxh));
+ }
+ }
+ } else {
+ /* Restart with exclusive lock. */
+ gen_helper_exit_atomic(cpu_env);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ }
+ } else {
+ mop = DEF_MEMOP(MO_Q);
+ if (store) {
+ tcg_gen_qemu_st_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
+ }
+
+ gen_addr_add(ctx, ea, ea, 8);
+
+ if (store) {
+ tcg_gen_qemu_st_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
+ }
+ }
+ tcg_temp_free(ea);
+#else
+ qemu_build_not_reached();
+#endif
+
+ return true;
+}
+
/* Load Byte and Zero */
TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
@@ -110,6 +201,9 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
+/* Load Quadword */
+TRANS64(LQ, do_ldst_quad, false, false);
+
/* Store Byte */
TRANS(STB, do_ldst_D, false, true, MO_UB)
TRANS(STBX, do_ldst_X, false, true, MO_UB)
@@ -138,6 +232,9 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
+/* Store Quadword */
+TRANS64(STQ, do_ldst_quad, true, false);
+
/*
* Fixed-Point Compare Instructions
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 06/34] target/ppc: Implement PLQ and PSTQ
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (4 preceding siblings ...)
2021-10-29 20:23 ` [PATCH v2 05/34] target/ppc: Move LQ and STQ to decodetree matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-29 20:23 ` [PATCH v2 07/34] target/ppc: Implement cntlzdm matheus.ferst
` (28 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 4 ++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 11e5ea81d6..48756cd4ca 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -38,6 +38,8 @@ PLWA 000001 00 0--.-- .................. \
101001 ..... ..... ................ @PLS_D
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
+PLQ 000001 00 0--.-- .................. \
+ 111000 ..... ..... ................ @PLS_D
### Fixed-Point Store Instructions
@@ -50,6 +52,8 @@ PSTH 000001 10 0--.-- .................. \
PSTD 000001 00 0--.-- .................. \
111101 ..... ..... ................ @PLS_D
+PSTQ 000001 00 0--.-- .................. \
+ 111100 ..... ..... ................ @PLS_D
### Fixed-Point Arithmetic Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index ff35a96459..0d9c6e0996 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -160,6 +160,16 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
return true;
}
+static bool do_ldst_quad_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_ldst_quad(ctx, &d, store, true);
+}
+
/* Load Byte and Zero */
TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
@@ -203,6 +213,7 @@ TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
/* Load Quadword */
TRANS64(LQ, do_ldst_quad, false, false);
+TRANS64(PLQ, do_ldst_quad_PLS_D, false);
/* Store Byte */
TRANS(STB, do_ldst_D, false, true, MO_UB)
@@ -234,6 +245,7 @@ TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
/* Store Quadword */
TRANS64(STQ, do_ldst_quad, true, false);
+TRANS64(PSTQ, do_ldst_quad_PLS_D, true);
/*
* Fixed-Point Compare Instructions
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 07/34] target/ppc: Implement cntlzdm
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (5 preceding siblings ...)
2021-10-29 20:23 ` [PATCH v2 06/34] target/ppc: Implement PLQ and PSTQ matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-30 21:17 ` Richard Henderson
2021-10-29 20:23 ` [PATCH v2 08/34] target/ppc: Implement cnttzdm matheus.ferst
` (27 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Inline implementation of cntlzdm
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixedpoint-impl.c.inc | 36 ++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9cb9fc00b8..221cb00dd6 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -203,6 +203,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
+CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 0d9c6e0996..c9e9ae35df 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -413,3 +413,39 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+#if defined(TARGET_PPC64)
+static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
+{
+ TCGv_i64 tmp;
+ TCGLabel *l1;
+
+ tmp = tcg_temp_local_new_i64();
+ l1 = gen_new_label();
+
+ tcg_gen_and_i64(tmp, src, mask);
+ tcg_gen_clzi_i64(tmp, tmp, 64);
+
+ tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
+
+ tcg_gen_subfi_i64(tmp, 64, tmp);
+ tcg_gen_shr_i64(tmp, mask, tmp);
+ tcg_gen_ctpop_i64(tmp, tmp);
+
+ gen_set_label(l1);
+
+ tcg_gen_mov_i64(dst, tmp);
+}
+#endif
+
+static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ do_cntlzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 07/34] target/ppc: Implement cntlzdm
2021-10-29 20:23 ` [PATCH v2 07/34] target/ppc: Implement cntlzdm matheus.ferst
@ 2021-10-30 21:17 ` Richard Henderson
2021-11-01 0:16 ` David Gibson
2021-11-04 11:37 ` Matheus K. Ferst
0 siblings, 2 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 21:17 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:23 PM, matheus.ferst@eldorado.org.br wrote:
> From: Luis Pires <luis.pires@eldorado.org.br>
>
> Implement the following PowerISA v3.1 instruction:
> cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
> v2:
> - Inline implementation of cntlzdm
> ---
> target/ppc/insn32.decode | 1 +
> target/ppc/translate/fixedpoint-impl.c.inc | 36 ++++++++++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 9cb9fc00b8..221cb00dd6 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -203,6 +203,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
> ## Fixed-Point Logical Instructions
>
> CFUGED 011111 ..... ..... ..... 0011011100 - @X
> +CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
>
> ### Float-Point Load Instructions
>
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 0d9c6e0996..c9e9ae35df 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -413,3 +413,39 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
> #endif
> return true;
> }
> +
> +#if defined(TARGET_PPC64)
> +static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
> +{
> + TCGv_i64 tmp;
> + TCGLabel *l1;
> +
> + tmp = tcg_temp_local_new_i64();
> + l1 = gen_new_label();
> +
> + tcg_gen_and_i64(tmp, src, mask);
> + tcg_gen_clzi_i64(tmp, tmp, 64);
> +
> + tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
> +
> + tcg_gen_subfi_i64(tmp, 64, tmp);
> + tcg_gen_shr_i64(tmp, mask, tmp);
> + tcg_gen_ctpop_i64(tmp, tmp);
> +
> + gen_set_label(l1);
> +
> + tcg_gen_mov_i64(dst, tmp);
This works, but a form without brcond would be better (due to how poorly tcg handles basic
blocks).
How about
tcg_gen_clzi_i64(tmp, tmp, 0);
tcg_gen_xori_i64(tmp, tmp, 63);
tcg_gen_shr_i64(tmp, mask, tmp);
tcg_gen_shri_i64(tmp, tmp, 1);
tcg_gen_ctpop_i64(dst, tmp);
The middle 3 operations perform a shift between [1-64], such that we are assured of 0 for 64.
Either way,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v2 07/34] target/ppc: Implement cntlzdm
2021-10-30 21:17 ` Richard Henderson
@ 2021-11-01 0:16 ` David Gibson
2021-11-04 11:37 ` Matheus K. Ferst
1 sibling, 0 replies; 54+ messages in thread
From: David Gibson @ 2021-11-01 0:16 UTC (permalink / raw)
To: Richard Henderson
Cc: lucas.castro, qemu-devel, groug, luis.pires, qemu-ppc, matheus.ferst
[-- Attachment #1: Type: text/plain, Size: 3058 bytes --]
On Sat, Oct 30, 2021 at 02:17:07PM -0700, Richard Henderson wrote:
> On 10/29/21 1:23 PM, matheus.ferst@eldorado.org.br wrote:
> > From: Luis Pires <luis.pires@eldorado.org.br>
> >
> > Implement the following PowerISA v3.1 instruction:
> > cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
> >
> > Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> > Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
> > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> > ---
> > v2:
> > - Inline implementation of cntlzdm
> > ---
> > target/ppc/insn32.decode | 1 +
> > target/ppc/translate/fixedpoint-impl.c.inc | 36 ++++++++++++++++++++++
> > 2 files changed, 37 insertions(+)
> >
> > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> > index 9cb9fc00b8..221cb00dd6 100644
> > --- a/target/ppc/insn32.decode
> > +++ b/target/ppc/insn32.decode
> > @@ -203,6 +203,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
> > ## Fixed-Point Logical Instructions
> > CFUGED 011111 ..... ..... ..... 0011011100 - @X
> > +CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
> > ### Float-Point Load Instructions
> > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> > index 0d9c6e0996..c9e9ae35df 100644
> > --- a/target/ppc/translate/fixedpoint-impl.c.inc
> > +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> > @@ -413,3 +413,39 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
> > #endif
> > return true;
> > }
> > +
> > +#if defined(TARGET_PPC64)
> > +static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
> > +{
> > + TCGv_i64 tmp;
> > + TCGLabel *l1;
> > +
> > + tmp = tcg_temp_local_new_i64();
> > + l1 = gen_new_label();
> > +
> > + tcg_gen_and_i64(tmp, src, mask);
> > + tcg_gen_clzi_i64(tmp, tmp, 64);
> > +
> > + tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
> > +
> > + tcg_gen_subfi_i64(tmp, 64, tmp);
> > + tcg_gen_shr_i64(tmp, mask, tmp);
> > + tcg_gen_ctpop_i64(tmp, tmp);
> > +
> > + gen_set_label(l1);
> > +
> > + tcg_gen_mov_i64(dst, tmp);
>
> This works, but a form without brcond would be better (due to how poorly tcg
> handles basic blocks).
>
> How about
>
> tcg_gen_clzi_i64(tmp, tmp, 0);
>
> tcg_gen_xori_i64(tmp, tmp, 63);
> tcg_gen_shr_i64(tmp, mask, tmp);
> tcg_gen_shri_i64(tmp, tmp, 1);
>
> tcg_gen_ctpop_i64(dst, tmp);
I've applied this to ppc-for-6.2. You can make this improvement as a
followup if you want.
>
> The middle 3 operations perform a shift between [1-64], such that we are assured of 0 for 64.
>
> Either way,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v2 07/34] target/ppc: Implement cntlzdm
2021-10-30 21:17 ` Richard Henderson
2021-11-01 0:16 ` David Gibson
@ 2021-11-04 11:37 ` Matheus K. Ferst
1 sibling, 0 replies; 54+ messages in thread
From: Matheus K. Ferst @ 2021-11-04 11:37 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 30/10/2021 18:17, Richard Henderson wrote:
> On 10/29/21 1:23 PM, matheus.ferst@eldorado.org.br wrote:
>> From: Luis Pires <luis.pires@eldorado.org.br>
>>
>> Implement the following PowerISA v3.1 instruction:
>> cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
>>
>> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
>> ---
>> v2:
>> - Inline implementation of cntlzdm
>> ---
>> target/ppc/insn32.decode | 1 +
>> target/ppc/translate/fixedpoint-impl.c.inc | 36 ++++++++++++++++++++++
>> 2 files changed, 37 insertions(+)
>>
>> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
>> index 9cb9fc00b8..221cb00dd6 100644
>> --- a/target/ppc/insn32.decode
>> +++ b/target/ppc/insn32.decode
>> @@ -203,6 +203,7 @@ ADDPCIS 010011 ..... ..... ..........
>> 00010 . @DX
>> ## Fixed-Point Logical Instructions
>>
>> CFUGED 011111 ..... ..... ..... 0011011100 - @X
>> +CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
>>
>> ### Float-Point Load Instructions
>>
>> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
>> b/target/ppc/translate/fixedpoint-impl.c.inc
>> index 0d9c6e0996..c9e9ae35df 100644
>> --- a/target/ppc/translate/fixedpoint-impl.c.inc
>> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
>> @@ -413,3 +413,39 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X
>> *a)
>> #endif
>> return true;
>> }
>> +
>> +#if defined(TARGET_PPC64)
>> +static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
>> +{
>> + TCGv_i64 tmp;
>> + TCGLabel *l1;
>> +
>> + tmp = tcg_temp_local_new_i64();
>> + l1 = gen_new_label();
>> +
>> + tcg_gen_and_i64(tmp, src, mask);
>> + tcg_gen_clzi_i64(tmp, tmp, 64);
>> +
>> + tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
>> +
>> + tcg_gen_subfi_i64(tmp, 64, tmp);
>> + tcg_gen_shr_i64(tmp, mask, tmp);
>> + tcg_gen_ctpop_i64(tmp, tmp);
>> +
>> + gen_set_label(l1);
>> +
>> + tcg_gen_mov_i64(dst, tmp);
>
> This works, but a form without brcond would be better (due to how poorly
> tcg handles basic
> blocks).
>
I should've tried a little harder to get rid of this branch...
> How about
>
> tcg_gen_clzi_i64(tmp, tmp, 0);
>
> tcg_gen_xori_i64(tmp, tmp, 63);
> tcg_gen_shr_i64(tmp, mask, tmp);
> tcg_gen_shri_i64(tmp, tmp, 1);
>
> tcg_gen_ctpop_i64(dst, tmp);
>
> The middle 3 operations perform a shift between [1-64], such that we are
> assured of 0 for 64.
When src & mask == 0 we shouldn't shift mask (or shift it zero bits), so
I guess we can't have this shri. Maybe something like
tcg_gen_and_i64(t0, src, mask);
tcg_gen_clzi_i64(t0, t0, -1);
tcg_gen_setcondi_i64(TCG_COND_NE, t1, t0, -1);
tcg_gen_andi_i64(t0, t0, 63);
tcg_gen_xori_i64(t0, t0, 63);
tcg_gen_shr_i64(t0, mask, t0);
tcg_gen_shr_i64(t0, t0, t1);
tcg_gen_ctpop_i64(dst, t0);
So we still shift 63+1 bits when there are no leading zeros and shift 0
bits when it's all zeros.
>
> Either way,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 08/34] target/ppc: Implement cnttzdm
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (6 preceding siblings ...)
2021-10-29 20:23 ` [PATCH v2 07/34] target/ppc: Implement cntlzdm matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-30 21:17 ` Richard Henderson
2021-10-29 20:23 ` [PATCH v2 09/34] target/ppc: Implement pdepd instruction matheus.ferst
` (26 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cnttzdm: Count Trailing Zeros Doubleword Under Bit Mask
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Inline implementation of cnttzdm
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixedpoint-impl.c.inc | 28 ++++++++++++++++++----
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 221cb00dd6..3d692e9e6a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -204,6 +204,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
+CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index c9e9ae35df..d3dc0a474e 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -415,7 +415,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
}
#if defined(TARGET_PPC64)
-static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
+static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
{
TCGv_i64 tmp;
TCGLabel *l1;
@@ -424,12 +424,20 @@ static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
l1 = gen_new_label();
tcg_gen_and_i64(tmp, src, mask);
- tcg_gen_clzi_i64(tmp, tmp, 64);
+ if (trail) {
+ tcg_gen_ctzi_i64(tmp, tmp, 64);
+ } else {
+ tcg_gen_clzi_i64(tmp, tmp, 64);
+ }
tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
tcg_gen_subfi_i64(tmp, 64, tmp);
- tcg_gen_shr_i64(tmp, mask, tmp);
+ if (trail) {
+ tcg_gen_shl_i64(tmp, mask, tmp);
+ } else {
+ tcg_gen_shr_i64(tmp, mask, tmp);
+ }
tcg_gen_ctpop_i64(tmp, tmp);
gen_set_label(l1);
@@ -443,7 +451,19 @@ static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
#if defined(TARGET_PPC64)
- do_cntlzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+ do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], false);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], true);
#else
qemu_build_not_reached();
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 08/34] target/ppc: Implement cnttzdm
2021-10-29 20:23 ` [PATCH v2 08/34] target/ppc: Implement cnttzdm matheus.ferst
@ 2021-10-30 21:17 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 21:17 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:23 PM, matheus.ferst@eldorado.org.br wrote:
> From: Luis Pires<luis.pires@eldorado.org.br>
>
> Implement the following PowerISA v3.1 instruction:
> cnttzdm: Count Trailing Zeros Doubleword Under Bit Mask
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Luis Pires<luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - Inline implementation of cnttzdm
> ---
> target/ppc/insn32.decode | 1 +
> target/ppc/translate/fixedpoint-impl.c.inc | 28 ++++++++++++++++++----
> 2 files changed, 25 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 09/34] target/ppc: Implement pdepd instruction
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (7 preceding siblings ...)
2021-10-29 20:23 ` [PATCH v2 08/34] target/ppc: Implement cnttzdm matheus.ferst
@ 2021-10-29 20:23 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 10/34] target/ppc: Implement pextd instruction matheus.ferst
` (25 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:23 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Helper moved into ifdef TARGET_PPC64. Will be moved out when needed in
patch 13.
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 20 ++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
4 files changed, 34 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6fa3e15fe9..e3ed0d85c6 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -48,6 +48,7 @@ DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
+DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3d692e9e6a..ff70b3e863 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -205,6 +205,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
+PDEPD 011111 ..... ..... ..... 0010011100 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index eeb7781a9e..337bb7f4d3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -386,6 +386,26 @@ uint64_t helper_cfuged(uint64_t src, uint64_t mask)
return left | (right >> n);
}
+#if defined(TARGET_PPC64)
+uint64_t helper_PDEPD(uint64_t src, uint64_t mask)
+{
+ int i, o;
+ uint64_t result = 0;
+
+ if (mask == -1) {
+ return src;
+ }
+
+ for (i = 0; mask != 0; i++) {
+ o = ctz64(mask);
+ mask &= mask - 1;
+ result |= ((src >> i) & 1) << o;
+ }
+
+ return result;
+}
+#endif
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index d3dc0a474e..f0bf69fbac 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -469,3 +469,15 @@ static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_PDEPD(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_PDEPD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 10/34] target/ppc: Implement pextd instruction
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (8 preceding siblings ...)
2021-10-29 20:23 ` [PATCH v2 09/34] target/ppc: Implement pdepd instruction matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
` (24 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Helper moved into ifdef TARGET_PPC64. Will be moved out when needed in
patch 13.
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 18 ++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
4 files changed, 32 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index e3ed0d85c6..72e66c5fe8 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -49,6 +49,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index ff70b3e863..65075f0d03 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -206,6 +206,7 @@ CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
PDEPD 011111 ..... ..... ..... 0010011100 - @X
+PEXTD 011111 ..... ..... ..... 0010111100 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 337bb7f4d3..913d76be6e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -404,6 +404,24 @@ uint64_t helper_PDEPD(uint64_t src, uint64_t mask)
return result;
}
+
+uint64_t helper_PEXTD(uint64_t src, uint64_t mask)
+{
+ int i, o;
+ uint64_t result = 0;
+
+ if (mask == -1) {
+ return src;
+ }
+
+ for (o = 0; mask != 0; o++) {
+ i = ctz64(mask);
+ mask &= mask - 1;
+ result |= ((src >> i) & 1) << o;
+ }
+
+ return result;
+}
#endif
/*****************************************************************************/
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index f0bf69fbac..220b099fcd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -481,3 +481,15 @@ static bool trans_PDEPD(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_PEXTD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (9 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 10/34] target/ppc: Implement pextd instruction matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-11-01 0:20 ` David Gibson
2021-10-29 20:24 ` [PATCH v2 12/34] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
` (23 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
There's no reason to keep vector-impl.c.inc separate from
vmx-impl.c.inc. Additionally, let GVec handle the multiple calls to
helper_cfuged for us.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- vecop_list removed
---
target/ppc/helper.h | 2 +-
target/ppc/int_helper.c | 2 +-
target/ppc/translate.c | 1 -
target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
target/ppc/translate/vector-impl.c.inc | 48 ----------------------
target/ppc/translate/vmx-impl.c.inc | 16 ++++++++
6 files changed, 19 insertions(+), 52 deletions(-)
delete mode 100644 target/ppc/translate/vector-impl.c.inc
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 72e66c5fe8..401575b935 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,7 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
-DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 913d76be6e..f03c864e48 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -324,7 +324,7 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
-uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+uint64_t helper_CFUGED(uint64_t src, uint64_t mask)
{
/*
* Instead of processing the mask bit-by-bit from the most significant to
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 659859ff5f..fc9d35a7a8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7407,7 +7407,6 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.c.inc"
-#include "translate/vector-impl.c.inc"
#include "translate/dfp-impl.c.inc"
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 220b099fcd..fa519c2d3e 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -407,7 +407,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
#if defined(TARGET_PPC64)
- gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+ gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
deleted file mode 100644
index 197e903337..0000000000
--- a/target/ppc/translate/vector-impl.c.inc
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Power ISA decode for Vector Facility instructions
- *
- * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
-{
- TCGv_i64 tgt, src, mask;
-
- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
- REQUIRE_VECTOR(ctx);
-
- tgt = tcg_temp_new_i64();
- src = tcg_temp_new_i64();
- mask = tcg_temp_new_i64();
-
- /* centrifuge lower double word */
- get_cpu_vsrl(src, a->vra + 32);
- get_cpu_vsrl(mask, a->vrb + 32);
- gen_helper_cfuged(tgt, src, mask);
- set_cpu_vsrl(a->vrt + 32, tgt);
-
- /* centrifuge higher double word */
- get_cpu_vsrh(src, a->vra + 32);
- get_cpu_vsrh(mask, a->vrb + 32);
- gen_helper_cfuged(tgt, src, mask);
- set_cpu_vsrh(a->vrt + 32, tgt);
-
- tcg_temp_free_i64(tgt);
- tcg_temp_free_i64(src);
- tcg_temp_free_i64(mask);
-
- return true;
-}
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 92b9527aff..e36c66589c 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1559,6 +1559,22 @@ GEN_VXFORM3(vpermxor, 22, 0xFF)
GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
+static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_CFUGED,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc
2021-10-29 20:24 ` [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
@ 2021-11-01 0:20 ` David Gibson
0 siblings, 0 replies; 54+ messages in thread
From: David Gibson @ 2021-11-01 0:20 UTC (permalink / raw)
To: matheus.ferst
Cc: lucas.castro, richard.henderson, qemu-devel, groug, luis.pires, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 6307 bytes --]
On Fri, Oct 29, 2021 at 05:24:01PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> There's no reason to keep vector-impl.c.inc separate from
> vmx-impl.c.inc. Additionally, let GVec handle the multiple calls to
> helper_cfuged for us.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
I'm afraid this doesn't apply clean to ppc-for-6.2 any more, though
I'm not sure why.
> ---
> v2:
> - vecop_list removed
> ---
> target/ppc/helper.h | 2 +-
> target/ppc/int_helper.c | 2 +-
> target/ppc/translate.c | 1 -
> target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
> target/ppc/translate/vector-impl.c.inc | 48 ----------------------
> target/ppc/translate/vmx-impl.c.inc | 16 ++++++++
> 6 files changed, 19 insertions(+), 52 deletions(-)
> delete mode 100644 target/ppc/translate/vector-impl.c.inc
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 72e66c5fe8..401575b935 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -46,7 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
> DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
> DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> DEF_HELPER_3(sraw, tl, env, tl, tl)
> -DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> #if defined(TARGET_PPC64)
> DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 913d76be6e..f03c864e48 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -324,7 +324,7 @@ target_ulong helper_popcntb(target_ulong val)
> }
> #endif
>
> -uint64_t helper_cfuged(uint64_t src, uint64_t mask)
> +uint64_t helper_CFUGED(uint64_t src, uint64_t mask)
> {
> /*
> * Instead of processing the mask bit-by-bit from the most significant to
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 659859ff5f..fc9d35a7a8 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7407,7 +7407,6 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
> #include "translate/vmx-impl.c.inc"
>
> #include "translate/vsx-impl.c.inc"
> -#include "translate/vector-impl.c.inc"
>
> #include "translate/dfp-impl.c.inc"
>
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 220b099fcd..fa519c2d3e 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -407,7 +407,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
> REQUIRE_64BIT(ctx);
> REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> #if defined(TARGET_PPC64)
> - gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
> + gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
> #else
> qemu_build_not_reached();
> #endif
> diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
> deleted file mode 100644
> index 197e903337..0000000000
> --- a/target/ppc/translate/vector-impl.c.inc
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -/*
> - * Power ISA decode for Vector Facility instructions
> - *
> - * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> - *
> - * This library is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU Lesser General Public
> - * License as published by the Free Software Foundation; either
> - * version 2.1 of the License, or (at your option) any later version.
> - *
> - * This library is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> - * Lesser General Public License for more details.
> - *
> - * You should have received a copy of the GNU Lesser General Public
> - * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> - */
> -
> -static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
> -{
> - TCGv_i64 tgt, src, mask;
> -
> - REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> - REQUIRE_VECTOR(ctx);
> -
> - tgt = tcg_temp_new_i64();
> - src = tcg_temp_new_i64();
> - mask = tcg_temp_new_i64();
> -
> - /* centrifuge lower double word */
> - get_cpu_vsrl(src, a->vra + 32);
> - get_cpu_vsrl(mask, a->vrb + 32);
> - gen_helper_cfuged(tgt, src, mask);
> - set_cpu_vsrl(a->vrt + 32, tgt);
> -
> - /* centrifuge higher double word */
> - get_cpu_vsrh(src, a->vra + 32);
> - get_cpu_vsrh(mask, a->vrb + 32);
> - gen_helper_cfuged(tgt, src, mask);
> - set_cpu_vsrh(a->vrt + 32, tgt);
> -
> - tcg_temp_free_i64(tgt);
> - tcg_temp_free_i64(src);
> - tcg_temp_free_i64(mask);
> -
> - return true;
> -}
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index 92b9527aff..e36c66589c 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -1559,6 +1559,22 @@ GEN_VXFORM3(vpermxor, 22, 0xFF)
> GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
> vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
>
> +static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
> +{
> + static const GVecGen3 g = {
> + .fni8 = gen_helper_CFUGED,
> + .vece = MO_64,
> + };
> +
> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> + REQUIRE_VECTOR(ctx);
> +
> + tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
> + avr_full_offset(a->vrb), 16, 16, &g);
> +
> + return true;
> +}
> +
> #undef GEN_VR_LDX
> #undef GEN_VR_STX
> #undef GEN_VR_LVE
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 12/34] target/ppc: Implement vclzdm/vctzdm instructions
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (10 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 21:34 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 13/34] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
` (22 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
The signature of do_cntzdm is changed to allow reuse as GVecGen3i.fni8.
The method is also moved out of #ifdef TARGET_PPC64, as PowerISA doesn't
say vclzdm and vctzdm are 64-bit only.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Inline implementation of cntlzdm/cnttzdm
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/fixedpoint-impl.c.inc | 4 +--
target/ppc/translate/vmx-impl.c.inc | 32 ++++++++++++++++++++++
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 65075f0d03..6ce06b231d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -334,3 +334,5 @@ DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
+VCLZDM 000100 ..... ..... ..... 11110000100 @VX
+VCTZDM 000100 ..... ..... ..... 11111000100 @VX
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index fa519c2d3e..e093562e2a 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -414,8 +414,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
return true;
}
-#if defined(TARGET_PPC64)
-static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
+static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
{
TCGv_i64 tmp;
TCGLabel *l1;
@@ -444,7 +443,6 @@ static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
tcg_gen_mov_i64(dst, tmp);
}
-#endif
static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
{
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index e36c66589c..6da8a9123f 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1575,6 +1575,38 @@ static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3i g = {
+ .fni8 = do_cntzdm,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, false, &g);
+
+ return true;
+}
+
+static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3i g = {
+ .fni8 = do_cntzdm,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, true, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 12/34] target/ppc: Implement vclzdm/vctzdm instructions
2021-10-29 20:24 ` [PATCH v2 12/34] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
@ 2021-10-30 21:34 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 21:34 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> The signature of do_cntzdm is changed to allow reuse as GVecGen3i.fni8.
> The method is also moved out of #ifdef TARGET_PPC64, as PowerISA doesn't
> say vclzdm and vctzdm are 64-bit only.
>
> Signed-off-by: Luis Pires<luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - Inline implementation of cntlzdm/cnttzdm
> ---
> target/ppc/insn32.decode | 2 ++
> target/ppc/translate/fixedpoint-impl.c.inc | 4 +--
> target/ppc/translate/vmx-impl.c.inc | 32 ++++++++++++++++++++++
> 3 files changed, 35 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 13/34] target/ppc: Implement vpdepd/vpextd instruction
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (11 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 12/34] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 14/34] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
` (21 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
pdepd and pextd helpers are moved out of #ifdef (TARGET_PPC64) to allow
them to be reused as GVecGen3.fni8.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/int_helper.c | 2 --
target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++++++++++
4 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 401575b935..0e99f8095c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -47,9 +47,9 @@ DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 6ce06b231d..4666c06f55 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -336,3 +336,5 @@ DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
VCLZDM 000100 ..... ..... ..... 11110000100 @VX
VCTZDM 000100 ..... ..... ..... 11111000100 @VX
+VPDEPD 000100 ..... ..... ..... 10111001101 @VX
+VPEXTD 000100 ..... ..... ..... 10110001101 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index f03c864e48..42541736f1 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -386,7 +386,6 @@ uint64_t helper_CFUGED(uint64_t src, uint64_t mask)
return left | (right >> n);
}
-#if defined(TARGET_PPC64)
uint64_t helper_PDEPD(uint64_t src, uint64_t mask)
{
int i, o;
@@ -422,7 +421,6 @@ uint64_t helper_PEXTD(uint64_t src, uint64_t mask)
return result;
}
-#endif
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6da8a9123f..cddb3848ab 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1607,6 +1607,38 @@ static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VPDEPD(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_PDEPD,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
+static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_PEXTD,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 14/34] target/ppc: Implement vsldbi/vsrdbi instructions
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (12 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 13/34] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 21:42 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 15/34] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
` (20 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- tcg_gen_extract2_i64 instead of shifts and or
---
target/ppc/insn32.decode | 8 ++++
target/ppc/translate/vmx-impl.c.inc | 66 +++++++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 4666c06f55..257b11113d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -38,6 +38,9 @@
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+&VN vrt vra vrb sh
+@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
+
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
@@ -338,3 +341,8 @@ VCLZDM 000100 ..... ..... ..... 11110000100 @VX
VCTZDM 000100 ..... ..... ..... 11111000100 @VX
VPDEPD 000100 ..... ..... ..... 10111001101 @VX
VPEXTD 000100 ..... ..... ..... 10110001101 @VX
+
+## Vector Permute and Formatting Instruction
+
+VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
+VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index cddb3848ab..6edffd5637 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1257,6 +1257,72 @@ static void gen_vsldoi(DisasContext *ctx)
tcg_temp_free_i32(sh);
}
+static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
+{
+ TCGv_i64 t0, t1, t2;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ get_avr64(t0, a->vra, true);
+ get_avr64(t1, a->vra, false);
+
+ if (a->sh != 0) {
+ t2 = tcg_temp_new_i64();
+
+ get_avr64(t2, a->vrb, true);
+
+ tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
+ tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
+
+ tcg_temp_free_i64(t2);
+ }
+
+ set_avr64(a->vrt, t0, true);
+ set_avr64(a->vrt, t1, false);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
+static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
+{
+ TCGv_i64 t2, t1, t0;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ get_avr64(t0, a->vrb, false);
+ get_avr64(t1, a->vrb, true);
+
+ if (a->sh != 0) {
+ t2 = tcg_temp_new_i64();
+
+ get_avr64(t2, a->vra, false);
+
+ tcg_gen_extract2_i64(t0, t0, t1, a->sh);
+ tcg_gen_extract2_i64(t1, t1, t2, a->sh);
+
+ tcg_temp_free_i64(t2);
+ }
+
+ set_avr64(a->vrt, t0, false);
+ set_avr64(a->vrt, t1, true);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 14/34] target/ppc: Implement vsldbi/vsrdbi instructions
2021-10-29 20:24 ` [PATCH v2 14/34] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
@ 2021-10-30 21:42 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 21:42 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - tcg_gen_extract2_i64 instead of shifts and or
> ---
> target/ppc/insn32.decode | 8 ++++
> target/ppc/translate/vmx-impl.c.inc | 66 +++++++++++++++++++++++++++++
> 2 files changed, 74 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 15/34] target/ppc: Implement Vector Insert from GPR using GPR index insns
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (13 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 14/34] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 22:26 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
` (19 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsblx: Vector Insert Byte from GPR using GPR-specified Left-Index
vinshlx: Vector Insert Halfword from GPR using GPR-specified Left-Index
vinswlx: Vector Insert Word from GPR using GPR-specified Left-Index
vinsdlx: Vector Insert Doubleword from GPR using GPR-specified
Left-Index
vinsbrx: Vector Insert Byte from GPR using GPR-specified Right-Index
vinshrx: Vector Insert Halfword from GPR using GPR-specified
Right-Index
vinswrx: Vector Insert Word from GPR using GPR-specified Right-Index
vinsdrx: Vector Insert Doubleword from GPR using GPR-specified
Right-Index
The helpers and do_vinsx receive i64 to allow code sharing with the
future implementation of Vector Insert from VSR using GPR Index.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- #ifdef TARGET_PPC64 removed from translation code
- ELEM_ADDR without VsrB
- memcpy instead of misaligned store
- Simplified log message
---
target/ppc/helper.h | 4 +++
target/ppc/insn32.decode | 9 ++++++
target/ppc/int_helper.c | 29 +++++++++++++++++
target/ppc/translate/vmx-impl.c.inc | 50 +++++++++++++++++++++++++++++
4 files changed, 92 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0e99f8095c..80f88ce78b 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -228,6 +228,10 @@ DEF_HELPER_3(vinsertb, void, avr, avr, i32)
DEF_HELPER_3(vinserth, void, avr, avr, i32)
DEF_HELPER_3(vinsertw, void, avr, avr, i32)
DEF_HELPER_3(vinsertd, void, avr, avr, i32)
+DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl)
+DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl)
+DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl)
+DEF_HELPER_4(VINSDLX, void, env, avr, i64, tl)
DEF_HELPER_2(vextsb2w, void, avr, avr)
DEF_HELPER_2(vextsh2w, void, avr, avr)
DEF_HELPER_2(vextsb2d, void, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 257b11113d..b794424496 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -344,5 +344,14 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
+VINSBLX 000100 ..... ..... ..... 01000001111 @VX
+VINSBRX 000100 ..... ..... ..... 01100001111 @VX
+VINSHLX 000100 ..... ..... ..... 01001001111 @VX
+VINSHRX 000100 ..... ..... ..... 01101001111 @VX
+VINSWLX 000100 ..... ..... ..... 01010001111 @VX
+VINSWRX 000100 ..... ..... ..... 01110001111 @VX
+VINSDLX 000100 ..... ..... ..... 01011001111 @VX
+VINSDRX 000100 ..... ..... ..... 01111001111 @VX
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 42541736f1..29715d3e19 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1632,6 +1632,35 @@ VINSERT(h, u16)
VINSERT(w, u32)
VINSERT(d, u64)
#undef VINSERT
+
+#if defined(HOST_WORDS_BIGENDIAN)
+#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[IDX])
+#else
+#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[15 - (IDX)] - (SIZE) + 1)
+#endif
+
+#define VINSX(SUFFIX, TYPE) \
+void glue(glue(helper_VINS, SUFFIX), LX)(CPUPPCState *env, ppc_avr_t *t, \
+ uint64_t val, target_ulong index) \
+{ \
+ const int maxidx = ARRAY_SIZE(t->u8) - sizeof(TYPE); \
+ target_long idx = index; \
+ \
+ if (idx < 0 || idx > maxidx) { \
+ idx = idx < 0 ? sizeof(TYPE) - idx : idx; \
+ qemu_log_mask(LOG_GUEST_ERROR, \
+ "Invalid index for Vector Insert Element after 0x" TARGET_FMT_lx \
+ ", RA = " TARGET_FMT_ld " > %d\n", env->nip, idx, maxidx); \
+ } else { \
+ memcpy(ELEM_ADDR(t, idx, sizeof(TYPE)), &val, sizeof(TYPE)); \
+ } \
+}
+VINSX(B, uint8_t)
+VINSX(H, uint16_t)
+VINSX(W, uint32_t)
+VINSX(D, uint64_t)
+#undef ELEM_ADDR
+#undef VINSX
#if defined(HOST_WORDS_BIGENDIAN)
#define VEXTRACT(suffix, element) \
void helper_vextract##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6edffd5637..21af60c616 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1238,6 +1238,56 @@ GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
vinsertw, PPC_NONE, PPC2_ISA300);
+static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
+ TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ TCGv_ptr t;
+ TCGv idx;
+
+ t = gen_avr_ptr(vrt);
+ idx = tcg_temp_new();
+
+ tcg_gen_andi_tl(idx, ra, 0xF);
+ if (right) {
+ tcg_gen_subfi_tl(idx, 16 - size, idx);
+ }
+
+ gen_helper(cpu_env, t, rb, idx);
+
+ tcg_temp_free_ptr(t);
+ tcg_temp_free(idx);
+
+ return true;
+}
+
+static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ val = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
+
+ ok = do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
+TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
+TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
+TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
+TRANS(VINSDLX, do_vinsx_VX, 8, false, gen_helper_VINSDLX)
+
+TRANS(VINSBRX, do_vinsx_VX, 1, true, gen_helper_VINSBLX)
+TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
+TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
+TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 15/34] target/ppc: Implement Vector Insert from GPR using GPR index insns
2021-10-29 20:24 ` [PATCH v2 15/34] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
@ 2021-10-30 22:26 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 22:26 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> + memcpy(ELEM_ADDR(t, idx, sizeof(TYPE)), &val, sizeof(TYPE)); \
You need to copy val to TYPE before you can memcpy out of it, otherwise failure for
big-endian host.
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using Immediate insns
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (14 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 15/34] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 22:27 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 17/34] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
` (18 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsw: Vector Insert Word from GPR using immediate-specified index
vinsd: Vector Insert Doubleword from GPR using immediate-specified
index
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- #ifdef TARGET_PPC64 removed from translation code
- Comments about real hardware behavior
---
target/ppc/insn32.decode | 6 +++++
target/ppc/translate/vmx-impl.c.inc | 37 +++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b794424496..e1f76aac34 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -44,6 +44,9 @@
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+&VX_uim4 vrt uim vrb
+@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -353,5 +356,8 @@ VINSWRX 000100 ..... ..... ..... 01110001111 @VX
VINSDLX 000100 ..... ..... ..... 01011001111 @VX
VINSDRX 000100 ..... ..... ..... 01111001111 @VX
+VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
+VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 21af60c616..9642cfa037 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1278,6 +1278,40 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
return ok;
}
+static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ if (a->uim > (16 - size)) {
+ /*
+ * PowerISA v3.1 says that the resulting value is undefined in this
+ * case, so just log a guest error and leave VRT unchanged. The
+ * real hardware would do a partial insert, e.g. if VRT is zeroed and
+ * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
+ * VRT = 0x0000...00001234, but we don't bother to reproduce this
+ * behavior as software shouldn't rely on it.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
+ " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
+ 16 - size);
+ return true;
+ }
+
+ val = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
+
+ ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
+ gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
@@ -1288,6 +1322,9 @@ TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
+TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
+TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using Immediate insns
2021-10-29 20:24 ` [PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
@ 2021-10-30 22:27 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 22:27 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> Implements the following PowerISA v3.1 instructions:
> vinsw: Vector Insert Word from GPR using immediate-specified index
> vinsd: Vector Insert Doubleword from GPR using immediate-specified
> index
>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - #ifdef TARGET_PPC64 removed from translation code
> - Comments about real hardware behavior
> ---
> target/ppc/insn32.decode | 6 +++++
> target/ppc/translate/vmx-impl.c.inc | 37 +++++++++++++++++++++++++++++
> 2 files changed, 43 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 17/34] target/ppc: Implement Vector Insert from VSR using GPR index insns
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (15 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 18/34] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
` (17 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsbvlx: Vector Insert Byte from VSR using GPR-specified Left-Index
vinshvlx: Vector Insert Halfword from VSR using GPR-specified
Left-Index
vinswvlx: Vector Insert Word from VSR using GPR-specified Left-Index
vinsbvrx: Vector Insert Byte from VSR using GPR-specified Right-Index
vinshvrx: Vector Insert Halfword from VSR using GPR-specified
Right-Index
vinswvrx: Vector Insert Word from VSR using GPR-specified Right-Index
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 7 +++++++
target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e1f76aac34..de410abf7d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -359,5 +359,12 @@ VINSDRX 000100 ..... ..... ..... 01111001111 @VX
VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
+VINSBVLX 000100 ..... ..... ..... 00000001111 @VX
+VINSBVRX 000100 ..... ..... ..... 00100001111 @VX
+VINSHVLX 000100 ..... ..... ..... 00001001111 @VX
+VINSHVRX 000100 ..... ..... ..... 00101001111 @VX
+VINSWVLX 000100 ..... ..... ..... 00010001111 @VX
+VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 9642cfa037..46d6890242 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1260,6 +1260,20 @@ static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
return true;
}
+static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
+ int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ val = tcg_temp_new_i64();
+ get_avr64(val, vrb, true);
+ ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
@@ -1278,6 +1292,16 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
return ok;
}
+static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
+ gen_helper);
+}
+
static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
@@ -1325,6 +1349,14 @@ TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
+TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
+TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
+TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
+
+TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
+TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
+TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 18/34] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (16 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 17/34] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 19/34] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
` (16 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 4 ----
target/ppc/insn32.decode | 5 +++++
target/ppc/int_helper.c | 21 -------------------
target/ppc/translate/vmx-impl.c.inc | 32 ++++++++++++++++++++---------
target/ppc/translate/vmx-ops.c.inc | 10 +++------
5 files changed, 30 insertions(+), 42 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 80f88ce78b..356495f392 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -224,10 +224,6 @@ DEF_HELPER_3(vextractub, void, avr, avr, i32)
DEF_HELPER_3(vextractuh, void, avr, avr, i32)
DEF_HELPER_3(vextractuw, void, avr, avr, i32)
DEF_HELPER_3(vextractd, void, avr, avr, i32)
-DEF_HELPER_3(vinsertb, void, avr, avr, i32)
-DEF_HELPER_3(vinserth, void, avr, avr, i32)
-DEF_HELPER_3(vinsertw, void, avr, avr, i32)
-DEF_HELPER_3(vinsertd, void, avr, avr, i32)
DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index de410abf7d..2eb7fb4e92 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -347,6 +347,11 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
+VINSERTB 000100 ..... - .... ..... 01100001101 @VX_uim4
+VINSERTH 000100 ..... - .... ..... 01101001101 @VX_uim4
+VINSERTW 000100 ..... - .... ..... 01110001101 @VX_uim4
+VINSERTD 000100 ..... - .... ..... 01111001101 @VX_uim4
+
VINSBLX 000100 ..... ..... ..... 01000001111 @VX
VINSBRX 000100 ..... ..... ..... 01100001111 @VX
VINSHLX 000100 ..... ..... ..... 01001001111 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 29715d3e19..713a43e6e3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1612,27 +1612,6 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
#endif
}
-#if defined(HOST_WORDS_BIGENDIAN)
-#define VINSERT(suffix, element) \
- void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
- { \
- memmove(&r->u8[index], &b->u8[8 - sizeof(r->element[0])], \
- sizeof(r->element[0])); \
- }
-#else
-#define VINSERT(suffix, element) \
- void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
- { \
- uint32_t d = (16 - index) - sizeof(r->element[0]); \
- memmove(&r->u8[d], &b->u8[8], sizeof(r->element[0])); \
- }
-#endif
-VINSERT(b, u8)
-VINSERT(h, u16)
-VINSERT(w, u32)
-VINSERT(d, u64)
-#undef VINSERT
-
#if defined(HOST_WORDS_BIGENDIAN)
#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[IDX])
#else
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 46d6890242..6fd18690df 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1217,10 +1217,6 @@ GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
-GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
-GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
-GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
-GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
@@ -1231,12 +1227,6 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
vextractuh, PPC_NONE, PPC2_ISA300);
GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
vextractuw, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
- vinsertb, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
- vinserth, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
- vinsertw, PPC_NONE, PPC2_ISA300);
static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
@@ -1336,6 +1326,23 @@ static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
return ok;
}
+static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VECTOR(ctx);
+
+ if (a->uim > (16 - size)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
+ " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
+ 16 - size);
+ return true;
+ }
+
+ return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
+ gen_helper);
+}
+
TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
@@ -1357,6 +1364,11 @@ TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
+TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
+TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
+TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
+TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index f3f4855111..25ee715b43 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -225,13 +225,9 @@ GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000,
GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000,
PPC_ALTIVEC),
GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000),
-GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
+GEN_VXFORM(vspltisb, 6, 12),
+GEN_VXFORM(vspltish, 6, 13),
+GEN_VXFORM(vspltisw, 6, 14),
GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 19/34] target/ppc: Implement Vector Extract Double to VSR using GPR index insns
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (17 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 18/34] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 22:29 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 20/34] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
` (15 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vextdubvlx: Vector Extract Double Unsigned Byte to VSR using
GPR-specified Left-Index
vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using
GPR-specified Left-Index
vextduwvlx: Vector Extract Double Unsigned Word to VSR using
GPR-specified Left-Index
vextddvlx: Vector Extract Double Doubleword to VSR using
GPR-specified Left-Index
vextdubvrx: Vector Extract Double Unsigned Byte to VSR using
GPR-specified Right-Index
vextduhvrx: Vector Extract Double Unsigned Halfword to VSR using
GPR-specified Right-Index
vextduwvrx: Vector Extract Double Unsigned Word to VSR using
GPR-specified Right-Index
vextddvrx: Vector Extract Double Doubleword to VSR using
GPR-specified Right-Index
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Simplified helper
---
target/ppc/helper.h | 4 +++
target/ppc/insn32.decode | 12 +++++++++
target/ppc/int_helper.c | 39 +++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.c.inc | 37 +++++++++++++++++++++++++++
4 files changed, 92 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 356495f392..7ff1d055c4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -334,6 +334,10 @@ DEF_HELPER_2(vextuwlx, tl, tl, avr)
DEF_HELPER_2(vextubrx, tl, tl, avr)
DEF_HELPER_2(vextuhrx, tl, tl, avr)
DEF_HELPER_2(vextuwrx, tl, tl, avr)
+DEF_HELPER_5(VEXTDUBVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUHVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUWVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDDVLX, void, env, avr, avr, avr, tl)
DEF_HELPER_2(vsbox, void, avr, avr)
DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2eb7fb4e92..e438177b32 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -38,6 +38,9 @@
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+&VA vrt vra vrb rc
+@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
+
&VN vrt vra vrb sh
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
@@ -347,6 +350,15 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
+VEXTDUBVLX 000100 ..... ..... ..... ..... 011000 @VA
+VEXTDUBVRX 000100 ..... ..... ..... ..... 011001 @VA
+VEXTDUHVLX 000100 ..... ..... ..... ..... 011010 @VA
+VEXTDUHVRX 000100 ..... ..... ..... ..... 011011 @VA
+VEXTDUWVLX 000100 ..... ..... ..... ..... 011100 @VA
+VEXTDUWVRX 000100 ..... ..... ..... ..... 011101 @VA
+VEXTDDVLX 000100 ..... ..... ..... ..... 011110 @VA
+VEXTDDVRX 000100 ..... ..... ..... ..... 011111 @VA
+
VINSERTB 000100 ..... - .... ..... 01100001101 @VX_uim4
VINSERTH 000100 ..... - .... ..... 01101001101 @VX_uim4
VINSERTW 000100 ..... - .... ..... 01110001101 @VX_uim4
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 713a43e6e3..6d475e1687 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1641,6 +1641,45 @@ VINSX(D, uint64_t)
#undef ELEM_ADDR
#undef VINSX
#if defined(HOST_WORDS_BIGENDIAN)
+#define VEXTDVLX(NAME, SIZE) \
+void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ target_ulong index) \
+{ \
+ const target_long idx = index; \
+ ppc_avr_t tmp[2] = { *a, *b }; \
+ memset(t, 0, sizeof(*t)); \
+ if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \
+ memcpy(&t->u8[ARRAY_SIZE(t->u8) / 2 - SIZE], (void *)tmp + idx, SIZE); \
+ } else { \
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for " #NAME " after 0x" \
+ TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", \
+ env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \
+ } \
+}
+#else
+#define VEXTDVLX(NAME, SIZE) \
+void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ target_ulong index) \
+{ \
+ const target_long idx = index; \
+ ppc_avr_t tmp[2] = { *b, *a }; \
+ memset(t, 0, sizeof(*t)); \
+ if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \
+ memcpy(&t->u8[ARRAY_SIZE(t->u8) / 2], \
+ (void *)tmp + sizeof(tmp) - SIZE - idx, SIZE); \
+ } else { \
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for " #NAME " after 0x" \
+ TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", \
+ env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \
+ } \
+}
+#endif
+VEXTDVLX(VEXTDUBVLX, 1)
+VEXTDVLX(VEXTDUHVLX, 2)
+VEXTDVLX(VEXTDUWVLX, 4)
+VEXTDVLX(VEXTDDVLX, 8)
+#undef VEXTDVLX
+#if defined(HOST_WORDS_BIGENDIAN)
#define VEXTRACT(suffix, element) \
void helper_vextract##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
{ \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6fd18690df..8eb8d3a067 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1228,6 +1228,43 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
vextractuw, PPC_NONE, PPC2_ISA300);
+static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
+{
+ TCGv_ptr vrt, vra, vrb;
+ TCGv rc;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ vrt = gen_avr_ptr(a->vrt);
+ vra = gen_avr_ptr(a->vra);
+ vrb = gen_avr_ptr(a->vrb);
+ rc = tcg_temp_new();
+
+ tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
+ if (right) {
+ tcg_gen_subfi_tl(rc, 32 - size, rc);
+ }
+ gen_helper(cpu_env, vrt, vra, vrb, rc);
+
+ tcg_temp_free_ptr(vrt);
+ tcg_temp_free_ptr(vra);
+ tcg_temp_free_ptr(vrb);
+ tcg_temp_free(rc);
+ return true;
+}
+
+TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
+TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
+TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
+TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
+
+TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
+TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
+TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
+TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
+
static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 19/34] target/ppc: Implement Vector Extract Double to VSR using GPR index insns
2021-10-29 20:24 ` [PATCH v2 19/34] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
@ 2021-10-30 22:29 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 22:29 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> Implement the following PowerISA v3.1 instructions:
> vextdubvlx: Vector Extract Double Unsigned Byte to VSR using
> GPR-specified Left-Index
> vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using
> GPR-specified Left-Index
> vextduwvlx: Vector Extract Double Unsigned Word to VSR using
> GPR-specified Left-Index
> vextddvlx: Vector Extract Double Doubleword to VSR using
> GPR-specified Left-Index
> vextdubvrx: Vector Extract Double Unsigned Byte to VSR using
> GPR-specified Right-Index
> vextduhvrx: Vector Extract Double Unsigned Halfword to VSR using
> GPR-specified Right-Index
> vextduwvrx: Vector Extract Double Unsigned Word to VSR using
> GPR-specified Right-Index
> vextddvrx: Vector Extract Double Doubleword to VSR using
> GPR-specified Right-Index
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Luis Pires<luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - Simplified helper
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 20/34] target/ppc: Introduce REQUIRE_VSX macro
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (18 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 19/34] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 21/34] target/ppc: receive high/low as argument in get/set_cpu_vsr matheus.ferst
` (14 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires,
Bruno Larsen (billionai),
Matheus Ferst, david
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Introduce the macro to centralize checking if the VSX facility is
enabled and handle it correctly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index fc9d35a7a8..e88b613093 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7354,6 +7354,14 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#define REQUIRE_VSX(CTX) \
+ do { \
+ if (unlikely(!(CTX)->vsx_enabled)) { \
+ gen_exception((CTX), POWERPC_EXCP_VSXU); \
+ return true; \
+ } \
+ } while (0)
+
#define REQUIRE_FPU(ctx) \
do { \
if (unlikely(!(ctx)->fpu_enabled)) { \
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 21/34] target/ppc: receive high/low as argument in get/set_cpu_vsr
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (19 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 20/34] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 22:31 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 22/34] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
` (13 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Changes get_cpu_vsr to receive a new argument indicating whether the
high or low part of the register is being accessed. This change improves
consistency between the interfaces used to access Vector and VSX
registers and helps to handle endianness in some cases.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
New in v2. Will be used in the next patch to address the problems in the
v1 implementation of stxv/lxv.
---
target/ppc/translate/vsx-impl.c.inc | 317 +++++++++++++---------------
1 file changed, 146 insertions(+), 171 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 57a7f73bba..d923c6a090 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1,23 +1,13 @@
/*** VSX extension ***/
-static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
+static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high)
{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, true));
+ tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, high));
}
-static inline void get_cpu_vsrl(TCGv_i64 dst, int n)
+static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high)
{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, false));
-}
-
-static inline void set_cpu_vsrh(int n, TCGv_i64 src)
-{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, true));
-}
-
-static inline void set_cpu_vsrl(int n, TCGv_i64 src)
-{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false));
+ tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, high));
}
static inline TCGv_ptr gen_vsr_ptr(int reg)
@@ -41,7 +31,7 @@ static void gen_##name(DisasContext *ctx) \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
gen_qemu_##operation(ctx, t0, EA); \
- set_cpu_vsrh(xT(ctx->opcode), t0); \
+ set_cpu_vsr(xT(ctx->opcode), t0, true); \
/* NOTE: cpu_vsrl is undefined */ \
tcg_temp_free(EA); \
tcg_temp_free_i64(t0); \
@@ -67,10 +57,10 @@ static void gen_lxvd2x(DisasContext *ctx)
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_gen_addi_tl(EA, EA, 8);
gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrl(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, false);
tcg_temp_free(EA);
tcg_temp_free_i64(t0);
}
@@ -109,8 +99,8 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_gen_addi_tl(EA, EA, 8);
tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
}
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -233,8 +223,8 @@ static void gen_lxvh8x(DisasContext *ctx)
if (ctx->le_mode) {
gen_bswap16x8(xth, xtl, xth, xtl);
}
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -258,8 +248,8 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
tcg_gen_addi_tl(EA, EA, 8);
tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -301,16 +291,16 @@ static void gen_##name(DisasContext *ctx) \
} \
if (ctx->le_mode) { \
tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsrl(xt, xtl); \
+ set_cpu_vsr(xt, xtl, false); \
tcg_gen_addi_tl(EA, EA, 8); \
tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsrh(xt, xth); \
+ set_cpu_vsr(xt, xth, true); \
} else { \
tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsrh(xt, xth); \
+ set_cpu_vsr(xt, xth, true); \
tcg_gen_addi_tl(EA, EA, 8); \
tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsrl(xt, xtl); \
+ set_cpu_vsr(xt, xtl, false); \
} \
tcg_temp_free(EA); \
tcg_temp_free_i64(xth); \
@@ -347,8 +337,8 @@ static void gen_##name(DisasContext *ctx) \
} \
xth = tcg_temp_new_i64(); \
xtl = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, xt); \
- get_cpu_vsrl(xtl, xt); \
+ get_cpu_vsr(xth, xt, true); \
+ get_cpu_vsr(xtl, xt, false); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
if (indexed) { \
@@ -421,7 +411,7 @@ static void gen_##name(DisasContext *ctx) \
EA = tcg_temp_new(); \
gen_addr_imm_index(ctx, EA, 0x03); \
gen_qemu_##operation(ctx, xth, EA); \
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); \
/* NOTE: cpu_vsrl is undefined */ \
tcg_temp_free(EA); \
tcg_temp_free_i64(xth); \
@@ -443,7 +433,7 @@ static void gen_##name(DisasContext *ctx) \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
- get_cpu_vsrh(t0, xS(ctx->opcode)); \
+ get_cpu_vsr(t0, xS(ctx->opcode), true); \
gen_qemu_##operation(ctx, t0, EA); \
tcg_temp_free(EA); \
tcg_temp_free_i64(t0); \
@@ -468,10 +458,10 @@ static void gen_stxvd2x(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
- get_cpu_vsrh(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), true);
gen_qemu_st64_i64(ctx, t0, EA);
tcg_gen_addi_tl(EA, EA, 8);
- get_cpu_vsrl(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), false);
gen_qemu_st64_i64(ctx, t0, EA);
tcg_temp_free(EA);
tcg_temp_free_i64(t0);
@@ -489,8 +479,8 @@ static void gen_stxvw4x(DisasContext *ctx)
}
xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
+ get_cpu_vsr(xsl, xS(ctx->opcode), false);
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -529,8 +519,8 @@ static void gen_stxvh8x(DisasContext *ctx)
}
xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
+ get_cpu_vsr(xsl, xS(ctx->opcode), false);
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -566,8 +556,8 @@ static void gen_stxvb16x(DisasContext *ctx)
}
xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
+ get_cpu_vsr(xsl, xS(ctx->opcode), false);
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -590,7 +580,7 @@ static void gen_##name(DisasContext *ctx) \
return; \
} \
xth = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \
+ get_cpu_vsr(xth, rD(ctx->opcode) + 32, true); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_imm_index(ctx, EA, 0x03); \
@@ -618,7 +608,7 @@ static void gen_mfvsrwz(DisasContext *ctx)
}
TCGv_i64 tmp = tcg_temp_new_i64();
TCGv_i64 xsh = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
tcg_gen_ext32u_i64(tmp, xsh);
tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp);
tcg_temp_free_i64(tmp);
@@ -642,7 +632,7 @@ static void gen_mtvsrwa(DisasContext *ctx)
TCGv_i64 xsh = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_ext32s_i64(xsh, tmp);
- set_cpu_vsrh(xT(ctx->opcode), xsh);
+ set_cpu_vsr(xT(ctx->opcode), xsh, true);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(xsh);
}
@@ -664,7 +654,7 @@ static void gen_mtvsrwz(DisasContext *ctx)
TCGv_i64 xsh = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_ext32u_i64(xsh, tmp);
- set_cpu_vsrh(xT(ctx->opcode), xsh);
+ set_cpu_vsr(xT(ctx->opcode), xsh, true);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(xsh);
}
@@ -685,7 +675,7 @@ static void gen_mfvsrd(DisasContext *ctx)
}
}
t0 = tcg_temp_new_i64();
- get_cpu_vsrh(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), true);
tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
tcg_temp_free_i64(t0);
}
@@ -706,7 +696,7 @@ static void gen_mtvsrd(DisasContext *ctx)
}
t0 = tcg_temp_new_i64();
tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_temp_free_i64(t0);
}
@@ -725,7 +715,7 @@ static void gen_mfvsrld(DisasContext *ctx)
}
}
t0 = tcg_temp_new_i64();
- get_cpu_vsrl(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), false);
tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
tcg_temp_free_i64(t0);
}
@@ -751,10 +741,10 @@ static void gen_mtvsrdd(DisasContext *ctx)
} else {
tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
}
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]);
- set_cpu_vsrl(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, false);
tcg_temp_free_i64(t0);
}
@@ -776,8 +766,8 @@ static void gen_mtvsrws(DisasContext *ctx)
t0 = tcg_temp_new_i64();
tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rA(ctx->opcode)], 32, 32);
- set_cpu_vsrl(xT(ctx->opcode), t0);
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, false);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_temp_free_i64(t0);
}
@@ -797,33 +787,25 @@ static void gen_xxpermdi(DisasContext *ctx)
if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
(xT(ctx->opcode) == xB(ctx->opcode)))) {
- if ((DM(ctx->opcode) & 2) == 0) {
- get_cpu_vsrh(xh, xA(ctx->opcode));
- } else {
- get_cpu_vsrl(xh, xA(ctx->opcode));
- }
- if ((DM(ctx->opcode) & 1) == 0) {
- get_cpu_vsrh(xl, xB(ctx->opcode));
- } else {
- get_cpu_vsrl(xl, xB(ctx->opcode));
- }
+ get_cpu_vsr(xh, xA(ctx->opcode), (DM(ctx->opcode) & 2) == 0);
+ get_cpu_vsr(xl, xB(ctx->opcode), (DM(ctx->opcode) & 1) == 0);
- set_cpu_vsrh(xT(ctx->opcode), xh);
- set_cpu_vsrl(xT(ctx->opcode), xl);
+ set_cpu_vsr(xT(ctx->opcode), xh, true);
+ set_cpu_vsr(xT(ctx->opcode), xl, false);
} else {
if ((DM(ctx->opcode) & 2) == 0) {
- get_cpu_vsrh(xh, xA(ctx->opcode));
- set_cpu_vsrh(xT(ctx->opcode), xh);
+ get_cpu_vsr(xh, xA(ctx->opcode), true);
+ set_cpu_vsr(xT(ctx->opcode), xh, true);
} else {
- get_cpu_vsrl(xh, xA(ctx->opcode));
- set_cpu_vsrh(xT(ctx->opcode), xh);
+ get_cpu_vsr(xh, xA(ctx->opcode), false);
+ set_cpu_vsr(xT(ctx->opcode), xh, true);
}
if ((DM(ctx->opcode) & 1) == 0) {
- get_cpu_vsrh(xl, xB(ctx->opcode));
- set_cpu_vsrl(xT(ctx->opcode), xl);
+ get_cpu_vsr(xl, xB(ctx->opcode), true);
+ set_cpu_vsr(xT(ctx->opcode), xl, false);
} else {
- get_cpu_vsrl(xl, xB(ctx->opcode));
- set_cpu_vsrl(xT(ctx->opcode), xl);
+ get_cpu_vsr(xl, xB(ctx->opcode), false);
+ set_cpu_vsr(xT(ctx->opcode), xl, false);
}
}
tcg_temp_free_i64(xh);
@@ -847,7 +829,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
} \
xb = tcg_temp_new_i64(); \
sgm = tcg_temp_new_i64(); \
- get_cpu_vsrh(xb, xB(ctx->opcode)); \
+ get_cpu_vsr(xb, xB(ctx->opcode), true); \
tcg_gen_movi_i64(sgm, sgn_mask); \
switch (op) { \
case OP_ABS: { \
@@ -864,7 +846,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
} \
case OP_CPSGN: { \
TCGv_i64 xa = tcg_temp_new_i64(); \
- get_cpu_vsrh(xa, xA(ctx->opcode)); \
+ get_cpu_vsr(xa, xA(ctx->opcode), true); \
tcg_gen_and_i64(xa, xa, sgm); \
tcg_gen_andc_i64(xb, xb, sgm); \
tcg_gen_or_i64(xb, xb, xa); \
@@ -872,7 +854,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
break; \
} \
} \
- set_cpu_vsrh(xT(ctx->opcode), xb); \
+ set_cpu_vsr(xT(ctx->opcode), xb, true); \
tcg_temp_free_i64(xb); \
tcg_temp_free_i64(sgm); \
}
@@ -898,8 +880,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
xbl = tcg_temp_new_i64(); \
sgm = tcg_temp_new_i64(); \
tmp = tcg_temp_new_i64(); \
- get_cpu_vsrh(xbh, xb); \
- get_cpu_vsrl(xbl, xb); \
+ get_cpu_vsr(xbh, xb, true); \
+ get_cpu_vsr(xbl, xb, false); \
tcg_gen_movi_i64(sgm, sgn_mask); \
switch (op) { \
case OP_ABS: \
@@ -914,15 +896,15 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_CPSGN: \
xah = tcg_temp_new_i64(); \
xa = rA(ctx->opcode) + 32; \
- get_cpu_vsrh(tmp, xa); \
+ get_cpu_vsr(tmp, xa, true); \
tcg_gen_and_i64(xah, tmp, sgm); \
tcg_gen_andc_i64(xbh, xbh, sgm); \
tcg_gen_or_i64(xbh, xbh, xah); \
tcg_temp_free_i64(xah); \
break; \
} \
- set_cpu_vsrh(xt, xbh); \
- set_cpu_vsrl(xt, xbl); \
+ set_cpu_vsr(xt, xbh, true); \
+ set_cpu_vsr(xt, xbl, false); \
tcg_temp_free_i64(xbl); \
tcg_temp_free_i64(xbh); \
tcg_temp_free_i64(sgm); \
@@ -945,8 +927,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
xbh = tcg_temp_new_i64(); \
xbl = tcg_temp_new_i64(); \
sgm = tcg_temp_new_i64(); \
- get_cpu_vsrh(xbh, xB(ctx->opcode)); \
- get_cpu_vsrl(xbl, xB(ctx->opcode)); \
+ get_cpu_vsr(xbh, xB(ctx->opcode), true); \
+ get_cpu_vsr(xbl, xB(ctx->opcode), false); \
tcg_gen_movi_i64(sgm, sgn_mask); \
switch (op) { \
case OP_ABS: { \
@@ -967,8 +949,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_CPSGN: { \
TCGv_i64 xah = tcg_temp_new_i64(); \
TCGv_i64 xal = tcg_temp_new_i64(); \
- get_cpu_vsrh(xah, xA(ctx->opcode)); \
- get_cpu_vsrl(xal, xA(ctx->opcode)); \
+ get_cpu_vsr(xah, xA(ctx->opcode), true); \
+ get_cpu_vsr(xal, xA(ctx->opcode), false); \
tcg_gen_and_i64(xah, xah, sgm); \
tcg_gen_and_i64(xal, xal, sgm); \
tcg_gen_andc_i64(xbh, xbh, sgm); \
@@ -980,8 +962,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
break; \
} \
} \
- set_cpu_vsrh(xT(ctx->opcode), xbh); \
- set_cpu_vsrl(xT(ctx->opcode), xbl); \
+ set_cpu_vsr(xT(ctx->opcode), xbh, true); \
+ set_cpu_vsr(xT(ctx->opcode), xbl, false); \
tcg_temp_free_i64(xbh); \
tcg_temp_free_i64(xbl); \
tcg_temp_free_i64(sgm); \
@@ -1193,9 +1175,9 @@ static void gen_##name(DisasContext *ctx) \
} \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
- get_cpu_vsrh(t0, xB(ctx->opcode)); \
+ get_cpu_vsr(t0, xB(ctx->opcode), true); \
gen_helper_##name(t1, cpu_env, t0); \
- set_cpu_vsrh(xT(ctx->opcode), t1); \
+ set_cpu_vsr(xT(ctx->opcode), t1, true); \
tcg_temp_free_i64(t0); \
tcg_temp_free_i64(t1); \
}
@@ -1390,13 +1372,13 @@ static void gen_xxbrd(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_bswap64_i64(xth, xbh);
tcg_gen_bswap64_i64(xtl, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1419,12 +1401,12 @@ static void gen_xxbrh(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
gen_bswap16x8(xth, xtl, xbh, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1448,15 +1430,15 @@ static void gen_xxbrq(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
t0 = tcg_temp_new_i64();
tcg_gen_bswap64_i64(t0, xbl);
tcg_gen_bswap64_i64(xtl, xbh);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_gen_mov_i64(xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1480,12 +1462,12 @@ static void gen_xxbrw(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
gen_bswap32x4(xth, xtl, xbh, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1527,23 +1509,16 @@ static void glue(gen_, name)(DisasContext *ctx) \
b0 = tcg_temp_new_i64(); \
b1 = tcg_temp_new_i64(); \
tmp = tcg_temp_new_i64(); \
- if (high) { \
- get_cpu_vsrh(a0, xA(ctx->opcode)); \
- get_cpu_vsrh(a1, xA(ctx->opcode)); \
- get_cpu_vsrh(b0, xB(ctx->opcode)); \
- get_cpu_vsrh(b1, xB(ctx->opcode)); \
- } else { \
- get_cpu_vsrl(a0, xA(ctx->opcode)); \
- get_cpu_vsrl(a1, xA(ctx->opcode)); \
- get_cpu_vsrl(b0, xB(ctx->opcode)); \
- get_cpu_vsrl(b1, xB(ctx->opcode)); \
- } \
+ get_cpu_vsr(a0, xA(ctx->opcode), high); \
+ get_cpu_vsr(a1, xA(ctx->opcode), high); \
+ get_cpu_vsr(b0, xB(ctx->opcode), high); \
+ get_cpu_vsr(b1, xB(ctx->opcode), high); \
tcg_gen_shri_i64(a0, a0, 32); \
tcg_gen_shri_i64(b0, b0, 32); \
tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \
- set_cpu_vsrh(xT(ctx->opcode), tmp); \
+ set_cpu_vsr(xT(ctx->opcode), tmp, true); \
tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \
- set_cpu_vsrl(xT(ctx->opcode), tmp); \
+ set_cpu_vsr(xT(ctx->opcode), tmp, false); \
tcg_temp_free_i64(a0); \
tcg_temp_free_i64(a1); \
tcg_temp_free_i64(b0); \
@@ -1624,40 +1599,40 @@ static void gen_xxsldwi(DisasContext *ctx)
switch (SHW(ctx->opcode)) {
case 0: {
- get_cpu_vsrh(xth, xA(ctx->opcode));
- get_cpu_vsrl(xtl, xA(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), true);
+ get_cpu_vsr(xtl, xA(ctx->opcode), false);
break;
}
case 1: {
TCGv_i64 t0 = tcg_temp_new_i64();
- get_cpu_vsrh(xth, xA(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), true);
tcg_gen_shli_i64(xth, xth, 32);
- get_cpu_vsrl(t0, xA(ctx->opcode));
+ get_cpu_vsr(t0, xA(ctx->opcode), false);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xth, xth, t0);
- get_cpu_vsrl(xtl, xA(ctx->opcode));
+ get_cpu_vsr(xtl, xA(ctx->opcode), false);
tcg_gen_shli_i64(xtl, xtl, 32);
- get_cpu_vsrh(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), true);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xtl, xtl, t0);
tcg_temp_free_i64(t0);
break;
}
case 2: {
- get_cpu_vsrl(xth, xA(ctx->opcode));
- get_cpu_vsrh(xtl, xB(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), false);
+ get_cpu_vsr(xtl, xB(ctx->opcode), true);
break;
}
case 3: {
TCGv_i64 t0 = tcg_temp_new_i64();
- get_cpu_vsrl(xth, xA(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), false);
tcg_gen_shli_i64(xth, xth, 32);
- get_cpu_vsrh(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), true);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xth, xth, t0);
- get_cpu_vsrh(xtl, xB(ctx->opcode));
+ get_cpu_vsr(xtl, xB(ctx->opcode), true);
tcg_gen_shli_i64(xtl, xtl, 32);
- get_cpu_vsrl(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), false);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xtl, xtl, t0);
tcg_temp_free_i64(t0);
@@ -1665,8 +1640,8 @@ static void gen_xxsldwi(DisasContext *ctx)
}
}
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1694,8 +1669,8 @@ static void gen_##name(DisasContext *ctx) \
*/ \
if (uimm > 15) { \
tcg_gen_movi_i64(t1, 0); \
- set_cpu_vsrh(xT(ctx->opcode), t1); \
- set_cpu_vsrl(xT(ctx->opcode), t1); \
+ set_cpu_vsr(xT(ctx->opcode), t1, true); \
+ set_cpu_vsr(xT(ctx->opcode), t1, false); \
return; \
} \
tcg_gen_movi_i32(t0, uimm); \
@@ -1719,7 +1694,7 @@ static void gen_xsxexpdp(DisasContext *ctx)
return;
}
t0 = tcg_temp_new_i64();
- get_cpu_vsrh(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), true);
tcg_gen_extract_i64(rt, t0, 52, 11);
tcg_temp_free_i64(t0);
}
@@ -1737,12 +1712,12 @@ static void gen_xsxexpqp(DisasContext *ctx)
xth = tcg_temp_new_i64();
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
+ get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
tcg_gen_extract_i64(xth, xbh, 48, 15);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
tcg_gen_movi_i64(xtl, 0);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
tcg_temp_free_i64(xbh);
tcg_temp_free_i64(xth);
@@ -1766,7 +1741,7 @@ static void gen_xsiexpdp(DisasContext *ctx)
tcg_gen_andi_i64(t0, rb, 0x7FF);
tcg_gen_shli_i64(t0, t0, 52);
tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
/* dword[1] is undefined */
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1789,19 +1764,19 @@ static void gen_xsiexpqp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xah = tcg_temp_new_i64();
xal = tcg_temp_new_i64();
- get_cpu_vsrh(xah, rA(ctx->opcode) + 32);
- get_cpu_vsrl(xal, rA(ctx->opcode) + 32);
+ get_cpu_vsr(xah, rA(ctx->opcode) + 32, true);
+ get_cpu_vsr(xal, rA(ctx->opcode) + 32, false);
xbh = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
+ get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
t0 = tcg_temp_new_i64();
tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF);
tcg_gen_andi_i64(t0, xbh, 0x7FFF);
tcg_gen_shli_i64(t0, t0, 48);
tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
tcg_gen_mov_i64(xtl, xal);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1826,12 +1801,12 @@ static void gen_xsxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
- get_cpu_vsrh(t1, xB(ctx->opcode));
+ get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_extract_i64(exp, t1, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- get_cpu_vsrh(t1, xB(ctx->opcode));
+ get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_deposit_i64(rt, t0, t1, 0, 52);
tcg_temp_free_i64(t0);
@@ -1857,8 +1832,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
- get_cpu_vsrl(xbl, rB(ctx->opcode) + 32);
+ get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
+ get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
@@ -1869,9 +1844,9 @@ static void gen_xsxsigqp(DisasContext *ctx)
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_deposit_i64(xth, t0, xbh, 0, 48);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
tcg_gen_mov_i64(xtl, xbl);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(exp);
@@ -1904,22 +1879,22 @@ static void gen_xviexpsp(DisasContext *ctx)
xal = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xah, xA(ctx->opcode));
- get_cpu_vsrl(xal, xA(ctx->opcode));
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xah, xA(ctx->opcode), true);
+ get_cpu_vsr(xal, xA(ctx->opcode), false);
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
t0 = tcg_temp_new_i64();
tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF);
tcg_gen_andi_i64(t0, xbh, 0xFF000000FF);
tcg_gen_shli_i64(t0, t0, 23);
tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF);
tcg_gen_andi_i64(t0, xbl, 0xFF000000FF);
tcg_gen_shli_i64(t0, t0, 23);
tcg_gen_or_i64(xtl, xtl, t0);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1949,16 +1924,16 @@ static void gen_xviexpdp(DisasContext *ctx)
xal = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xah, xA(ctx->opcode));
- get_cpu_vsrl(xal, xA(ctx->opcode));
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xah, xA(ctx->opcode), true);
+ get_cpu_vsr(xal, xA(ctx->opcode), false);
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_deposit_i64(xth, xah, xbh, 52, 11);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1983,15 +1958,15 @@ static void gen_xvxexpsp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_shri_i64(xth, xbh, 23);
tcg_gen_andi_i64(xth, xth, 0xFF000000FF);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_shri_i64(xtl, xbl, 23);
tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -2014,13 +1989,13 @@ static void gen_xvxexpdp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_extract_i64(xth, xbh, 52, 11);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_extract_i64(xtl, xbl, 52, 11);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -2046,8 +2021,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
@@ -2058,14 +2033,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_deposit_i64(xth, t0, xbh, 0, 52);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_extract_i64(exp, xbl, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(exp);
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 21/34] target/ppc: receive high/low as argument in get/set_cpu_vsr
2021-10-29 20:24 ` [PATCH v2 21/34] target/ppc: receive high/low as argument in get/set_cpu_vsr matheus.ferst
@ 2021-10-30 22:31 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 22:31 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> Changes get_cpu_vsr to receive a new argument indicating whether the
> high or low part of the register is being accessed. This change improves
> consistency between the interfaces used to access Vector and VSX
> registers and helps to handle endianness in some cases.
>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> New in v2. Will be used in the next patch to address the problems in the
> v1 implementation of stxv/lxv.
> ---
> target/ppc/translate/vsx-impl.c.inc | 317 +++++++++++++---------------
> 1 file changed, 146 insertions(+), 171 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 22/34] target/ppc: moved stxv and lxv from legacy to decodtree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (20 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 21/34] target/ppc: receive high/low as argument in get/set_cpu_vsr matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 22:32 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 23/34] target/ppc: moved stxvx and lxvx " matheus.ferst
` (12 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Moved stxv and lxv implementation from the legacy system to
decodetree.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Do not access EA+8 first in LE.
- do_lstxv receives TCGv displ
---
target/ppc/insn32.decode | 8 +++++
target/ppc/translate.c | 17 ++--------
target/ppc/translate/vsx-impl.c.inc | 51 +++++++++++++++++++++++++++--
3 files changed, 59 insertions(+), 17 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e438177b32..296d6d6c5a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -28,6 +28,9 @@
%dq_rtp 22:4 !function=times_2
@DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
+%dq_rt_tsx 3:1 21:5
+@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@@ -385,3 +388,8 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
+
+# VSX Load/Store Instructions
+
+LXV 111101 ..... ..... ............ . 001 @DQ_TSX
+STXV 111101 ..... ..... ............ . 101 @DQ_TSX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e88b613093..9960df6e18 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7446,20 +7446,7 @@ static void gen_dform39(DisasContext *ctx)
/* handles stfdp, lxv, stxsd, stxssp lxvx */
static void gen_dform3D(DisasContext *ctx)
{
- if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
- switch (ctx->opcode & 0x7) {
- case 1: /* lxv */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_lxv(ctx);
- }
- break;
- case 5: /* stxv */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_stxv(ctx);
- }
- break;
- }
- } else { /* DS-FORM */
+ if ((ctx->opcode & 3) != 1) { /* DS-FORM */
switch (ctx->opcode & 0x3) {
case 0: /* stfdp */
if (ctx->insns_flags2 & PPC2_ISA205) {
@@ -7584,7 +7571,7 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
-/* handles stfdp, lxv, stxsd, stxssp, stxv */
+/* handles stfdp, stxsd, stxssp */
GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index d923c6a090..9da66b5348 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -307,7 +307,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xtl); \
}
-VSX_VECTOR_LOAD(lxv, ld_i64, 0)
VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
#define VSX_VECTOR_STORE(name, op, indexed) \
@@ -360,7 +359,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xtl); \
}
-VSX_VECTOR_STORE(stxv, st_i64, 0)
VSX_VECTOR_STORE(stxvx, st_i64, 1)
#ifdef TARGET_PPC64
@@ -2052,6 +2050,55 @@ static void gen_xvxsigdp(DisasContext *ctx)
tcg_temp_free_i64(xbl);
}
+static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
+ int rt, bool store)
+{
+ TCGv ea;
+ TCGv_i64 xt;
+ MemOp mop;
+
+ xt = tcg_temp_new_i64();
+
+ mop = DEF_MEMOP(MO_Q);
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, ra, displ);
+
+ if (store) {
+ get_cpu_vsr(xt, rt, !ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ gen_addr_add(ctx, ea, ea, 8);
+ get_cpu_vsr(xt, rt, ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt, xt, !ctx->le_mode);
+ gen_addr_add(ctx, ea, ea, 8);
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt, xt, ctx->le_mode);
+ }
+
+ tcg_temp_free(ea);
+ tcg_temp_free_i64(xt);
+ return true;
+}
+
+static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+
+ if (a->rt >= 32) {
+ REQUIRE_VSX(ctx);
+ } else {
+ REQUIRE_VECTOR(ctx);
+ }
+
+ return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);
+}
+
+TRANS(STXV, do_lstxv_D, true)
+TRANS(LXV, do_lstxv_D, false)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 22/34] target/ppc: moved stxv and lxv from legacy to decodtree
2021-10-29 20:24 ` [PATCH v2 22/34] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
@ 2021-10-30 22:32 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 22:32 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: "Lucas Mateus Castro (alqotel)"<lucas.castro@eldorado.org.br>
>
> Moved stxv and lxv implementation from the legacy system to
> decodetree.
>
> Signed-off-by: Luis Pires<luis.pires@eldorado.org.br>
> Signed-off-by: Lucas Mateus Castro (alqotel)<lucas.castro@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - Do not access EA+8 first in LE.
> - do_lstxv receives TCGv displ
> ---
> target/ppc/insn32.decode | 8 +++++
> target/ppc/translate.c | 17 ++--------
> target/ppc/translate/vsx-impl.c.inc | 51 +++++++++++++++++++++++++++--
> 3 files changed, 59 insertions(+), 17 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 23/34] target/ppc: moved stxvx and lxvx from legacy to decodtree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (21 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 22/34] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 24/34] target/ppc: added the instructions LXVP and STXVP matheus.ferst
` (11 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Moved stxvx and lxvx implementation from the legacy system to
decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 5 ++
target/ppc/translate/vsx-impl.c.inc | 121 ++++------------------------
target/ppc/translate/vsx-ops.c.inc | 2 -
3 files changed, 20 insertions(+), 108 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 296d6d6c5a..3ce26b2e6e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -103,6 +103,9 @@
@X_tbp_s_rc ...... ....0 s:1 .... ....0 .......... rc:1 &X_tb_s_rc rt=%x_frtp rb=%x_frbp
+%x_rt_tsx 0:1 21:5
+@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
+
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -393,3 +396,5 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
+LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
+STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 9da66b5348..1973bb18f3 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -255,112 +255,6 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_VECTOR_LOAD(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsr(xt, xtl, false); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsr(xt, xth, true); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsr(xt, xth, true); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsr(xt, xtl, false); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
-
-#define VSX_VECTOR_STORE(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- get_cpu_vsr(xth, xt, true); \
- get_cpu_vsr(xtl, xt, false); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_STORE(stxvx, st_i64, 1)
-
#ifdef TARGET_PPC64
#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
static void gen_##name(DisasContext *ctx) \
@@ -2096,8 +1990,23 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);
}
+static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+
+ if (a->rt >= 32) {
+ REQUIRE_VSX(ctx);
+ } else {
+ REQUIRE_VECTOR(ctx);
+ }
+
+ return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store);
+}
+
TRANS(STXV, do_lstxv_D, true)
TRANS(LXV, do_lstxv_D, false)
+TRANS(STXVX, do_lstxv_X, true)
+TRANS(LXVX, do_lstxv_X, false)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 1d41beef26..b94f3fa4e0 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -10,7 +10,6 @@ GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
@@ -25,7 +24,6 @@ GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 24/34] target/ppc: added the instructions LXVP and STXVP
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (22 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 23/34] target/ppc: moved stxvx and lxvx " matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 23:13 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 25/34] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
` (10 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions lxvp and stxvp using decodetree
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Do not access EA+24 first in LE.
---
target/ppc/insn32.decode | 5 +++
target/ppc/translate/vsx-impl.c.inc | 55 ++++++++++++++++++++++-------
2 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3ce26b2e6e..c252dec02f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -31,6 +31,9 @@
%dq_rt_tsx 3:1 21:5
@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx
+%rt_tsxp 21:1 22:4 !function=times_2
+@DQ_TSXP ...... ..... ra:5 ............ .... &D si=%dq_si rt=%rt_tsxp
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@@ -396,5 +399,7 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
+LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
+STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 1973bb18f3..05bf6ea40c 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1945,11 +1945,12 @@ static void gen_xvxsigdp(DisasContext *ctx)
}
static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
- int rt, bool store)
+ int rt, bool store, bool paired)
{
TCGv ea;
TCGv_i64 xt;
MemOp mop;
+ int rt1, rt2;
xt = tcg_temp_new_i64();
@@ -1958,18 +1959,42 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
gen_set_access_type(ctx, ACCESS_INT);
ea = do_ea_calc(ctx, ra, displ);
+ if (paired && ctx->le_mode) {
+ rt1 = rt + 1;
+ rt2 = rt;
+ } else {
+ rt1 = rt;
+ rt2 = rt + 1;
+ }
+
if (store) {
- get_cpu_vsr(xt, rt, !ctx->le_mode);
+ get_cpu_vsr(xt, rt1, !ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
gen_addr_add(ctx, ea, ea, 8);
- get_cpu_vsr(xt, rt, ctx->le_mode);
+ get_cpu_vsr(xt, rt1, ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ if (paired) {
+ gen_addr_add(ctx, ea, ea, 8);
+ get_cpu_vsr(xt, rt2, !ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ gen_addr_add(ctx, ea, ea, 8);
+ get_cpu_vsr(xt, rt2, ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ }
} else {
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
- set_cpu_vsr(rt, xt, !ctx->le_mode);
+ set_cpu_vsr(rt1, xt, !ctx->le_mode);
gen_addr_add(ctx, ea, ea, 8);
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
- set_cpu_vsr(rt, xt, ctx->le_mode);
+ set_cpu_vsr(rt1, xt, ctx->le_mode);
+ if (paired) {
+ gen_addr_add(ctx, ea, ea, 8);
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt2, xt, !ctx->le_mode);
+ gen_addr_add(ctx, ea, ea, 8);
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt2, xt, ctx->le_mode);
+ }
}
tcg_temp_free(ea);
@@ -1977,17 +2002,21 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
return true;
}
-static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
+static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
{
- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ if (paired) {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ } else {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ }
- if (a->rt >= 32) {
+ if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
}
- return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);
+ return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
}
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
@@ -2000,11 +2029,13 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
REQUIRE_VECTOR(ctx);
}
- return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store);
+ return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, false);
}
-TRANS(STXV, do_lstxv_D, true)
-TRANS(LXV, do_lstxv_D, false)
+TRANS(STXV, do_lstxv_D, true, false)
+TRANS(LXV, do_lstxv_D, false, false)
+TRANS(STXVP, do_lstxv_D, true, true)
+TRANS(LXVP, do_lstxv_D, false, true)
TRANS(STXVX, do_lstxv_X, true)
TRANS(LXVX, do_lstxv_X, false)
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 24/34] target/ppc: added the instructions LXVP and STXVP
2021-10-29 20:24 ` [PATCH v2 24/34] target/ppc: added the instructions LXVP and STXVP matheus.ferst
@ 2021-10-30 23:13 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 23:13 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: "Lucas Mateus Castro (alqotel)"<lucas.castro@eldorado.org.br>
>
> Implemented the instructions lxvp and stxvp using decodetree
>
> Signed-off-by: Luis Pires<luis.pires@eldorado.org.br>
> Signed-off-by: Lucas Mateus Castro (alqotel)<lucas.castro@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - Do not access EA+24 first in LE.
> ---
> target/ppc/insn32.decode | 5 +++
> target/ppc/translate/vsx-impl.c.inc | 55 ++++++++++++++++++++++-------
> 2 files changed, 48 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 25/34] target/ppc: added the instructions LXVPX and STXVPX
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (23 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 24/34] target/ppc: added the instructions LXVP and STXVP matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 26/34] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
` (9 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions lxvpx and stxvpx using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 3 +++
target/ppc/translate/vsx-impl.c.inc | 18 ++++++++++++------
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c252dec02f..e4508631b0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -108,6 +108,7 @@
%x_rt_tsx 0:1 21:5
@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
+@X_TSXP ...... ..... ra:5 rb:5 .......... . &X rt=%rt_tsxp
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -403,3 +404,5 @@ LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
+LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
+STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 9b870a9b8b..d634699e38 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2016,25 +2016,31 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
}
-static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
+static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
{
- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ if (paired) {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ } else {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ }
- if (a->rt >= 32) {
+ if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
}
- return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, false);
+ return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
}
TRANS(STXV, do_lstxv_D, true, false)
TRANS(LXV, do_lstxv_D, false, false)
TRANS(STXVP, do_lstxv_D, true, true)
TRANS(LXVP, do_lstxv_D, false, true)
-TRANS(STXVX, do_lstxv_X, true)
-TRANS(LXVX, do_lstxv_X, false)
+TRANS(STXVX, do_lstxv_X, true, false)
+TRANS(LXVX, do_lstxv_X, false, false)
+TRANS(STXVPX, do_lstxv_X, true, true)
+TRANS(LXVPX, do_lstxv_X, false, true)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 26/34] target/ppc: added the instructions PLXV and PSTXV
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (24 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 25/34] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 27/34] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
` (8 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions plxv and pstxv using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 10 ++++++++++
target/ppc/translate/vsx-impl.c.inc | 16 ++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 48756cd4ca..093439b370 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -23,6 +23,9 @@
@PLS_D ...... .. ... r:1 .. .................. \
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
+@8LS_D_TSX ...... .. . .. r:1 .. .................. \
+ ..... rt:6 ra:5 ................ \
+ &PLS_D si=%pls_si
### Fixed-Point Load Instructions
@@ -137,3 +140,10 @@ PSTFD 000001 10 0--.-- .................. \
PNOP ................................ \
-------------------------------- @PNOP
}
+
+### VSX instructions
+
+PLXV 000001 00 0--.-- .................. \
+ 11001 ...... ..... ................ @8LS_D_TSX
+PSTXV 000001 00 0--.-- .................. \
+ 11011 ...... ..... ................ @8LS_D_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index d634699e38..bbf437536e 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2016,6 +2016,20 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
}
+static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
+ bool store, bool paired)
+{
+ arg_D d;
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_lstxv(ctx, d.ra, tcg_constant_tl(d.si), d.rt, store, paired);
+}
+
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
{
if (paired) {
@@ -2041,6 +2055,8 @@ TRANS(STXVX, do_lstxv_X, true, false)
TRANS(LXVX, do_lstxv_X, false, false)
TRANS(STXVPX, do_lstxv_X, true, true)
TRANS(LXVPX, do_lstxv_X, false, true)
+TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
+TRANS64(PLXV, do_lstxv_PLS_D, false, false)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 27/34] target/ppc: added the instructions PLXVP and PSTXVP
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (25 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 26/34] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 28/34] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
` (7 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions plxvp and pstxvp using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 9 +++++++++
target/ppc/translate/vsx-impl.c.inc | 2 ++
2 files changed, 11 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 093439b370..880ac3edc7 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -27,6 +27,11 @@
..... rt:6 ra:5 ................ \
&PLS_D si=%pls_si
+%rt_tsxp 21:1 22:4 !function=times_2
+@8LS_D_TSXP ...... .. . .. r:1 .. .................. \
+ ...... ..... ra:5 ................ \
+ &PLS_D si=%pls_si rt=%rt_tsxp
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -147,3 +152,7 @@ PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
11011 ...... ..... ................ @8LS_D_TSX
+PLXVP 000001 00 0--.-- .................. \
+ 111010 ..... ..... ................ @8LS_D_TSXP
+PSTXVP 000001 00 0--.-- .................. \
+ 111110 ..... ..... ................ @8LS_D_TSXP
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index bbf437536e..3606acdb2e 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2057,6 +2057,8 @@ TRANS(STXVPX, do_lstxv_X, true, true)
TRANS(LXVPX, do_lstxv_X, false, true)
TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
TRANS64(PLXV, do_lstxv_PLS_D, false, false)
+TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
+TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 28/34] target/ppc: moved XXSPLTW to using decodetree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (26 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 27/34] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 29/34] target/ppc: moved XXSPLTIB " matheus.ferst
` (6 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires,
Bruno Larsen (billionai),
Matheus Ferst, david
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Changed the function that handles XXSPLTW emulation to using decodetree,
but still using the same logic.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 9 +++++++++
target/ppc/translate/vsx-impl.c.inc | 17 ++++++-----------
target/ppc/translate/vsx-ops.c.inc | 1 -
3 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e4508631b0..5d425ec076 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -116,6 +116,11 @@
&X_vrt_frbp vrt frbp
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+&XX2 xt xb uim:uint8_t
+%xx2_xt 0:1 21:5
+%xx2_xb 1:1 11:5
+@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
+
&Z22_bf_fra bf fra dm
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
@@ -406,3 +411,7 @@ LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
+
+## VSX splat instruction
+
+XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 3606acdb2e..3439268e1c 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1436,26 +1436,21 @@ static void gen_xxsel(DisasContext *ctx)
vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
}
-static void gen_xxspltw(DisasContext *ctx)
+static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
{
- int rt = xT(ctx->opcode);
- int rb = xB(ctx->opcode);
- int uim = UIM(ctx->opcode);
int tofs, bofs;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
+ REQUIRE_VSX(ctx);
- tofs = vsr_full_offset(rt);
- bofs = vsr_full_offset(rb);
- bofs += uim << MO_32;
+ tofs = vsr_full_offset(a->xt);
+ bofs = vsr_full_offset(a->xb);
+ bofs += a->uim << MO_32;
#ifndef HOST_WORDS_BIG_ENDIAN
bofs ^= 8 | 4;
#endif
tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
+ return true;
}
#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index b94f3fa4e0..b669b64d35 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -348,7 +348,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
-GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 29/34] target/ppc: moved XXSPLTIB to using decodetree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (27 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 28/34] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 30/34] target/ppc: implemented XXSPLTI32DX matheus.ferst
` (5 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires,
Bruno Larsen (billionai),
Matheus Ferst, david
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Changed the function that handles XXSPLTIB emulation to using
decodetree, but still use the same logic as before
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 5 +++++
target/ppc/translate/vsx-impl.c.inc | 20 ++++++--------------
target/ppc/translate/vsx-ops.c.inc | 1 -
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 5d425ec076..fd73946122 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -96,6 +96,10 @@
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+%x_xt 0:1 21:5
+&X_imm8 xt imm:uint8_t
+@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
+
&X_tb_sp_rc rt rb sp rc:bool
@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
@@ -414,4 +418,5 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
## VSX splat instruction
+XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 3439268e1c..b64b965255 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1455,23 +1455,15 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
-static void gen_xxspltib(DisasContext *ctx)
+static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
{
- uint8_t uim8 = IMM8(ctx->opcode);
- int rt = xT(ctx->opcode);
-
- if (rt < 32) {
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
+ if (a->xt < 32) {
+ REQUIRE_VSX(ctx);
} else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
+ REQUIRE_VECTOR(ctx);
}
- tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
+ tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(a->xt), 16, 16, a->imm);
+ return true;
}
static void gen_xxsldwi(DisasContext *ctx)
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index b669b64d35..152d1e5c3b 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -348,7 +348,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
-GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 30/34] target/ppc: implemented XXSPLTI32DX
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (28 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 29/34] target/ppc: moved XXSPLTIB " matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-30 23:27 ` Richard Henderson
2021-10-29 20:24 ` [PATCH v2 31/34] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
` (4 subsequent siblings)
34 siblings, 1 reply; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires,
Bruno Larsen (billionai),
Matheus Ferst, david
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented XXSPLTI32DX emulation using decodetree
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- 8RR_D si field is now unsigned
- Implemented with two tcg_gen_st_i32
---
target/ppc/insn64.decode | 11 +++++++++++
target/ppc/translate/vsx-impl.c.inc | 17 +++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 880ac3edc7..134bc60c57 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -32,6 +32,14 @@
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp
+# Format 8RR:D
+%8rr_si 32:s16 0:16
+%8rr_xt 16:1 21:5
+&8RR_D_IX xt ix si
+@8RR_D_IX ...... .. .... .. .. ................ \
+ ...... ..... ... ix:1 . ................ \
+ &8RR_D_IX si=%8rr_si xt=%8rr_xt
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -156,3 +164,6 @@ PLXVP 000001 00 0--.-- .................. \
111010 ..... ..... ................ @8LS_D_TSXP
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+
+XXSPLTI32DX 000001 01 0000 -- -- ................ \
+ 100000 ..... 000 .. ................ @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index b64b965255..552f05bbda 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,23 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
return true;
}
+static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
+{
+ TCGv_i32 imm;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ imm = tcg_constant_i32(a->si);
+
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 30/34] target/ppc: implemented XXSPLTI32DX
2021-10-29 20:24 ` [PATCH v2 30/34] target/ppc: implemented XXSPLTI32DX matheus.ferst
@ 2021-10-30 23:27 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-30 23:27 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lucas.castro, Bruno Larsen (billionai), luis.pires, groug, david
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: "Bruno Larsen (billionai)"<bruno.larsen@eldorado.org.br>
>
> Implemented XXSPLTI32DX emulation using decodetree
>
> Signed-off-by: Bruno Larsen (billionai)<bruno.larsen@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - 8RR_D si field is now unsigned
> - Implemented with two tcg_gen_st_i32
> ---
> target/ppc/insn64.decode | 11 +++++++++++
> target/ppc/translate/vsx-impl.c.inc | 17 +++++++++++++++++
> 2 files changed, 28 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 31/34] target/ppc: Implemented XXSPLTIW using decodetree
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (29 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 30/34] target/ppc: implemented XXSPLTI32DX matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 32/34] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
` (3 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires,
Bruno Larsen (billionai),
Matheus Ferst, david
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented the XXSPLTIW instruction, using decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 6 ++++++
target/ppc/translate/vsx-impl.c.inc | 10 ++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 134bc60c57..bd71f616cc 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -39,6 +39,10 @@
@8RR_D_IX ...... .. .... .. .. ................ \
...... ..... ... ix:1 . ................ \
&8RR_D_IX si=%8rr_si xt=%8rr_xt
+&8RR_D xt si:int32_t
+@8RR_D ...... .. .... .. .. ................ \
+ ...... ..... .... . ................ \
+ &8RR_D si=%8rr_si xt=%8rr_xt
### Fixed-Point Load Instructions
@@ -165,5 +169,7 @@ PLXVP 000001 00 0--.-- .................. \
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+XXSPLTIW 000001 01 0000 -- -- ................ \
+ 100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 552f05bbda..9b8612ee73 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,16 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
return true;
}
+static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_dup_imm(MO_32, vsr_full_offset(a->xt), 16, 16, a->si);
+
+ return true;
+}
+
static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
{
TCGv_i32 imm;
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 32/34] target/ppc: implemented XXSPLTIDP instruction
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (30 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 31/34] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 33/34] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
` (2 subsequent siblings)
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires,
Bruno Larsen (billionai),
Matheus Ferst, david
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented the instruction XXSPLTIDP using decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 2 ++
target/ppc/translate/vsx-impl.c.inc | 10 ++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index bd71f616cc..20aa2b4615 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -169,6 +169,8 @@ PLXVP 000001 00 0--.-- .................. \
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+XXSPLTIDP 000001 01 0000 -- -- ................ \
+ 100000 ..... 0010 . ................ @8RR_D
XXSPLTIW 000001 01 0000 -- -- ................ \
100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 9b8612ee73..95e762bf7b 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1476,6 +1476,16 @@ static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
return true;
}
+static bool trans_XXSPLTIDP(DisasContext *ctx, arg_8RR_D *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_dup_imm(MO_64, vsr_full_offset(a->xt), 16, 16,
+ helper_todouble(a->si));
+ return true;
+}
+
static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
{
TCGv_i32 imm;
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 33/34] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (31 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 32/34] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-10-29 20:24 ` [PATCH v2 34/34] target/ppc: Implement lxvkq instruction matheus.ferst
2021-11-01 0:13 ` [PATCH v2 00/34] PowerISA v3.1 instruction batch David Gibson
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Bruno Larsen,
Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 4 +++
target/ppc/insn64.decode | 19 ++++++++++
target/ppc/int_helper.c | 15 ++++++++
target/ppc/translate/vsx-impl.c.inc | 55 +++++++++++++++++++++++++++++
4 files changed, 93 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7ff1d055c4..627811cefc 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -520,6 +520,10 @@ DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr)
+DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVH, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVW, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVD, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 20aa2b4615..39e610913d 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -44,6 +44,16 @@
...... ..... .... . ................ \
&8RR_D si=%8rr_si xt=%8rr_xt
+# Format XX4
+&XX4 xt xa xb xc
+%xx4_xt 0:1 21:5
+%xx4_xa 2:1 16:5
+%xx4_xb 1:1 11:5
+%xx4_xc 3:1 6:5
+@XX4 ........ ........ ........ ........ \
+ ...... ..... ..... ..... ..... .. .... \
+ &XX4 xt=%xx4_xt xa=%xx4_xa xb=%xx4_xb xc=%xx4_xc
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -175,3 +185,12 @@ XXSPLTIW 000001 01 0000 -- -- ................ \
100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
+
+XXBLENDVD 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 11 .... @XX4
+XXBLENDVW 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 10 .... @XX4
+XXBLENDVH 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 01 .... @XX4
+XXBLENDVB 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 00 .... @XX4
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 6d475e1687..099bacf74c 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1736,6 +1736,21 @@ void helper_xxinsertw(CPUPPCState *env, ppc_vsr_t *xt,
*xt = t;
}
+#define XXBLEND(name, sz) \
+void glue(helper_XXBLENDV, name)(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ ppc_avr_t *c, uint32_t desc) \
+{ \
+ for (int i = 0; i < ARRAY_SIZE(t->glue(u, sz)); i++) { \
+ t->glue(u, sz)[i] = (c->glue(s, sz)[i] >> (sz - 1)) ? \
+ b->glue(u, sz)[i] : a->glue(u, sz)[i]; \
+ } \
+}
+XXBLEND(B, 8)
+XXBLEND(H, 16)
+XXBLEND(W, 32)
+XXBLEND(D, 64)
+#undef XXBLEND
+
#define VEXT_SIGNED(name, element, cast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 95e762bf7b..1b890b60a9 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2084,6 +2084,61 @@ TRANS64(PLXV, do_lstxv_PLS_D, false, false)
TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
+static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
+ TCGv_vec c)
+{
+ TCGv_vec tmp = tcg_temp_new_vec_matching(c);
+ tcg_gen_sari_vec(vece, tmp, c, (8 << vece) - 1);
+ tcg_gen_bitsel_vec(vece, t, tmp, b, a);
+ tcg_temp_free_vec(tmp);
+}
+
+static bool do_xxblendv(DisasContext *ctx, arg_XX4 *a, unsigned vece)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_sari_vec, 0
+ };
+ static const GVecGen4 ops[4] = {
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVB,
+ .opt_opc = vecop_list,
+ .vece = MO_8
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVH,
+ .opt_opc = vecop_list,
+ .vece = MO_16
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVW,
+ .opt_opc = vecop_list,
+ .vece = MO_32
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVD,
+ .opt_opc = vecop_list,
+ .vece = MO_64
+ }
+ };
+
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_4(vsr_full_offset(a->xt), vsr_full_offset(a->xa),
+ vsr_full_offset(a->xb), vsr_full_offset(a->xc),
+ 16, 16, &ops[vece]);
+
+ return true;
+}
+
+TRANS(XXBLENDVB, do_xxblendv, MO_8)
+TRANS(XXBLENDVH, do_xxblendv, MO_16)
+TRANS(XXBLENDVW, do_xxblendv, MO_32)
+TRANS(XXBLENDVD, do_xxblendv, MO_64)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v2 34/34] target/ppc: Implement lxvkq instruction
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (32 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 33/34] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
@ 2021-10-29 20:24 ` matheus.ferst
2021-11-01 0:13 ` [PATCH v2 00/34] PowerISA v3.1 instruction batch David Gibson
34 siblings, 0 replies; 54+ messages in thread
From: matheus.ferst @ 2021-10-29 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: lucas.castro, richard.henderson, groug, luis.pires, Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- valid_values mask removed
---
target/ppc/insn32.decode | 7 +++++
target/ppc/translate/vsx-impl.c.inc | 43 +++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fd73946122..e135b8aba4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -100,6 +100,9 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
+&X_uim5 xt uim:uint8_t
+@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
+
&X_tb_sp_rc rt rb sp rc:bool
@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
@@ -420,3 +423,7 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
+
+## VSX Vector Load Special Value Instruction
+
+LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 1b890b60a9..f4f19dd479 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1503,6 +1503,49 @@ static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
return true;
}
+static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
+{
+ static const uint64_t values[32] = {
+ 0, /* Unspecified */
+ 0x3FFF000000000000llu, /* QP +1.0 */
+ 0x4000000000000000llu, /* QP +2.0 */
+ 0x4000800000000000llu, /* QP +3.0 */
+ 0x4001000000000000llu, /* QP +4.0 */
+ 0x4001400000000000llu, /* QP +5.0 */
+ 0x4001800000000000llu, /* QP +6.0 */
+ 0x4001C00000000000llu, /* QP +7.0 */
+ 0x7FFF000000000000llu, /* QP +Inf */
+ 0x7FFF800000000000llu, /* QP dQNaN */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0x8000000000000000llu, /* QP -0.0 */
+ 0xBFFF000000000000llu, /* QP -1.0 */
+ 0xC000000000000000llu, /* QP -2.0 */
+ 0xC000800000000000llu, /* QP -3.0 */
+ 0xC001000000000000llu, /* QP -4.0 */
+ 0xC001400000000000llu, /* QP -5.0 */
+ 0xC001800000000000llu, /* QP -6.0 */
+ 0xC001C00000000000llu, /* QP -7.0 */
+ 0xFFFF000000000000llu, /* QP -Inf */
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (values[a->uim]) {
+ set_cpu_vsr(a->xt, tcg_constant_i64(0x0), false);
+ set_cpu_vsr(a->xt, tcg_constant_i64(values[a->uim]), true);
+ } else {
+ gen_invalid(ctx);
+ }
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.25.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v2 00/34] PowerISA v3.1 instruction batch
2021-10-29 20:23 [PATCH v2 00/34] PowerISA v3.1 instruction batch matheus.ferst
` (33 preceding siblings ...)
2021-10-29 20:24 ` [PATCH v2 34/34] target/ppc: Implement lxvkq instruction matheus.ferst
@ 2021-11-01 0:13 ` David Gibson
2021-11-01 0:22 ` David Gibson
34 siblings, 1 reply; 54+ messages in thread
From: David Gibson @ 2021-11-01 0:13 UTC (permalink / raw)
To: matheus.ferst
Cc: lucas.castro, richard.henderson, qemu-devel, groug, luis.pires, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 4519 bytes --]
On Fri, Oct 29, 2021 at 05:23:50PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> This patch series implements 56 new instructions for POWER10, moving 28
> "old" instructions to decodetree along the way. The series is divided by
> facility as follows:
>
> - From patch 1 to 4: Floating-Point
> - From patch 5 to 10: Fixed-Point
> - From patch 11 to 19: Vector
> - From patch 20 to 34: Vector-Scalar Extensions
>
> Based-on: <20211029192417.400707-1-luis.pires@eldorado.org.br>
> because of patch 2 ("target/ppc: Move REQUIRE_ALTIVEC/VECTOR to
> translate.c") and patch 3 ("target/ppc: Introduce REQUIRE_FPU"), and
> Based-on: ppc-for-6.2
>
> Patches without review: 7-8, 12, 14-16, 19, 21-22, 24, 30
Patches 1..6 applied to ppc-for-6.2.
>
> v2:
> - do_ea_calc now allocate and returns ea
> - Inline version of cntlzdm/cnttzdm
> - vecop_list removed from GVecGen* without fniv
> - vsldbi/vsrdbi implemented with tcg_gen_extract2_i64
> - memcpy instead of misaligned load/stores on vector insert instructions
> - Simplified helper for Vector Extract
> - Fixed [p]stxv[xp]/[p]lxv[xp] to always access to lowest address first
> in LE
> - xxsplti32dx implemented with tcg_gen_st_i32
> - valid_values mask removed from lxvkq implementation
>
> Bruno Larsen (billionai) (6):
> target/ppc: Introduce REQUIRE_VSX macro
> target/ppc: moved XXSPLTW to using decodetree
> target/ppc: moved XXSPLTIB to using decodetree
> target/ppc: implemented XXSPLTI32DX
> target/ppc: Implemented XXSPLTIW using decodetree
> target/ppc: implemented XXSPLTIDP instruction
>
> Fernando Eckhardt Valle (4):
> target/ppc: introduce do_ea_calc
> target/ppc: move resolve_PLS_D to translate.c
> target/ppc: Move load and store floating point instructions to
> decodetree
> target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions
>
> Lucas Mateus Castro (alqotel) (6):
> target/ppc: moved stxv and lxv from legacy to decodtree
> target/ppc: moved stxvx and lxvx from legacy to decodtree
> target/ppc: added the instructions LXVP and STXVP
> target/ppc: added the instructions LXVPX and STXVPX
> target/ppc: added the instructions PLXV and PSTXV
> target/ppc: added the instructions PLXVP and PSTXVP
>
> Luis Pires (2):
> target/ppc: Implement cntlzdm
> target/ppc: Implement cnttzdm
>
> Matheus Ferst (16):
> target/ppc: Move LQ and STQ to decodetree
> target/ppc: Implement PLQ and PSTQ
> target/ppc: Implement pdepd instruction
> target/ppc: Implement pextd instruction
> target/ppc: Move vcfuged to vmx-impl.c.inc
> target/ppc: Implement vclzdm/vctzdm instructions
> target/ppc: Implement vpdepd/vpextd instruction
> target/ppc: Implement vsldbi/vsrdbi instructions
> target/ppc: Implement Vector Insert from GPR using GPR index insns
> target/ppc: Implement Vector Insert Word from GPR using Immediate
> insns
> target/ppc: Implement Vector Insert from VSR using GPR index insns
> target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree
> target/ppc: Implement Vector Extract Double to VSR using GPR index
> insns
> target/ppc: receive high/low as argument in get/set_cpu_vsr
> target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd
> instructions
> target/ppc: Implement lxvkq instruction
>
> target/ppc/helper.h | 20 +-
> target/ppc/insn32.decode | 132 ++++
> target/ppc/insn64.decode | 72 +++
> target/ppc/int_helper.c | 134 +++-
> target/ppc/translate.c | 215 ++-----
> target/ppc/translate/fixedpoint-impl.c.inc | 218 ++++++-
> target/ppc/translate/fp-impl.c.inc | 261 +++-----
> target/ppc/translate/fp-ops.c.inc | 29 -
> target/ppc/translate/vector-impl.c.inc | 48 --
> target/ppc/translate/vmx-impl.c.inc | 334 +++++++++-
> target/ppc/translate/vmx-ops.c.inc | 10 +-
> target/ppc/translate/vsx-impl.c.inc | 701 ++++++++++++---------
> target/ppc/translate/vsx-ops.c.inc | 4 -
> 13 files changed, 1387 insertions(+), 791 deletions(-)
> delete mode 100644 target/ppc/translate/vector-impl.c.inc
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v2 00/34] PowerISA v3.1 instruction batch
2021-11-01 0:13 ` [PATCH v2 00/34] PowerISA v3.1 instruction batch David Gibson
@ 2021-11-01 0:22 ` David Gibson
0 siblings, 0 replies; 54+ messages in thread
From: David Gibson @ 2021-11-01 0:22 UTC (permalink / raw)
To: matheus.ferst
Cc: lucas.castro, richard.henderson, qemu-devel, groug, luis.pires, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 4945 bytes --]
On Mon, Nov 01, 2021 at 11:13:42AM +1100, David Gibson wrote:
> On Fri, Oct 29, 2021 at 05:23:50PM -0300, matheus.ferst@eldorado.org.br wrote:
> > From: Matheus Ferst <matheus.ferst@eldorado.org.br>
> >
> > This patch series implements 56 new instructions for POWER10, moving 28
> > "old" instructions to decodetree along the way. The series is divided by
> > facility as follows:
> >
> > - From patch 1 to 4: Floating-Point
> > - From patch 5 to 10: Fixed-Point
> > - From patch 11 to 19: Vector
> > - From patch 20 to 34: Vector-Scalar Extensions
> >
> > Based-on: <20211029192417.400707-1-luis.pires@eldorado.org.br>
> > because of patch 2 ("target/ppc: Move REQUIRE_ALTIVEC/VECTOR to
> > translate.c") and patch 3 ("target/ppc: Introduce REQUIRE_FPU"), and
> > Based-on: ppc-for-6.2
> >
> > Patches without review: 7-8, 12, 14-16, 19, 21-22, 24, 30
>
> Patches 1..6 applied to ppc-for-6.2.
Patches 7..10 now applied as well. 11 doesn't apply clean for me now,
so if you can fix that up, fold in Richard's further reviews and
repost, please.
>
> >
> > v2:
> > - do_ea_calc now allocate and returns ea
> > - Inline version of cntlzdm/cnttzdm
> > - vecop_list removed from GVecGen* without fniv
> > - vsldbi/vsrdbi implemented with tcg_gen_extract2_i64
> > - memcpy instead of misaligned load/stores on vector insert instructions
> > - Simplified helper for Vector Extract
> > - Fixed [p]stxv[xp]/[p]lxv[xp] to always access to lowest address first
> > in LE
> > - xxsplti32dx implemented with tcg_gen_st_i32
> > - valid_values mask removed from lxvkq implementation
> >
> > Bruno Larsen (billionai) (6):
> > target/ppc: Introduce REQUIRE_VSX macro
> > target/ppc: moved XXSPLTW to using decodetree
> > target/ppc: moved XXSPLTIB to using decodetree
> > target/ppc: implemented XXSPLTI32DX
> > target/ppc: Implemented XXSPLTIW using decodetree
> > target/ppc: implemented XXSPLTIDP instruction
> >
> > Fernando Eckhardt Valle (4):
> > target/ppc: introduce do_ea_calc
> > target/ppc: move resolve_PLS_D to translate.c
> > target/ppc: Move load and store floating point instructions to
> > decodetree
> > target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions
> >
> > Lucas Mateus Castro (alqotel) (6):
> > target/ppc: moved stxv and lxv from legacy to decodtree
> > target/ppc: moved stxvx and lxvx from legacy to decodtree
> > target/ppc: added the instructions LXVP and STXVP
> > target/ppc: added the instructions LXVPX and STXVPX
> > target/ppc: added the instructions PLXV and PSTXV
> > target/ppc: added the instructions PLXVP and PSTXVP
> >
> > Luis Pires (2):
> > target/ppc: Implement cntlzdm
> > target/ppc: Implement cnttzdm
> >
> > Matheus Ferst (16):
> > target/ppc: Move LQ and STQ to decodetree
> > target/ppc: Implement PLQ and PSTQ
> > target/ppc: Implement pdepd instruction
> > target/ppc: Implement pextd instruction
> > target/ppc: Move vcfuged to vmx-impl.c.inc
> > target/ppc: Implement vclzdm/vctzdm instructions
> > target/ppc: Implement vpdepd/vpextd instruction
> > target/ppc: Implement vsldbi/vsrdbi instructions
> > target/ppc: Implement Vector Insert from GPR using GPR index insns
> > target/ppc: Implement Vector Insert Word from GPR using Immediate
> > insns
> > target/ppc: Implement Vector Insert from VSR using GPR index insns
> > target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree
> > target/ppc: Implement Vector Extract Double to VSR using GPR index
> > insns
> > target/ppc: receive high/low as argument in get/set_cpu_vsr
> > target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd
> > instructions
> > target/ppc: Implement lxvkq instruction
> >
> > target/ppc/helper.h | 20 +-
> > target/ppc/insn32.decode | 132 ++++
> > target/ppc/insn64.decode | 72 +++
> > target/ppc/int_helper.c | 134 +++-
> > target/ppc/translate.c | 215 ++-----
> > target/ppc/translate/fixedpoint-impl.c.inc | 218 ++++++-
> > target/ppc/translate/fp-impl.c.inc | 261 +++-----
> > target/ppc/translate/fp-ops.c.inc | 29 -
> > target/ppc/translate/vector-impl.c.inc | 48 --
> > target/ppc/translate/vmx-impl.c.inc | 334 +++++++++-
> > target/ppc/translate/vmx-ops.c.inc | 10 +-
> > target/ppc/translate/vsx-impl.c.inc | 701 ++++++++++++---------
> > target/ppc/translate/vsx-ops.c.inc | 4 -
> > 13 files changed, 1387 insertions(+), 791 deletions(-)
> > delete mode 100644 target/ppc/translate/vector-impl.c.inc
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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