From: Vincent Pelletier <plr.vincent@gmail.com>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: Marc Zyngier <maz@kernel.org>,
guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de,
robh@kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT
Date: Mon, 1 Nov 2021 05:11:34 +0000 [thread overview]
Message-ID: <20211101051134.447647af@gmail.com> (raw)
In-Reply-To: <20211028135523.5cf4b66b@redslave.neermore.group>
On Thu, 28 Oct 2021 13:55:23 +0300, Nikita Shubin <nikita.shubin@maquefel.me> wrote:
> This indeed happens with SiFive PLIC. I am currently tinkering with
> da9063 RTC on SiFive Unmatched, and ALARM irq fires only once.
Happy to see someone else having this issue. I hit this issue in July
and tried to get feedback, but nothing happened and I gave up:
http://lists.infradead.org/pipermail/linux-riscv/2021-July/007441.html
My uneducated guess, by spying on the registers behind the kernel's
back (see the python script I attached), was that this could be
specific to level-signalled interrupts, where the IRQ re-triggers in
the PLIC right after being cleared but after being unbound from any
hart. Then the "IRQ pending" flag is set (causing the IRQ edge which
would normally trigger interrupt handling in associated hart) without
anything noticing, so it will never be cleared and never be handled.
> However
> with changes proposed by Guo Ren in plic_thead_irq_eoi, everything
> begins to work fine.
Great news, so this issue will be fixed in a better way than my RFC.
RFC which can hence be discarded in patchwork, I believe:
https://patchwork.kernel.org/project/linux-riscv/patch/8c36c1a28ce63b5120765fd3c636944bfec8bee9.1625882423.git.plr.vincent@gmail.com/
(I'm not sure if I can do it myself)
Regards,
--
Vincent Pelletier
GPG fingerprint 983A E8B7 3B91 1598 7A92 3845 CAC9 3691 4257 B0C1
WARNING: multiple messages have this Message-ID (diff)
From: Vincent Pelletier <plr.vincent@gmail.com>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: Marc Zyngier <maz@kernel.org>,
guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de,
robh@kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT
Date: Mon, 1 Nov 2021 05:11:34 +0000 [thread overview]
Message-ID: <20211101051134.447647af@gmail.com> (raw)
In-Reply-To: <20211028135523.5cf4b66b@redslave.neermore.group>
On Thu, 28 Oct 2021 13:55:23 +0300, Nikita Shubin <nikita.shubin@maquefel.me> wrote:
> This indeed happens with SiFive PLIC. I am currently tinkering with
> da9063 RTC on SiFive Unmatched, and ALARM irq fires only once.
Happy to see someone else having this issue. I hit this issue in July
and tried to get feedback, but nothing happened and I gave up:
http://lists.infradead.org/pipermail/linux-riscv/2021-July/007441.html
My uneducated guess, by spying on the registers behind the kernel's
back (see the python script I attached), was that this could be
specific to level-signalled interrupts, where the IRQ re-triggers in
the PLIC right after being cleared but after being unbound from any
hart. Then the "IRQ pending" flag is set (causing the IRQ edge which
would normally trigger interrupt handling in associated hart) without
anything noticing, so it will never be cleared and never be handled.
> However
> with changes proposed by Guo Ren in plic_thead_irq_eoi, everything
> begins to work fine.
Great news, so this issue will be fixed in a better way than my RFC.
RFC which can hence be discarded in patchwork, I believe:
https://patchwork.kernel.org/project/linux-riscv/patch/8c36c1a28ce63b5120765fd3c636944bfec8bee9.1625882423.git.plr.vincent@gmail.com/
(I'm not sure if I can do it myself)
Regards,
--
Vincent Pelletier
GPG fingerprint 983A E8B7 3B91 1598 7A92 3845 CAC9 3691 4257 B0C1
_______________________________________________
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next prev parent reply other threads:[~2021-11-01 5:11 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-24 1:33 [PATCH V5 0/3] Add thead,c900-plic support guoren
2021-10-24 1:33 ` guoren
2021-10-24 1:33 ` [PATCH V5 1/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
2021-10-24 1:33 ` guoren
2021-11-02 2:21 ` Guo Ren
2021-11-02 2:21 ` Guo Ren
2021-11-02 12:59 ` Rob Herring
2021-11-02 12:59 ` Rob Herring
2021-11-03 1:52 ` Guo Ren
2021-11-03 1:52 ` Guo Ren
2021-10-24 1:33 ` [PATCH V5 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-24 1:33 ` guoren
2021-10-24 7:35 ` Anup Patel
2021-10-24 7:35 ` Anup Patel
2021-10-24 9:01 ` Guo Ren
2021-10-24 9:01 ` Guo Ren
2021-10-24 9:18 ` Anup Patel
2021-10-24 9:18 ` Anup Patel
2021-10-24 9:35 ` Guo Ren
2021-10-24 9:35 ` Guo Ren
2021-10-24 9:52 ` Anup Patel
2021-10-24 9:52 ` Anup Patel
2021-10-24 10:04 ` Guo Ren
2021-10-24 10:04 ` Guo Ren
2021-10-24 1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT guoren
2021-10-24 1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " guoren
2021-10-25 10:48 ` Marc Zyngier
2021-10-25 10:48 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2021-10-25 13:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " Guo Ren
2021-10-25 13:33 ` Guo Ren
2021-10-28 10:55 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Nikita Shubin
2021-10-28 10:55 ` Nikita Shubin
2021-10-28 14:58 ` Marc Zyngier
2021-10-28 14:58 ` Marc Zyngier
2021-10-30 10:27 ` Anup Patel
2021-10-30 10:27 ` Anup Patel
2021-11-01 2:20 ` Guo Ren
2021-11-01 2:20 ` Guo Ren
2021-11-01 2:53 ` Anup Patel
2021-11-01 2:53 ` Anup Patel
2021-11-01 3:57 ` Guo Ren
2021-11-01 3:57 ` Guo Ren
2021-11-01 4:27 ` Anup Patel
2021-11-01 4:27 ` Anup Patel
2021-11-01 7:56 ` Guo Ren
2021-11-01 7:56 ` Guo Ren
2021-11-01 9:27 ` Marc Zyngier
2021-11-01 9:27 ` Marc Zyngier
2021-11-01 9:25 ` Marc Zyngier
2021-11-01 9:25 ` Marc Zyngier
2021-11-01 2:00 ` Guo Ren
2021-11-01 2:00 ` Guo Ren
2021-11-01 5:11 ` Vincent Pelletier [this message]
2021-11-01 5:11 ` Vincent Pelletier
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