From: Anup Patel <anup@brainfault.org> To: Marc Zyngier <maz@kernel.org> Cc: "Nikita Shubin" <nikita.shubin@maquefel.me>, "Guo Ren" <guoren@kernel.org>, "Atish Patra" <atish.patra@wdc.com>, "Thomas Gleixner" <tglx@linutronix.de>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Heiko Stübner" <heiko@sntech.de>, "Rob Herring" <robh@kernel.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, "Guo Ren" <guoren@linux.alibaba.com> Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT Date: Sat, 30 Oct 2021 15:57:16 +0530 [thread overview] Message-ID: <CAAhSdy3+vaUODbVbjQtUbB+exjrsrY3CitNvzEEcrh_nSBg6yA@mail.gmail.com> (raw) In-Reply-To: <87sfwl9oxg.wl-maz@kernel.org> On Thu, Oct 28, 2021 at 8:28 PM Marc Zyngier <maz@kernel.org> wrote: > > On Thu, 28 Oct 2021 11:55:23 +0100, > Nikita Shubin <nikita.shubin@maquefel.me> wrote: > > > > Hello Marc and Guo Ren! > > > > On Mon, 25 Oct 2021 11:48:33 +0100 > > Marc Zyngier <maz@kernel.org> wrote: > > > > > On Sun, 24 Oct 2021 02:33:03 +0100, > > > guoren@kernel.org wrote: > > > > > > > > From: Guo Ren <guoren@linux.alibaba.com> > > > > > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the > > > > driver, only the first interrupt could be handled, and continue irq > > > > is blocked by hw. Because the thead,c900-plic couldn't complete > > > > masked irq source which has been disabled in enable register. Add > > > > thead_plic_chip which fix up c906-plic irq source completion > > > > problem by unmask/mask wrapper. > > > > > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > > > > > The PLIC signals it has completed executing an interrupt handler by > > > > writing the interrupt ID it received from the claim to the > > > > claim/complete register. The PLIC does not check whether the > > > > completion ID is the same as the last claim ID for that target. If > > > > the completion ID does not match an interrupt source that is > > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ > > > > completion is silently ignored. > > > > > > Given this bit of the spec... > > > > > > > +static void plic_thead_irq_eoi(struct irq_data *d) > > > > +{ > > > > + struct plic_handler *handler = > > > > this_cpu_ptr(&plic_handlers); + > > > > + if (irqd_irq_masked(d)) { > > > > + plic_irq_unmask(d); > > > > + writel(d->hwirq, handler->hart_base + > > > > CONTEXT_CLAIM); > > > > + plic_irq_mask(d); > > > > + } else { > > > > + writel(d->hwirq, handler->hart_base + > > > > CONTEXT_CLAIM); > > > > + } > > > > +} > > > > + > > > > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC. > > > > This indeed happens with SiFive PLIC. I am currently tinkering with > > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However > > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything > > begins to work fine. > > > > May be these change should be propagated to plic_irq_eoi instead of > > making a new function ? > > That's my impression too. I think the T-Head defect is pretty much > immaterial when you consider how 'interesting' the PLIC architecture > is. Conflating EOI and masking really is a misfeature... Unfortunately, the PLIC implementation is the same across existing boards (except T-HEAD) so this issue is there on all existing boards. I double checked the upcoming RISC-V AIA specification and this problem is not there in RISC-V AIA because the interrupt claim/completion is different. (Refer, https://github.com/riscv/riscv-aia/releases/download/0.2-draft.27/riscv-interrupts-027.pdf) I plan to send-out RFC PATCH for AIA soon so that we get early feedback from everyone on LKML. Regards, Anup > > M. > > -- > Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Marc Zyngier <maz@kernel.org> Cc: "Nikita Shubin" <nikita.shubin@maquefel.me>, "Guo Ren" <guoren@kernel.org>, "Atish Patra" <atish.patra@wdc.com>, "Thomas Gleixner" <tglx@linutronix.de>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Heiko Stübner" <heiko@sntech.de>, "Rob Herring" <robh@kernel.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, "Guo Ren" <guoren@linux.alibaba.com> Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT Date: Sat, 30 Oct 2021 15:57:16 +0530 [thread overview] Message-ID: <CAAhSdy3+vaUODbVbjQtUbB+exjrsrY3CitNvzEEcrh_nSBg6yA@mail.gmail.com> (raw) In-Reply-To: <87sfwl9oxg.wl-maz@kernel.org> On Thu, Oct 28, 2021 at 8:28 PM Marc Zyngier <maz@kernel.org> wrote: > > On Thu, 28 Oct 2021 11:55:23 +0100, > Nikita Shubin <nikita.shubin@maquefel.me> wrote: > > > > Hello Marc and Guo Ren! > > > > On Mon, 25 Oct 2021 11:48:33 +0100 > > Marc Zyngier <maz@kernel.org> wrote: > > > > > On Sun, 24 Oct 2021 02:33:03 +0100, > > > guoren@kernel.org wrote: > > > > > > > > From: Guo Ren <guoren@linux.alibaba.com> > > > > > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the > > > > driver, only the first interrupt could be handled, and continue irq > > > > is blocked by hw. Because the thead,c900-plic couldn't complete > > > > masked irq source which has been disabled in enable register. Add > > > > thead_plic_chip which fix up c906-plic irq source completion > > > > problem by unmask/mask wrapper. > > > > > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > > > > > The PLIC signals it has completed executing an interrupt handler by > > > > writing the interrupt ID it received from the claim to the > > > > claim/complete register. The PLIC does not check whether the > > > > completion ID is the same as the last claim ID for that target. If > > > > the completion ID does not match an interrupt source that is > > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ > > > > completion is silently ignored. > > > > > > Given this bit of the spec... > > > > > > > +static void plic_thead_irq_eoi(struct irq_data *d) > > > > +{ > > > > + struct plic_handler *handler = > > > > this_cpu_ptr(&plic_handlers); + > > > > + if (irqd_irq_masked(d)) { > > > > + plic_irq_unmask(d); > > > > + writel(d->hwirq, handler->hart_base + > > > > CONTEXT_CLAIM); > > > > + plic_irq_mask(d); > > > > + } else { > > > > + writel(d->hwirq, handler->hart_base + > > > > CONTEXT_CLAIM); > > > > + } > > > > +} > > > > + > > > > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC. > > > > This indeed happens with SiFive PLIC. I am currently tinkering with > > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However > > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything > > begins to work fine. > > > > May be these change should be propagated to plic_irq_eoi instead of > > making a new function ? > > That's my impression too. I think the T-Head defect is pretty much > immaterial when you consider how 'interesting' the PLIC architecture > is. Conflating EOI and masking really is a misfeature... Unfortunately, the PLIC implementation is the same across existing boards (except T-HEAD) so this issue is there on all existing boards. I double checked the upcoming RISC-V AIA specification and this problem is not there in RISC-V AIA because the interrupt claim/completion is different. (Refer, https://github.com/riscv/riscv-aia/releases/download/0.2-draft.27/riscv-interrupts-027.pdf) I plan to send-out RFC PATCH for AIA soon so that we get early feedback from everyone on LKML. Regards, Anup > > M. > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-10-30 10:27 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-24 1:33 [PATCH V5 0/3] Add thead,c900-plic support guoren 2021-10-24 1:33 ` guoren 2021-10-24 1:33 ` [PATCH V5 1/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren 2021-10-24 1:33 ` guoren 2021-11-02 2:21 ` Guo Ren 2021-11-02 2:21 ` Guo Ren 2021-11-02 12:59 ` Rob Herring 2021-11-02 12:59 ` Rob Herring 2021-11-03 1:52 ` Guo Ren 2021-11-03 1:52 ` Guo Ren 2021-10-24 1:33 ` [PATCH V5 2/3] dt-bindings: update riscv plic compatible string guoren 2021-10-24 1:33 ` guoren 2021-10-24 7:35 ` Anup Patel 2021-10-24 7:35 ` Anup Patel 2021-10-24 9:01 ` Guo Ren 2021-10-24 9:01 ` Guo Ren 2021-10-24 9:18 ` Anup Patel 2021-10-24 9:18 ` Anup Patel 2021-10-24 9:35 ` Guo Ren 2021-10-24 9:35 ` Guo Ren 2021-10-24 9:52 ` Anup Patel 2021-10-24 9:52 ` Anup Patel 2021-10-24 10:04 ` Guo Ren 2021-10-24 10:04 ` Guo Ren 2021-10-24 1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT guoren 2021-10-24 1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " guoren 2021-10-25 10:48 ` Marc Zyngier 2021-10-25 10:48 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier 2021-10-25 13:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " Guo Ren 2021-10-25 13:33 ` Guo Ren 2021-10-28 10:55 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Nikita Shubin 2021-10-28 10:55 ` Nikita Shubin 2021-10-28 14:58 ` Marc Zyngier 2021-10-28 14:58 ` Marc Zyngier 2021-10-30 10:27 ` Anup Patel [this message] 2021-10-30 10:27 ` Anup Patel 2021-11-01 2:20 ` Guo Ren 2021-11-01 2:20 ` Guo Ren 2021-11-01 2:53 ` Anup Patel 2021-11-01 2:53 ` Anup Patel 2021-11-01 3:57 ` Guo Ren 2021-11-01 3:57 ` Guo Ren 2021-11-01 4:27 ` Anup Patel 2021-11-01 4:27 ` Anup Patel 2021-11-01 7:56 ` Guo Ren 2021-11-01 7:56 ` Guo Ren 2021-11-01 9:27 ` Marc Zyngier 2021-11-01 9:27 ` Marc Zyngier 2021-11-01 9:25 ` Marc Zyngier 2021-11-01 9:25 ` Marc Zyngier 2021-11-01 2:00 ` Guo Ren 2021-11-01 2:00 ` Guo Ren 2021-11-01 5:11 ` Vincent Pelletier 2021-11-01 5:11 ` Vincent Pelletier
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