From: Emil Renner Berthing <kernel@esmil.dk> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Cc: Emil Renner Berthing <kernel@esmil.dk>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Linus Walleij <linus.walleij@linaro.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Andy Shevchenko <andriy.shevchenko@linux.intel.com>, Jiri Slaby <jirislaby@kernel.org>, Maximilian Luz <luzmaximilian@gmail.com>, Sagar Kadam <sagar.kadam@sifive.com>, Drew Fustini <drew@beagleboard.org>, Geert Uytterhoeven <geert@linux-m68k.org>, Michael Zhu <michael.zhu@starfivetech.com>, Fu Wei <tekkamanninja@gmail.com>, Anup Patel <anup.patel@wdc.com>, Atish Patra <atish.patra@wdc.com>, Matteo Croce <mcroce@microsoft.com>, linux-kernel@vger.kernel.org Subject: [PATCH v3 15/16] RISC-V: Add initial StarFive JH7100 device tree Date: Tue, 2 Nov 2021 17:11:24 +0100 [thread overview] Message-ID: <20211102161125.1144023-16-kernel@esmil.dk> (raw) In-Reply-To: <20211102161125.1144023-1-kernel@esmil.dk> Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. The CPU and cache data is based on the device tree in the vendor u-boot port. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 230 +++++++++++++++++++++++ 1 file changed, 230 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi new file mode 100644 index 000000000000..69f22f9aad9d --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2021 StarFive Technology Co., Ltd. + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> + */ + +/dts-v1/; +#include <dt-bindings/clock/starfive-jh7100.h> +#include <dt-bindings/reset/starfive-jh7100.h> + +/ { + compatible = "starfive,jh7100"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + osc_sys: osc_sys { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + osc_aud: osc_aud { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + gmac_rmii_ref: gmac_rmii_ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Should be overridden by the board when needed */ + clock-frequency = <0>; + }; + + gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Should be overridden by the board when needed */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh7100-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; + }; + + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 + &cpu1_intc 11 &cpu1_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + riscv,ndev = <127>; + }; + + clkgen: clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x0 0x11800000 0x0 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; + + rstgen: reset-controller@11840000 { + compatible = "starfive,jh7100-reset"; + reg = <0x0 0x11840000 0x0 0x10000>; + #reset-cells = <1>; + }; + + i2c0: i2c@118b0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x118b0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C0_CORE>, + <&clkgen JH7100_CLK_I2C0_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C0_APB>; + interrupts = <96>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@118c0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x118c0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C1_CORE>, + <&clkgen JH7100_CLK_I2C1_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C1_APB>; + interrupts = <97>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gpio: pinctrl@11910000 { + compatible = "starfive,jh7100-pinctrl"; + reg = <0x0 0x11910000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x1000>; + reg-names = "gpio", "padctl"; + clocks = <&clkgen JH7100_CLK_GPIO_APB>; + resets = <&rstgen JH7100_RSTN_GPIO_APB>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart2: serial@12430000 { + compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; + reg = <0x0 0x12430000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_UART2_CORE>, + <&clkgen JH7100_CLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&rstgen JH7100_RSTN_UART2_APB>; + interrupts = <72>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@12440000 { + compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; + reg = <0x0 0x12440000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_UART3_CORE>, + <&clkgen JH7100_CLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&rstgen JH7100_RSTN_UART3_APB>; + interrupts = <73>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c2: i2c@12450000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12450000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C2_CORE>, + <&clkgen JH7100_CLK_I2C2_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C2_APB>; + interrupts = <74>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@12460000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12460000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C3_CORE>, + <&clkgen JH7100_CLK_I2C3_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C3_APB>; + interrupts = <75>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; -- 2.33.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
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From: Emil Renner Berthing <kernel@esmil.dk> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Cc: Emil Renner Berthing <kernel@esmil.dk>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Linus Walleij <linus.walleij@linaro.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Andy Shevchenko <andriy.shevchenko@linux.intel.com>, Jiri Slaby <jirislaby@kernel.org>, Maximilian Luz <luzmaximilian@gmail.com>, Sagar Kadam <sagar.kadam@sifive.com>, Drew Fustini <drew@beagleboard.org>, Geert Uytterhoeven <geert@linux-m68k.org>, Michael Zhu <michael.zhu@starfivetech.com>, Fu Wei <tekkamanninja@gmail.com>, Anup Patel <anup.patel@wdc.com>, Atish Patra <atish.patra@wdc.com>, Matteo Croce <mcroce@microsoft.com>, linux-kernel@vger.kernel.org Subject: [PATCH v3 15/16] RISC-V: Add initial StarFive JH7100 device tree Date: Tue, 2 Nov 2021 17:11:24 +0100 [thread overview] Message-ID: <20211102161125.1144023-16-kernel@esmil.dk> (raw) In-Reply-To: <20211102161125.1144023-1-kernel@esmil.dk> Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. The CPU and cache data is based on the device tree in the vendor u-boot port. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 230 +++++++++++++++++++++++ 1 file changed, 230 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi new file mode 100644 index 000000000000..69f22f9aad9d --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2021 StarFive Technology Co., Ltd. + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> + */ + +/dts-v1/; +#include <dt-bindings/clock/starfive-jh7100.h> +#include <dt-bindings/reset/starfive-jh7100.h> + +/ { + compatible = "starfive,jh7100"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + osc_sys: osc_sys { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + osc_aud: osc_aud { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + gmac_rmii_ref: gmac_rmii_ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Should be overridden by the board when needed */ + clock-frequency = <0>; + }; + + gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Should be overridden by the board when needed */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh7100-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; + }; + + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 + &cpu1_intc 11 &cpu1_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + riscv,ndev = <127>; + }; + + clkgen: clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x0 0x11800000 0x0 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; + + rstgen: reset-controller@11840000 { + compatible = "starfive,jh7100-reset"; + reg = <0x0 0x11840000 0x0 0x10000>; + #reset-cells = <1>; + }; + + i2c0: i2c@118b0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x118b0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C0_CORE>, + <&clkgen JH7100_CLK_I2C0_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C0_APB>; + interrupts = <96>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@118c0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x118c0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C1_CORE>, + <&clkgen JH7100_CLK_I2C1_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C1_APB>; + interrupts = <97>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gpio: pinctrl@11910000 { + compatible = "starfive,jh7100-pinctrl"; + reg = <0x0 0x11910000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x1000>; + reg-names = "gpio", "padctl"; + clocks = <&clkgen JH7100_CLK_GPIO_APB>; + resets = <&rstgen JH7100_RSTN_GPIO_APB>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart2: serial@12430000 { + compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; + reg = <0x0 0x12430000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_UART2_CORE>, + <&clkgen JH7100_CLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&rstgen JH7100_RSTN_UART2_APB>; + interrupts = <72>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@12440000 { + compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; + reg = <0x0 0x12440000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_UART3_CORE>, + <&clkgen JH7100_CLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&rstgen JH7100_RSTN_UART3_APB>; + interrupts = <73>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c2: i2c@12450000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12450000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C2_CORE>, + <&clkgen JH7100_CLK_I2C2_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C2_APB>; + interrupts = <74>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@12460000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12460000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C3_CORE>, + <&clkgen JH7100_CLK_I2C3_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C3_APB>; + interrupts = <75>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; -- 2.33.1
next prev parent reply other threads:[~2021-11-02 16:13 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-02 16:11 [PATCH v3 00/16] Basic StarFive JH7100 RISC-V SoC support Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 01/16] RISC-V: Add StarFive SoC Kconfig option Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-08 9:24 ` Geert Uytterhoeven 2021-11-08 9:24 ` Geert Uytterhoeven 2021-11-02 16:11 ` [PATCH v3 02/16] dt-bindings: timer: Add StarFive JH7100 clint Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 03/16] dt-bindings: interrupt-controller: Add StarFive JH7100 plic Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 04/16] dt-bindings: clock: starfive: Add JH7100 clock definitions Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 05/16] dt-bindings: clock: starfive: Add JH7100 bindings Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 06/16] clk: starfive: Add JH7100 clock generator driver Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 19:43 ` Andy Shevchenko 2021-11-02 19:43 ` Andy Shevchenko 2021-11-02 16:11 ` [PATCH v3 07/16] dt-bindings: reset: Add StarFive JH7100 reset definitions Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 08/16] dt-bindings: reset: Add Starfive JH7100 reset bindings Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-08 9:25 ` Geert Uytterhoeven 2021-11-08 9:25 ` Geert Uytterhoeven 2021-11-12 19:39 ` Rob Herring 2021-11-12 19:39 ` Rob Herring 2021-11-02 16:11 ` [PATCH v3 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 19:42 ` Andy Shevchenko 2021-11-02 19:42 ` Andy Shevchenko 2021-11-02 19:58 ` Emil Renner Berthing 2021-11-02 19:58 ` Emil Renner Berthing 2021-11-02 20:13 ` Andy Shevchenko 2021-11-02 20:13 ` Andy Shevchenko 2021-11-02 21:17 ` Emil Renner Berthing 2021-11-02 21:17 ` Emil Renner Berthing 2021-11-04 12:15 ` Emil Renner Berthing 2021-11-04 12:15 ` Emil Renner Berthing 2021-11-08 9:17 ` Andy Shevchenko 2021-11-08 9:17 ` Andy Shevchenko 2021-11-09 9:28 ` Emil Renner Berthing 2021-11-09 9:28 ` Emil Renner Berthing 2021-11-02 20:55 ` Yury Norov 2021-11-02 20:55 ` Yury Norov 2021-11-10 16:34 ` Yury Norov 2021-11-10 16:34 ` Yury Norov 2021-11-02 16:11 ` [PATCH v3 10/16] dt-bindings: pinctrl: Add StarFive pinctrl definitions Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-12 19:40 ` Rob Herring 2021-11-12 19:40 ` Rob Herring 2021-11-02 16:11 ` [PATCH v3 11/16] dt-bindings: pinctrl: Add StarFive JH7100 bindings Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-03 1:20 ` Rob Herring 2021-11-03 1:20 ` Rob Herring 2021-11-03 13:30 ` Emil Renner Berthing 2021-11-03 13:30 ` Emil Renner Berthing 2021-11-09 0:45 ` Linus Walleij 2021-11-09 0:45 ` Linus Walleij 2021-11-11 23:04 ` Emil Renner Berthing 2021-11-11 23:04 ` Emil Renner Berthing 2021-11-21 23:19 ` Linus Walleij 2021-11-21 23:19 ` Linus Walleij 2021-11-22 14:02 ` Emil Renner Berthing 2021-11-22 14:02 ` Emil Renner Berthing 2021-11-12 19:41 ` Rob Herring 2021-11-12 19:41 ` Rob Herring 2021-11-02 16:11 ` [PATCH v3 12/16] pinctrl: starfive: Add pinctrl driver for StarFive SoCs Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 20:02 ` Andy Shevchenko 2021-11-02 20:02 ` Andy Shevchenko 2021-11-02 20:07 ` Andy Shevchenko 2021-11-02 20:07 ` Andy Shevchenko 2021-11-09 1:01 ` Linus Walleij 2021-11-09 1:01 ` Linus Walleij 2021-11-09 9:21 ` Emil Renner Berthing 2021-11-09 9:21 ` Emil Renner Berthing 2021-11-09 9:33 ` Andy Shevchenko 2021-11-09 9:33 ` Andy Shevchenko 2021-11-09 9:40 ` Emil Renner Berthing 2021-11-09 9:40 ` Emil Renner Berthing 2021-11-09 20:29 ` Linus Walleij 2021-11-09 20:29 ` Linus Walleij 2021-11-09 21:04 ` Emil Renner Berthing 2021-11-09 21:04 ` Emil Renner Berthing 2021-11-10 8:04 ` Andy Shevchenko 2021-11-10 8:04 ` Andy Shevchenko 2021-11-10 11:15 ` Emil Renner Berthing 2021-11-10 11:15 ` Emil Renner Berthing 2021-11-02 20:35 ` Emil Renner Berthing 2021-11-02 20:35 ` Emil Renner Berthing 2021-11-03 9:12 ` Andy Shevchenko 2021-11-03 9:12 ` Andy Shevchenko 2021-11-03 12:35 ` Emil Renner Berthing 2021-11-03 12:35 ` Emil Renner Berthing 2021-11-03 14:13 ` Andy Shevchenko 2021-11-03 14:13 ` Andy Shevchenko 2021-11-09 0:54 ` Linus Walleij 2021-11-09 0:54 ` Linus Walleij 2021-11-09 8:58 ` Andy Shevchenko 2021-11-09 8:58 ` Andy Shevchenko 2021-11-02 16:11 ` [PATCH v3 13/16] dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 14/16] serial: 8250_dw: Add StarFive JH7100 quirk Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing 2021-11-02 20:14 ` Andy Shevchenko 2021-11-02 20:14 ` Andy Shevchenko 2021-11-08 9:32 ` Geert Uytterhoeven 2021-11-08 9:32 ` Geert Uytterhoeven 2021-11-02 16:11 ` Emil Renner Berthing [this message] 2021-11-02 16:11 ` [PATCH v3 15/16] RISC-V: Add initial StarFive JH7100 device tree Emil Renner Berthing 2021-11-02 16:11 ` [PATCH v3 16/16] RISC-V: Add BeagleV Starlight Beta " Emil Renner Berthing 2021-11-02 16:11 ` Emil Renner Berthing
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