[PATCH igt v2 0/3] msm: Add tests for gpu fault handling

[PATCH igt v2 0/3] msm: Add tests for gpu fault handling

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

The first patch adds a easy way to write debugfs files (needed to
disable hw fault detection, so we can test the sw timeout fallback).
The second adds some helpers for cmdstream building.  And the third
adds the new tests.

v2: Fix headerdoc comments in first patch

Rob Clark (3):
  lib/igt_debugfs: Add helper for writing debugfs files
  msm: Add helper for cmdstream building and submission
  msm: Add recovery tests

 lib/igt_debugfs.c    |  17 +++++
 lib/igt_debugfs.h    |  13 ++++
 lib/igt_msm.c        | 102 +++++++++++++++++++++++++
 lib/igt_msm.h        |  51 +++++++++++++
 tests/meson.build    |   1 +
 tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 356 insertions(+)
 create mode 100644 tests/msm_recovery.c

-- 
2.31.1

[igt-dev] [PATCH igt v2 0/3] msm: Add tests for gpu fault handling

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

The first patch adds a easy way to write debugfs files (needed to
disable hw fault detection, so we can test the sw timeout fallback).
The second adds some helpers for cmdstream building.  And the third
adds the new tests.

v2: Fix headerdoc comments in first patch

Rob Clark (3):
  lib/igt_debugfs: Add helper for writing debugfs files
  msm: Add helper for cmdstream building and submission
  msm: Add recovery tests

 lib/igt_debugfs.c    |  17 +++++
 lib/igt_debugfs.h    |  13 ++++
 lib/igt_msm.c        | 102 +++++++++++++++++++++++++
 lib/igt_msm.h        |  51 +++++++++++++
 tests/meson.build    |   1 +
 tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 356 insertions(+)
 create mode 100644 tests/msm_recovery.c

-- 
2.31.1

[PATCH igt v2 1/3] lib/igt_debugfs: Add helper for writing debugfs files

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

Signed-off-by: Rob Clark <robdclark@chromium.org>
---
v2: Fix headerdoc comments

 lib/igt_debugfs.c | 17 +++++++++++++++++
 lib/igt_debugfs.h | 13 +++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index a5bb95ca..dd6f2995 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -351,6 +351,23 @@ void __igt_debugfs_read(int fd, const char *filename, char *buf, int size)
 	close(dir);
 }
 
+/**
+ * __igt_debugfs_write:
+ * @fd: the drm device file fd
+ * @filename: file name
+ * @buf: buffer to be written to the debugfs file
+ * @size: size of the buffer
+ *
+ * This function opens the debugfs file, writes it, then closes the file.
+ */
+void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size)
+{
+	int dir = igt_debugfs_dir(fd);
+
+	igt_sysfs_write(dir, filename, buf, size);
+	close(dir);
+}
+
 /**
  * igt_debugfs_search:
  * @filename: file name
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index d43ba6c6..b4867681 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -40,6 +40,7 @@ int igt_debugfs_pipe_dir(int device, int pipe, int mode);
 
 int igt_debugfs_open(int fd, const char *filename, int mode);
 void __igt_debugfs_read(int fd, const char *filename, char *buf, int size);
+void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size);
 int igt_debugfs_simple_read(int dir, const char *filename, char *buf, int size);
 bool igt_debugfs_search(int fd, const char *filename, const char *substring);
 
@@ -54,6 +55,18 @@ bool igt_debugfs_search(int fd, const char *filename, const char *substring);
 #define igt_debugfs_read(fd, filename, buf) \
 		__igt_debugfs_read(fd, (filename), (buf), sizeof(buf))
 
+/**
+ * igt_debugfs_write:
+ * @fd: the drm device file fd
+ * @filename: name of the debugfs file
+ * @buf: buffer to be written to the debugfs file
+ *
+ * This is just a convenience wrapper for __igt_debugfs_write. See its
+ * documentation.
+ */
+#define igt_debugfs_write(fd, filename, buf) \
+		__igt_debugfs_write(fd, (filename), (buf), sizeof(buf))
+
 /*
  * Pipe CRC
  */
-- 
2.31.1

[igt-dev] [PATCH igt v2 1/3] lib/igt_debugfs: Add helper for writing debugfs files

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

Signed-off-by: Rob Clark <robdclark@chromium.org>
---
v2: Fix headerdoc comments

 lib/igt_debugfs.c | 17 +++++++++++++++++
 lib/igt_debugfs.h | 13 +++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index a5bb95ca..dd6f2995 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -351,6 +351,23 @@ void __igt_debugfs_read(int fd, const char *filename, char *buf, int size)
 	close(dir);
 }
 
+/**
+ * __igt_debugfs_write:
+ * @fd: the drm device file fd
+ * @filename: file name
+ * @buf: buffer to be written to the debugfs file
+ * @size: size of the buffer
+ *
+ * This function opens the debugfs file, writes it, then closes the file.
+ */
+void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size)
+{
+	int dir = igt_debugfs_dir(fd);
+
+	igt_sysfs_write(dir, filename, buf, size);
+	close(dir);
+}
+
 /**
  * igt_debugfs_search:
  * @filename: file name
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index d43ba6c6..b4867681 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -40,6 +40,7 @@ int igt_debugfs_pipe_dir(int device, int pipe, int mode);
 
 int igt_debugfs_open(int fd, const char *filename, int mode);
 void __igt_debugfs_read(int fd, const char *filename, char *buf, int size);
+void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size);
 int igt_debugfs_simple_read(int dir, const char *filename, char *buf, int size);
 bool igt_debugfs_search(int fd, const char *filename, const char *substring);
 
@@ -54,6 +55,18 @@ bool igt_debugfs_search(int fd, const char *filename, const char *substring);
 #define igt_debugfs_read(fd, filename, buf) \
 		__igt_debugfs_read(fd, (filename), (buf), sizeof(buf))
 
+/**
+ * igt_debugfs_write:
+ * @fd: the drm device file fd
+ * @filename: name of the debugfs file
+ * @buf: buffer to be written to the debugfs file
+ *
+ * This is just a convenience wrapper for __igt_debugfs_write. See its
+ * documentation.
+ */
+#define igt_debugfs_write(fd, filename, buf) \
+		__igt_debugfs_write(fd, (filename), (buf), sizeof(buf))
+
 /*
  * Pipe CRC
  */
-- 
2.31.1

Re: [PATCH igt v2 1/3] lib/igt_debugfs: Add helper for writing debugfs files

[Petri Latvala]

On Wed, Nov 10, 2021 at 10:42:11AM -0800, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>

Reviewed-by: Petri Latvala <petri.latvala@intel.com>


> ---
> v2: Fix headerdoc comments
> 
>  lib/igt_debugfs.c | 17 +++++++++++++++++
>  lib/igt_debugfs.h | 13 +++++++++++++
>  2 files changed, 30 insertions(+)
> 
> diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
> index a5bb95ca..dd6f2995 100644
> --- a/lib/igt_debugfs.c
> +++ b/lib/igt_debugfs.c
> @@ -351,6 +351,23 @@ void __igt_debugfs_read(int fd, const char *filename, char *buf, int size)
>  	close(dir);
>  }
>  
> +/**
> + * __igt_debugfs_write:
> + * @fd: the drm device file fd
> + * @filename: file name
> + * @buf: buffer to be written to the debugfs file
> + * @size: size of the buffer
> + *
> + * This function opens the debugfs file, writes it, then closes the file.
> + */
> +void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size)
> +{
> +	int dir = igt_debugfs_dir(fd);
> +
> +	igt_sysfs_write(dir, filename, buf, size);
> +	close(dir);
> +}
> +
>  /**
>   * igt_debugfs_search:
>   * @filename: file name
> diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
> index d43ba6c6..b4867681 100644
> --- a/lib/igt_debugfs.h
> +++ b/lib/igt_debugfs.h
> @@ -40,6 +40,7 @@ int igt_debugfs_pipe_dir(int device, int pipe, int mode);
>  
>  int igt_debugfs_open(int fd, const char *filename, int mode);
>  void __igt_debugfs_read(int fd, const char *filename, char *buf, int size);
> +void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size);
>  int igt_debugfs_simple_read(int dir, const char *filename, char *buf, int size);
>  bool igt_debugfs_search(int fd, const char *filename, const char *substring);
>  
> @@ -54,6 +55,18 @@ bool igt_debugfs_search(int fd, const char *filename, const char *substring);
>  #define igt_debugfs_read(fd, filename, buf) \
>  		__igt_debugfs_read(fd, (filename), (buf), sizeof(buf))
>  
> +/**
> + * igt_debugfs_write:
> + * @fd: the drm device file fd
> + * @filename: name of the debugfs file
> + * @buf: buffer to be written to the debugfs file
> + *
> + * This is just a convenience wrapper for __igt_debugfs_write. See its
> + * documentation.
> + */
> +#define igt_debugfs_write(fd, filename, buf) \
> +		__igt_debugfs_write(fd, (filename), (buf), sizeof(buf))
> +
>  /*
>   * Pipe CRC
>   */
> -- 
> 2.31.1
> 

Re: [igt-dev] [PATCH igt v2 1/3] lib/igt_debugfs: Add helper for writing debugfs files

[Petri Latvala]

On Wed, Nov 10, 2021 at 10:42:11AM -0800, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>

Reviewed-by: Petri Latvala <petri.latvala@intel.com>


> ---
> v2: Fix headerdoc comments
> 
>  lib/igt_debugfs.c | 17 +++++++++++++++++
>  lib/igt_debugfs.h | 13 +++++++++++++
>  2 files changed, 30 insertions(+)
> 
> diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
> index a5bb95ca..dd6f2995 100644
> --- a/lib/igt_debugfs.c
> +++ b/lib/igt_debugfs.c
> @@ -351,6 +351,23 @@ void __igt_debugfs_read(int fd, const char *filename, char *buf, int size)
>  	close(dir);
>  }
>  
> +/**
> + * __igt_debugfs_write:
> + * @fd: the drm device file fd
> + * @filename: file name
> + * @buf: buffer to be written to the debugfs file
> + * @size: size of the buffer
> + *
> + * This function opens the debugfs file, writes it, then closes the file.
> + */
> +void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size)
> +{
> +	int dir = igt_debugfs_dir(fd);
> +
> +	igt_sysfs_write(dir, filename, buf, size);
> +	close(dir);
> +}
> +
>  /**
>   * igt_debugfs_search:
>   * @filename: file name
> diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
> index d43ba6c6..b4867681 100644
> --- a/lib/igt_debugfs.h
> +++ b/lib/igt_debugfs.h
> @@ -40,6 +40,7 @@ int igt_debugfs_pipe_dir(int device, int pipe, int mode);
>  
>  int igt_debugfs_open(int fd, const char *filename, int mode);
>  void __igt_debugfs_read(int fd, const char *filename, char *buf, int size);
> +void __igt_debugfs_write(int fd, const char *filename, const char *buf, int size);
>  int igt_debugfs_simple_read(int dir, const char *filename, char *buf, int size);
>  bool igt_debugfs_search(int fd, const char *filename, const char *substring);
>  
> @@ -54,6 +55,18 @@ bool igt_debugfs_search(int fd, const char *filename, const char *substring);
>  #define igt_debugfs_read(fd, filename, buf) \
>  		__igt_debugfs_read(fd, (filename), (buf), sizeof(buf))
>  
> +/**
> + * igt_debugfs_write:
> + * @fd: the drm device file fd
> + * @filename: name of the debugfs file
> + * @buf: buffer to be written to the debugfs file
> + *
> + * This is just a convenience wrapper for __igt_debugfs_write. See its
> + * documentation.
> + */
> +#define igt_debugfs_write(fd, filename, buf) \
> +		__igt_debugfs_write(fd, (filename), (buf), sizeof(buf))
> +
>  /*
>   * Pipe CRC
>   */
> -- 
> 2.31.1
> 

[PATCH igt v2 2/3] msm: Add helper for cmdstream building and submission

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

A pretty minimal subset compared to what a full gallium driver would
need, but OTOH for igt tests we should only need to emit fairly basic
command stream.

Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 lib/igt_msm.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_msm.h |  48 ++++++++++++++++++++++++
 2 files changed, 150 insertions(+)

diff --git a/lib/igt_msm.c b/lib/igt_msm.c
index b9534164..e9cf588f 100644
--- a/lib/igt_msm.c
+++ b/lib/igt_msm.c
@@ -91,6 +91,19 @@ igt_msm_dev_close(struct msm_device *dev)
 	free(dev);
 }
 
+static uint64_t
+get_iova(struct msm_bo *bo)
+{
+	struct drm_msm_gem_info req = {
+			.handle = bo->handle,
+			.info = MSM_INFO_GET_IOVA,
+	};
+
+	do_ioctl(bo->dev->fd, DRM_IOCTL_MSM_GEM_INFO, &req);
+
+	return req.value;
+}
+
 /**
  * igt_msm_bo_new:
  * @dev: the device to allocate the BO from
@@ -115,6 +128,7 @@ igt_msm_bo_new(struct msm_device *dev, size_t size, uint32_t flags)
 	do_ioctl(dev->fd, DRM_IOCTL_MSM_GEM_NEW, &req);
 
 	bo->handle = req.handle;
+	bo->iova = get_iova(bo);
 
 	return bo;
 }
@@ -209,3 +223,91 @@ igt_msm_pipe_close(struct msm_pipe *pipe)
 	do_ioctl(pipe->dev->fd, DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE, &pipe->submitqueue_id);
 	free(pipe);
 }
+
+/**
+ * igt_msm_cmd_new:
+ * @pipe: the submitqueue to submit cmdstream against
+ * @size: the size of requested cmdstream buffer
+ */
+struct msm_cmd *
+igt_msm_cmd_new(struct msm_pipe *pipe, size_t size)
+{
+	struct msm_cmd *cmd = calloc(1, sizeof(*cmd));
+
+	cmd->pipe = pipe;
+	cmd->cmdstream_bo = igt_msm_bo_new(pipe->dev, size, MSM_BO_WC);
+	cmd->cur = igt_msm_bo_map(cmd->cmdstream_bo);
+
+	__igt_msm_append_bo(cmd, cmd->cmdstream_bo);
+
+	return cmd;
+}
+
+static uint32_t
+cmdstream_size(struct msm_cmd *cmd)
+{
+	uint8_t *start = igt_msm_bo_map(cmd->cmdstream_bo);
+	return (uint8_t *)cmd->cur - start;
+}
+
+/**
+ * igt_msm_cmd_submit:
+ * @cmd: the command stream object to submit
+ *
+ * Returns dma-fence fd
+ */
+int
+igt_msm_cmd_submit(struct msm_cmd *cmd)
+{
+	struct drm_msm_gem_submit_bo bos[cmd->nr_bos];
+	struct drm_msm_gem_submit_cmd cmds[] = {
+		[0] = {
+			.type       = MSM_SUBMIT_CMD_BUF,
+			.submit_idx = 0,
+			.size       = cmdstream_size(cmd),
+		},
+	};
+	struct drm_msm_gem_submit req = {
+			.flags   = cmd->pipe->pipe | MSM_SUBMIT_FENCE_FD_OUT,
+			.queueid = cmd->pipe->submitqueue_id,
+			.nr_cmds = ARRAY_SIZE(cmds),
+			.cmds    = VOID2U64(cmds),
+			.nr_bos  = ARRAY_SIZE(bos),
+			.bos     = VOID2U64(bos),
+	};
+
+	for (unsigned i = 0; i < cmd->nr_bos; i++) {
+		bos[i] = (struct drm_msm_gem_submit_bo) {
+			.handle  = cmd->bos[i]->handle,
+			.flags   = MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE,
+		};
+	}
+
+	do_ioctl(cmd->pipe->dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req);
+
+	return req.fence_fd;
+}
+
+void
+__igt_msm_append_bo(struct msm_cmd *cmd, struct msm_bo *bo)
+{
+	for (unsigned i = 0; i < cmd->nr_bos; i++)
+		if (cmd->bos[i] == bo)
+			return;
+
+	assert((cmd->nr_bos + 1) < ARRAY_SIZE(cmd->bos));
+	cmd->bos[cmd->nr_bos++] = bo;
+}
+
+/**
+ * igt_msm_cmd_free:
+ * @cmd: the command stream object to free
+ *
+ * Free a command stream object
+ */
+void
+igt_msm_cmd_free(struct msm_cmd *cmd)
+{
+	igt_msm_bo_free(cmd->cmdstream_bo);
+	free(cmd);
+}
diff --git a/lib/igt_msm.h b/lib/igt_msm.h
index 99a099c1..1a66c806 100644
--- a/lib/igt_msm.h
+++ b/lib/igt_msm.h
@@ -24,6 +24,8 @@
 #ifndef IGT_MSM_H
 #define IGT_MSM_H
 
+#include "ioctl_wrappers.h"
+
 #include "msm_drm.h"
 
 /**
@@ -47,6 +49,7 @@ void igt_msm_dev_close(struct msm_device *dev);
  * @handle: the BO's GEM handle
  * @size: the BO's size
  * @map: the BO's memory mapping (if mapped)
+ * @iova: the BO's GPU address
  *
  * Helper wrapper for a GEM buffer object.
  */
@@ -55,6 +58,7 @@ struct msm_bo {
 	int handle;
 	uint32_t size;
 	void *map;
+	uint64_t iova;
 };
 
 struct msm_bo *igt_msm_bo_new(struct msm_device *dev, size_t size, uint32_t flags);
@@ -136,6 +140,50 @@ pm4_pkt7_hdr(uint8_t opcode, uint16_t cnt)
 			((pm4_odd_parity_bit(opcode) << 23));
 }
 
+/**
+ * msm_cmd:
+ * @pipe: the submitqueue to submit cmdstream against
+ * @cmdstream_bo: the backing cmdstream buffer object
+ * @cur: pointer to current position in cmdstream
+ *
+ * Helper for building cmdstream and cmdstream submission
+ */
+struct msm_cmd {
+	struct msm_pipe *pipe;
+	struct msm_bo *cmdstream_bo;
+	uint32_t *cur;
+	uint32_t nr_bos;
+	struct msm_bo *bos[8];
+};
+
+struct msm_cmd *igt_msm_cmd_new(struct msm_pipe *pipe, size_t size);
+int igt_msm_cmd_submit(struct msm_cmd *cmd);
+void igt_msm_cmd_free(struct msm_cmd *cmd);
+
+static inline void
+msm_cmd_emit(struct msm_cmd *cmd, uint32_t dword)
+{
+	*(cmd->cur++) = dword;
+}
+
+static inline void
+msm_cmd_pkt7(struct msm_cmd *cmd, uint8_t opcode, uint16_t cnt)
+{
+	msm_cmd_emit(cmd, pm4_pkt7_hdr(opcode, cnt));
+}
+
+void __igt_msm_append_bo(struct msm_cmd *cmd, struct msm_bo *bo);
+
+static inline void
+msm_cmd_bo(struct msm_cmd *cmd, struct msm_bo *bo, uint32_t offset)
+{
+	uint64_t addr = bo->iova + offset;
+
+	__igt_msm_append_bo(cmd, bo);
+	msm_cmd_emit(cmd, lower_32_bits(addr));
+	msm_cmd_emit(cmd, upper_32_bits(addr));
+}
+
 #define U642VOID(x) ((void *)(uintptr_t)(x))
 #define VOID2U64(x) ((uint64_t)(uintptr_t)(x))
 
-- 
2.31.1

[igt-dev] [PATCH igt v2 2/3] msm: Add helper for cmdstream building and submission

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

A pretty minimal subset compared to what a full gallium driver would
need, but OTOH for igt tests we should only need to emit fairly basic
command stream.

Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 lib/igt_msm.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_msm.h |  48 ++++++++++++++++++++++++
 2 files changed, 150 insertions(+)

diff --git a/lib/igt_msm.c b/lib/igt_msm.c
index b9534164..e9cf588f 100644
--- a/lib/igt_msm.c
+++ b/lib/igt_msm.c
@@ -91,6 +91,19 @@ igt_msm_dev_close(struct msm_device *dev)
 	free(dev);
 }
 
+static uint64_t
+get_iova(struct msm_bo *bo)
+{
+	struct drm_msm_gem_info req = {
+			.handle = bo->handle,
+			.info = MSM_INFO_GET_IOVA,
+	};
+
+	do_ioctl(bo->dev->fd, DRM_IOCTL_MSM_GEM_INFO, &req);
+
+	return req.value;
+}
+
 /**
  * igt_msm_bo_new:
  * @dev: the device to allocate the BO from
@@ -115,6 +128,7 @@ igt_msm_bo_new(struct msm_device *dev, size_t size, uint32_t flags)
 	do_ioctl(dev->fd, DRM_IOCTL_MSM_GEM_NEW, &req);
 
 	bo->handle = req.handle;
+	bo->iova = get_iova(bo);
 
 	return bo;
 }
@@ -209,3 +223,91 @@ igt_msm_pipe_close(struct msm_pipe *pipe)
 	do_ioctl(pipe->dev->fd, DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE, &pipe->submitqueue_id);
 	free(pipe);
 }
+
+/**
+ * igt_msm_cmd_new:
+ * @pipe: the submitqueue to submit cmdstream against
+ * @size: the size of requested cmdstream buffer
+ */
+struct msm_cmd *
+igt_msm_cmd_new(struct msm_pipe *pipe, size_t size)
+{
+	struct msm_cmd *cmd = calloc(1, sizeof(*cmd));
+
+	cmd->pipe = pipe;
+	cmd->cmdstream_bo = igt_msm_bo_new(pipe->dev, size, MSM_BO_WC);
+	cmd->cur = igt_msm_bo_map(cmd->cmdstream_bo);
+
+	__igt_msm_append_bo(cmd, cmd->cmdstream_bo);
+
+	return cmd;
+}
+
+static uint32_t
+cmdstream_size(struct msm_cmd *cmd)
+{
+	uint8_t *start = igt_msm_bo_map(cmd->cmdstream_bo);
+	return (uint8_t *)cmd->cur - start;
+}
+
+/**
+ * igt_msm_cmd_submit:
+ * @cmd: the command stream object to submit
+ *
+ * Returns dma-fence fd
+ */
+int
+igt_msm_cmd_submit(struct msm_cmd *cmd)
+{
+	struct drm_msm_gem_submit_bo bos[cmd->nr_bos];
+	struct drm_msm_gem_submit_cmd cmds[] = {
+		[0] = {
+			.type       = MSM_SUBMIT_CMD_BUF,
+			.submit_idx = 0,
+			.size       = cmdstream_size(cmd),
+		},
+	};
+	struct drm_msm_gem_submit req = {
+			.flags   = cmd->pipe->pipe | MSM_SUBMIT_FENCE_FD_OUT,
+			.queueid = cmd->pipe->submitqueue_id,
+			.nr_cmds = ARRAY_SIZE(cmds),
+			.cmds    = VOID2U64(cmds),
+			.nr_bos  = ARRAY_SIZE(bos),
+			.bos     = VOID2U64(bos),
+	};
+
+	for (unsigned i = 0; i < cmd->nr_bos; i++) {
+		bos[i] = (struct drm_msm_gem_submit_bo) {
+			.handle  = cmd->bos[i]->handle,
+			.flags   = MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE,
+		};
+	}
+
+	do_ioctl(cmd->pipe->dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req);
+
+	return req.fence_fd;
+}
+
+void
+__igt_msm_append_bo(struct msm_cmd *cmd, struct msm_bo *bo)
+{
+	for (unsigned i = 0; i < cmd->nr_bos; i++)
+		if (cmd->bos[i] == bo)
+			return;
+
+	assert((cmd->nr_bos + 1) < ARRAY_SIZE(cmd->bos));
+	cmd->bos[cmd->nr_bos++] = bo;
+}
+
+/**
+ * igt_msm_cmd_free:
+ * @cmd: the command stream object to free
+ *
+ * Free a command stream object
+ */
+void
+igt_msm_cmd_free(struct msm_cmd *cmd)
+{
+	igt_msm_bo_free(cmd->cmdstream_bo);
+	free(cmd);
+}
diff --git a/lib/igt_msm.h b/lib/igt_msm.h
index 99a099c1..1a66c806 100644
--- a/lib/igt_msm.h
+++ b/lib/igt_msm.h
@@ -24,6 +24,8 @@
 #ifndef IGT_MSM_H
 #define IGT_MSM_H
 
+#include "ioctl_wrappers.h"
+
 #include "msm_drm.h"
 
 /**
@@ -47,6 +49,7 @@ void igt_msm_dev_close(struct msm_device *dev);
  * @handle: the BO's GEM handle
  * @size: the BO's size
  * @map: the BO's memory mapping (if mapped)
+ * @iova: the BO's GPU address
  *
  * Helper wrapper for a GEM buffer object.
  */
@@ -55,6 +58,7 @@ struct msm_bo {
 	int handle;
 	uint32_t size;
 	void *map;
+	uint64_t iova;
 };
 
 struct msm_bo *igt_msm_bo_new(struct msm_device *dev, size_t size, uint32_t flags);
@@ -136,6 +140,50 @@ pm4_pkt7_hdr(uint8_t opcode, uint16_t cnt)
 			((pm4_odd_parity_bit(opcode) << 23));
 }
 
+/**
+ * msm_cmd:
+ * @pipe: the submitqueue to submit cmdstream against
+ * @cmdstream_bo: the backing cmdstream buffer object
+ * @cur: pointer to current position in cmdstream
+ *
+ * Helper for building cmdstream and cmdstream submission
+ */
+struct msm_cmd {
+	struct msm_pipe *pipe;
+	struct msm_bo *cmdstream_bo;
+	uint32_t *cur;
+	uint32_t nr_bos;
+	struct msm_bo *bos[8];
+};
+
+struct msm_cmd *igt_msm_cmd_new(struct msm_pipe *pipe, size_t size);
+int igt_msm_cmd_submit(struct msm_cmd *cmd);
+void igt_msm_cmd_free(struct msm_cmd *cmd);
+
+static inline void
+msm_cmd_emit(struct msm_cmd *cmd, uint32_t dword)
+{
+	*(cmd->cur++) = dword;
+}
+
+static inline void
+msm_cmd_pkt7(struct msm_cmd *cmd, uint8_t opcode, uint16_t cnt)
+{
+	msm_cmd_emit(cmd, pm4_pkt7_hdr(opcode, cnt));
+}
+
+void __igt_msm_append_bo(struct msm_cmd *cmd, struct msm_bo *bo);
+
+static inline void
+msm_cmd_bo(struct msm_cmd *cmd, struct msm_bo *bo, uint32_t offset)
+{
+	uint64_t addr = bo->iova + offset;
+
+	__igt_msm_append_bo(cmd, bo);
+	msm_cmd_emit(cmd, lower_32_bits(addr));
+	msm_cmd_emit(cmd, upper_32_bits(addr));
+}
+
 #define U642VOID(x) ((void *)(uintptr_t)(x))
 #define VOID2U64(x) ((uint64_t)(uintptr_t)(x))
 
-- 
2.31.1

[PATCH igt v2 3/3] msm: Add recovery tests

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

Add tests to exercise:

1. sw hangcheck timeout
2. gpu fault (hang) recovery
3. iova fault recovery

Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 lib/igt_msm.h        |   3 +
 tests/meson.build    |   1 +
 tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 176 insertions(+)
 create mode 100644 tests/msm_recovery.c

diff --git a/lib/igt_msm.h b/lib/igt_msm.h
index 1a66c806..421d23ed 100644
--- a/lib/igt_msm.h
+++ b/lib/igt_msm.h
@@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
 
 enum adreno_pm4_type3_packets {
 	CP_NOP = 16,
+	CP_WAIT_MEM_GTE = 20,
+	CP_WAIT_REG_MEM = 60,
+	CP_MEM_WRITE = 61,
 };
 
 static inline unsigned
diff --git a/tests/meson.build b/tests/meson.build
index 0af3e03a..166e3494 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -60,6 +60,7 @@ test_progs = [
 	'kms_vrr',
 	'kms_writeback',
 	'meta_test',
+	'msm_recovery',
 	'msm_submit',
 	'panfrost_get_param',
 	'panfrost_gem_new',
diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
new file mode 100644
index 00000000..b71326b8
--- /dev/null
+++ b/tests/msm_recovery.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright © 2021 Google, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <sys/poll.h>
+
+#include "igt.h"
+#include "igt_msm.h"
+
+static struct msm_device *dev;
+static struct msm_bo *scratch_bo;
+static uint32_t *scratch;
+
+/*
+ * Helpers for cmdstream packet building:
+ */
+
+static void
+wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
+{
+	msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
+	msm_cmd_emit(cmd, 0);                              /* RESERVED */
+	msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
+	msm_cmd_emit(cmd, ref);                            /* REF */
+}
+
+static void
+mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
+{
+	msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
+	msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
+	msm_cmd_emit(cmd, val);                            /* VAL */
+}
+
+/*
+ * Helper to wait on a fence-fd:
+ */
+static void
+wait_and_close(int fence_fd)
+{
+	poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
+	close(fence_fd);
+}
+
+/*
+ * Helper for hang tests.  Emits multiple submits, with one in the middle
+ * that triggers a fault, and confirms that the submits before and after
+ * the faulting one execute properly, ie. that the driver properly manages
+ * to recover and re-queue the submits after the faulting submit;
+ */
+static void
+do_hang_test(struct msm_pipe *pipe)
+{
+	struct msm_cmd *cmds[16];
+	int fence_fds[ARRAY_SIZE(cmds)];
+
+	memset(scratch, 0, 0x1000);
+
+	for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
+		struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
+
+		cmds[i] = cmd;
+
+		/*
+		 * Emit a packet to wait for scratch[0] to be >= 1
+		 *
+		 * This lets us force the GPU to wait until all the cmdstream is
+		 * queued up.
+		 */
+		wait_mem_gte(cmd, 0, 1);
+
+		if (i == 10) {
+			msm_cmd_emit(cmd, 0xdeaddead);
+		}
+
+		/* Emit a packet to write scratch[1+i] = 2+i: */
+		mem_write(cmd, 1+i, 2+i);
+	}
+
+	for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
+		fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
+	}
+
+	usleep(10000);
+
+	/* Let the WAIT_MEM_GTE complete: */
+	scratch[0] = 1;
+
+	for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
+		wait_and_close(fence_fds[i]);
+		igt_msm_cmd_free(cmds[i]);
+		if (i == 10)
+			continue;
+		igt_assert_eq(scratch[1+i], 2+i);
+	}
+}
+
+/*
+ * Tests for drm/msm hangcheck, recovery, and fault handling
+ */
+
+igt_main
+{
+	static struct msm_pipe *pipe = NULL;
+
+	igt_fixture {
+		dev = igt_msm_dev_open();
+		pipe = igt_msm_pipe_open(dev, 0);
+		scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
+		scratch = igt_msm_bo_map(scratch_bo);
+	}
+
+	igt_describe("Test sw hangcheck handling");
+	igt_subtest("hangcheck") {
+		igt_require(dev->gen >= 6);
+
+		/* Disable hw hang detection to force fallback to sw hangcheck: */
+		igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
+
+		do_hang_test(pipe);
+
+		igt_debugfs_write(dev->fd, "disable_err_irq", "N");
+	}
+
+	igt_describe("Test hw fault handling");
+	igt_subtest("gpu-fault") {
+		igt_require(dev->gen >= 6);
+
+		do_hang_test(pipe);
+	}
+
+	igt_describe("Test iova fault handling");
+	igt_subtest("iova-fault") {
+		struct msm_cmd *cmd;
+
+		igt_require(dev->gen >= 6);
+
+		cmd = igt_msm_cmd_new(pipe, 0x1000);
+
+		msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
+		msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
+		msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
+		msm_cmd_emit(cmd, 0x123);                /* VAL */
+
+		wait_and_close(igt_msm_cmd_submit(cmd));
+	}
+
+	igt_fixture {
+		igt_msm_bo_free(scratch_bo);
+		igt_msm_pipe_close(pipe);
+		igt_msm_dev_close(dev);
+	}
+}
-- 
2.31.1

[igt-dev] [PATCH igt v2 3/3] msm: Add recovery tests

[Rob Clark]

From: Rob Clark <robdclark@chromium.org>

Add tests to exercise:

1. sw hangcheck timeout
2. gpu fault (hang) recovery
3. iova fault recovery

Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 lib/igt_msm.h        |   3 +
 tests/meson.build    |   1 +
 tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 176 insertions(+)
 create mode 100644 tests/msm_recovery.c

diff --git a/lib/igt_msm.h b/lib/igt_msm.h
index 1a66c806..421d23ed 100644
--- a/lib/igt_msm.h
+++ b/lib/igt_msm.h
@@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
 
 enum adreno_pm4_type3_packets {
 	CP_NOP = 16,
+	CP_WAIT_MEM_GTE = 20,
+	CP_WAIT_REG_MEM = 60,
+	CP_MEM_WRITE = 61,
 };
 
 static inline unsigned
diff --git a/tests/meson.build b/tests/meson.build
index 0af3e03a..166e3494 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -60,6 +60,7 @@ test_progs = [
 	'kms_vrr',
 	'kms_writeback',
 	'meta_test',
+	'msm_recovery',
 	'msm_submit',
 	'panfrost_get_param',
 	'panfrost_gem_new',
diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
new file mode 100644
index 00000000..b71326b8
--- /dev/null
+++ b/tests/msm_recovery.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright © 2021 Google, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <sys/poll.h>
+
+#include "igt.h"
+#include "igt_msm.h"
+
+static struct msm_device *dev;
+static struct msm_bo *scratch_bo;
+static uint32_t *scratch;
+
+/*
+ * Helpers for cmdstream packet building:
+ */
+
+static void
+wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
+{
+	msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
+	msm_cmd_emit(cmd, 0);                              /* RESERVED */
+	msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
+	msm_cmd_emit(cmd, ref);                            /* REF */
+}
+
+static void
+mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
+{
+	msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
+	msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
+	msm_cmd_emit(cmd, val);                            /* VAL */
+}
+
+/*
+ * Helper to wait on a fence-fd:
+ */
+static void
+wait_and_close(int fence_fd)
+{
+	poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
+	close(fence_fd);
+}
+
+/*
+ * Helper for hang tests.  Emits multiple submits, with one in the middle
+ * that triggers a fault, and confirms that the submits before and after
+ * the faulting one execute properly, ie. that the driver properly manages
+ * to recover and re-queue the submits after the faulting submit;
+ */
+static void
+do_hang_test(struct msm_pipe *pipe)
+{
+	struct msm_cmd *cmds[16];
+	int fence_fds[ARRAY_SIZE(cmds)];
+
+	memset(scratch, 0, 0x1000);
+
+	for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
+		struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
+
+		cmds[i] = cmd;
+
+		/*
+		 * Emit a packet to wait for scratch[0] to be >= 1
+		 *
+		 * This lets us force the GPU to wait until all the cmdstream is
+		 * queued up.
+		 */
+		wait_mem_gte(cmd, 0, 1);
+
+		if (i == 10) {
+			msm_cmd_emit(cmd, 0xdeaddead);
+		}
+
+		/* Emit a packet to write scratch[1+i] = 2+i: */
+		mem_write(cmd, 1+i, 2+i);
+	}
+
+	for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
+		fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
+	}
+
+	usleep(10000);
+
+	/* Let the WAIT_MEM_GTE complete: */
+	scratch[0] = 1;
+
+	for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
+		wait_and_close(fence_fds[i]);
+		igt_msm_cmd_free(cmds[i]);
+		if (i == 10)
+			continue;
+		igt_assert_eq(scratch[1+i], 2+i);
+	}
+}
+
+/*
+ * Tests for drm/msm hangcheck, recovery, and fault handling
+ */
+
+igt_main
+{
+	static struct msm_pipe *pipe = NULL;
+
+	igt_fixture {
+		dev = igt_msm_dev_open();
+		pipe = igt_msm_pipe_open(dev, 0);
+		scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
+		scratch = igt_msm_bo_map(scratch_bo);
+	}
+
+	igt_describe("Test sw hangcheck handling");
+	igt_subtest("hangcheck") {
+		igt_require(dev->gen >= 6);
+
+		/* Disable hw hang detection to force fallback to sw hangcheck: */
+		igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
+
+		do_hang_test(pipe);
+
+		igt_debugfs_write(dev->fd, "disable_err_irq", "N");
+	}
+
+	igt_describe("Test hw fault handling");
+	igt_subtest("gpu-fault") {
+		igt_require(dev->gen >= 6);
+
+		do_hang_test(pipe);
+	}
+
+	igt_describe("Test iova fault handling");
+	igt_subtest("iova-fault") {
+		struct msm_cmd *cmd;
+
+		igt_require(dev->gen >= 6);
+
+		cmd = igt_msm_cmd_new(pipe, 0x1000);
+
+		msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
+		msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
+		msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
+		msm_cmd_emit(cmd, 0x123);                /* VAL */
+
+		wait_and_close(igt_msm_cmd_submit(cmd));
+	}
+
+	igt_fixture {
+		igt_msm_bo_free(scratch_bo);
+		igt_msm_pipe_close(pipe);
+		igt_msm_dev_close(dev);
+	}
+}
-- 
2.31.1

Re: [PATCH igt v2 3/3] msm: Add recovery tests

[Rob Clark]

On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Add tests to exercise:
>
> 1. sw hangcheck timeout
> 2. gpu fault (hang) recovery
> 3. iova fault recovery
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
>  lib/igt_msm.h        |   3 +
>  tests/meson.build    |   1 +
>  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 176 insertions(+)
>  create mode 100644 tests/msm_recovery.c
>
> diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> index 1a66c806..421d23ed 100644
> --- a/lib/igt_msm.h
> +++ b/lib/igt_msm.h
> @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
>
>  enum adreno_pm4_type3_packets {
>         CP_NOP = 16,
> +       CP_WAIT_MEM_GTE = 20,
> +       CP_WAIT_REG_MEM = 60,
> +       CP_MEM_WRITE = 61,
>  };
>
>  static inline unsigned
> diff --git a/tests/meson.build b/tests/meson.build
> index 0af3e03a..166e3494 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -60,6 +60,7 @@ test_progs = [
>         'kms_vrr',
>         'kms_writeback',
>         'meta_test',
> +       'msm_recovery',
>         'msm_submit',
>         'panfrost_get_param',
>         'panfrost_gem_new',
> diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> new file mode 100644
> index 00000000..b71326b8
> --- /dev/null
> +++ b/tests/msm_recovery.c
> @@ -0,0 +1,172 @@
> +/*
> + * Copyright © 2021 Google, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include <sys/poll.h>
> +
> +#include "igt.h"
> +#include "igt_msm.h"
> +
> +static struct msm_device *dev;
> +static struct msm_bo *scratch_bo;
> +static uint32_t *scratch;
> +
> +/*
> + * Helpers for cmdstream packet building:
> + */
> +
> +static void
> +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> +{
> +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> +       msm_cmd_emit(cmd, ref);                            /* REF */
> +}
> +
> +static void
> +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> +{
> +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> +       msm_cmd_emit(cmd, val);                            /* VAL */
> +}
> +
> +/*
> + * Helper to wait on a fence-fd:
> + */
> +static void
> +wait_and_close(int fence_fd)
> +{
> +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> +       close(fence_fd);
> +}
> +
> +/*
> + * Helper for hang tests.  Emits multiple submits, with one in the middle
> + * that triggers a fault, and confirms that the submits before and after
> + * the faulting one execute properly, ie. that the driver properly manages
> + * to recover and re-queue the submits after the faulting submit;
> + */
> +static void
> +do_hang_test(struct msm_pipe *pipe)
> +{
> +       struct msm_cmd *cmds[16];
> +       int fence_fds[ARRAY_SIZE(cmds)];
> +
> +       memset(scratch, 0, 0x1000);
> +
> +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> +
> +               cmds[i] = cmd;
> +
> +               /*
> +                * Emit a packet to wait for scratch[0] to be >= 1
> +                *
> +                * This lets us force the GPU to wait until all the cmdstream is
> +                * queued up.
> +                */
> +               wait_mem_gte(cmd, 0, 1);
> +
> +               if (i == 10) {
> +                       msm_cmd_emit(cmd, 0xdeaddead);
> +               }
> +
> +               /* Emit a packet to write scratch[1+i] = 2+i: */
> +               mem_write(cmd, 1+i, 2+i);
> +       }
> +
> +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> +       }
> +
> +       usleep(10000);
> +
> +       /* Let the WAIT_MEM_GTE complete: */
> +       scratch[0] = 1;
> +
> +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> +               wait_and_close(fence_fds[i]);
> +               igt_msm_cmd_free(cmds[i]);
> +               if (i == 10)
> +                       continue;
> +               igt_assert_eq(scratch[1+i], 2+i);
> +       }
> +}
> +
> +/*
> + * Tests for drm/msm hangcheck, recovery, and fault handling
> + */
> +
> +igt_main
> +{
> +       static struct msm_pipe *pipe = NULL;
> +
> +       igt_fixture {
> +               dev = igt_msm_dev_open();
> +               pipe = igt_msm_pipe_open(dev, 0);
> +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> +               scratch = igt_msm_bo_map(scratch_bo);
> +       }
> +
> +       igt_describe("Test sw hangcheck handling");
> +       igt_subtest("hangcheck") {
> +               igt_require(dev->gen >= 6);
> +
> +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");

note that this depends on [1].. not sure if there is any constraint
about landing igt tests before some debugfs they depend on lands
upstream on the kernel side?

[1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1

BR,
-R

> +
> +               do_hang_test(pipe);
> +
> +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> +       }
> +
> +       igt_describe("Test hw fault handling");
> +       igt_subtest("gpu-fault") {
> +               igt_require(dev->gen >= 6);
> +
> +               do_hang_test(pipe);
> +       }
> +
> +       igt_describe("Test iova fault handling");
> +       igt_subtest("iova-fault") {
> +               struct msm_cmd *cmd;
> +
> +               igt_require(dev->gen >= 6);
> +
> +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> +
> +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> +
> +               wait_and_close(igt_msm_cmd_submit(cmd));
> +       }
> +
> +       igt_fixture {
> +               igt_msm_bo_free(scratch_bo);
> +               igt_msm_pipe_close(pipe);
> +               igt_msm_dev_close(dev);
> +       }
> +}
> --
> 2.31.1
>

Re: [igt-dev] [PATCH igt v2 3/3] msm: Add recovery tests

[Rob Clark]

On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Add tests to exercise:
>
> 1. sw hangcheck timeout
> 2. gpu fault (hang) recovery
> 3. iova fault recovery
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
>  lib/igt_msm.h        |   3 +
>  tests/meson.build    |   1 +
>  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 176 insertions(+)
>  create mode 100644 tests/msm_recovery.c
>
> diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> index 1a66c806..421d23ed 100644
> --- a/lib/igt_msm.h
> +++ b/lib/igt_msm.h
> @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
>
>  enum adreno_pm4_type3_packets {
>         CP_NOP = 16,
> +       CP_WAIT_MEM_GTE = 20,
> +       CP_WAIT_REG_MEM = 60,
> +       CP_MEM_WRITE = 61,
>  };
>
>  static inline unsigned
> diff --git a/tests/meson.build b/tests/meson.build
> index 0af3e03a..166e3494 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -60,6 +60,7 @@ test_progs = [
>         'kms_vrr',
>         'kms_writeback',
>         'meta_test',
> +       'msm_recovery',
>         'msm_submit',
>         'panfrost_get_param',
>         'panfrost_gem_new',
> diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> new file mode 100644
> index 00000000..b71326b8
> --- /dev/null
> +++ b/tests/msm_recovery.c
> @@ -0,0 +1,172 @@
> +/*
> + * Copyright © 2021 Google, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include <sys/poll.h>
> +
> +#include "igt.h"
> +#include "igt_msm.h"
> +
> +static struct msm_device *dev;
> +static struct msm_bo *scratch_bo;
> +static uint32_t *scratch;
> +
> +/*
> + * Helpers for cmdstream packet building:
> + */
> +
> +static void
> +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> +{
> +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> +       msm_cmd_emit(cmd, ref);                            /* REF */
> +}
> +
> +static void
> +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> +{
> +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> +       msm_cmd_emit(cmd, val);                            /* VAL */
> +}
> +
> +/*
> + * Helper to wait on a fence-fd:
> + */
> +static void
> +wait_and_close(int fence_fd)
> +{
> +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> +       close(fence_fd);
> +}
> +
> +/*
> + * Helper for hang tests.  Emits multiple submits, with one in the middle
> + * that triggers a fault, and confirms that the submits before and after
> + * the faulting one execute properly, ie. that the driver properly manages
> + * to recover and re-queue the submits after the faulting submit;
> + */
> +static void
> +do_hang_test(struct msm_pipe *pipe)
> +{
> +       struct msm_cmd *cmds[16];
> +       int fence_fds[ARRAY_SIZE(cmds)];
> +
> +       memset(scratch, 0, 0x1000);
> +
> +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> +
> +               cmds[i] = cmd;
> +
> +               /*
> +                * Emit a packet to wait for scratch[0] to be >= 1
> +                *
> +                * This lets us force the GPU to wait until all the cmdstream is
> +                * queued up.
> +                */
> +               wait_mem_gte(cmd, 0, 1);
> +
> +               if (i == 10) {
> +                       msm_cmd_emit(cmd, 0xdeaddead);
> +               }
> +
> +               /* Emit a packet to write scratch[1+i] = 2+i: */
> +               mem_write(cmd, 1+i, 2+i);
> +       }
> +
> +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> +       }
> +
> +       usleep(10000);
> +
> +       /* Let the WAIT_MEM_GTE complete: */
> +       scratch[0] = 1;
> +
> +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> +               wait_and_close(fence_fds[i]);
> +               igt_msm_cmd_free(cmds[i]);
> +               if (i == 10)
> +                       continue;
> +               igt_assert_eq(scratch[1+i], 2+i);
> +       }
> +}
> +
> +/*
> + * Tests for drm/msm hangcheck, recovery, and fault handling
> + */
> +
> +igt_main
> +{
> +       static struct msm_pipe *pipe = NULL;
> +
> +       igt_fixture {
> +               dev = igt_msm_dev_open();
> +               pipe = igt_msm_pipe_open(dev, 0);
> +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> +               scratch = igt_msm_bo_map(scratch_bo);
> +       }
> +
> +       igt_describe("Test sw hangcheck handling");
> +       igt_subtest("hangcheck") {
> +               igt_require(dev->gen >= 6);
> +
> +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");

note that this depends on [1].. not sure if there is any constraint
about landing igt tests before some debugfs they depend on lands
upstream on the kernel side?

[1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1

BR,
-R

> +
> +               do_hang_test(pipe);
> +
> +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> +       }
> +
> +       igt_describe("Test hw fault handling");
> +       igt_subtest("gpu-fault") {
> +               igt_require(dev->gen >= 6);
> +
> +               do_hang_test(pipe);
> +       }
> +
> +       igt_describe("Test iova fault handling");
> +       igt_subtest("iova-fault") {
> +               struct msm_cmd *cmd;
> +
> +               igt_require(dev->gen >= 6);
> +
> +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> +
> +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> +
> +               wait_and_close(igt_msm_cmd_submit(cmd));
> +       }
> +
> +       igt_fixture {
> +               igt_msm_bo_free(scratch_bo);
> +               igt_msm_pipe_close(pipe);
> +               igt_msm_dev_close(dev);
> +       }
> +}
> --
> 2.31.1
>

Re: [PATCH igt v2 3/3] msm: Add recovery tests

[Petri Latvala]

On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
> >
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Add tests to exercise:
> >
> > 1. sw hangcheck timeout
> > 2. gpu fault (hang) recovery
> > 3. iova fault recovery
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> >  lib/igt_msm.h        |   3 +
> >  tests/meson.build    |   1 +
> >  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 176 insertions(+)
> >  create mode 100644 tests/msm_recovery.c
> >
> > diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> > index 1a66c806..421d23ed 100644
> > --- a/lib/igt_msm.h
> > +++ b/lib/igt_msm.h
> > @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
> >
> >  enum adreno_pm4_type3_packets {
> >         CP_NOP = 16,
> > +       CP_WAIT_MEM_GTE = 20,
> > +       CP_WAIT_REG_MEM = 60,
> > +       CP_MEM_WRITE = 61,
> >  };
> >
> >  static inline unsigned
> > diff --git a/tests/meson.build b/tests/meson.build
> > index 0af3e03a..166e3494 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -60,6 +60,7 @@ test_progs = [
> >         'kms_vrr',
> >         'kms_writeback',
> >         'meta_test',
> > +       'msm_recovery',
> >         'msm_submit',
> >         'panfrost_get_param',
> >         'panfrost_gem_new',
> > diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> > new file mode 100644
> > index 00000000..b71326b8
> > --- /dev/null
> > +++ b/tests/msm_recovery.c
> > @@ -0,0 +1,172 @@
> > +/*
> > + * Copyright © 2021 Google, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the next
> > + * paragraph) shall be included in all copies or substantial portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include <sys/poll.h>
> > +
> > +#include "igt.h"
> > +#include "igt_msm.h"
> > +
> > +static struct msm_device *dev;
> > +static struct msm_bo *scratch_bo;
> > +static uint32_t *scratch;
> > +
> > +/*
> > + * Helpers for cmdstream packet building:
> > + */
> > +
> > +static void
> > +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> > +{
> > +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> > +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> > +       msm_cmd_emit(cmd, ref);                            /* REF */
> > +}
> > +
> > +static void
> > +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> > +{
> > +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> > +       msm_cmd_emit(cmd, val);                            /* VAL */
> > +}
> > +
> > +/*
> > + * Helper to wait on a fence-fd:
> > + */
> > +static void
> > +wait_and_close(int fence_fd)
> > +{
> > +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> > +       close(fence_fd);
> > +}
> > +
> > +/*
> > + * Helper for hang tests.  Emits multiple submits, with one in the middle
> > + * that triggers a fault, and confirms that the submits before and after
> > + * the faulting one execute properly, ie. that the driver properly manages
> > + * to recover and re-queue the submits after the faulting submit;
> > + */
> > +static void
> > +do_hang_test(struct msm_pipe *pipe)
> > +{
> > +       struct msm_cmd *cmds[16];
> > +       int fence_fds[ARRAY_SIZE(cmds)];
> > +
> > +       memset(scratch, 0, 0x1000);
> > +
> > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> > +
> > +               cmds[i] = cmd;
> > +
> > +               /*
> > +                * Emit a packet to wait for scratch[0] to be >= 1
> > +                *
> > +                * This lets us force the GPU to wait until all the cmdstream is
> > +                * queued up.
> > +                */
> > +               wait_mem_gte(cmd, 0, 1);
> > +
> > +               if (i == 10) {
> > +                       msm_cmd_emit(cmd, 0xdeaddead);
> > +               }
> > +
> > +               /* Emit a packet to write scratch[1+i] = 2+i: */
> > +               mem_write(cmd, 1+i, 2+i);
> > +       }
> > +
> > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> > +       }
> > +
> > +       usleep(10000);
> > +
> > +       /* Let the WAIT_MEM_GTE complete: */
> > +       scratch[0] = 1;
> > +
> > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > +               wait_and_close(fence_fds[i]);
> > +               igt_msm_cmd_free(cmds[i]);
> > +               if (i == 10)
> > +                       continue;
> > +               igt_assert_eq(scratch[1+i], 2+i);
> > +       }
> > +}
> > +
> > +/*
> > + * Tests for drm/msm hangcheck, recovery, and fault handling
> > + */
> > +
> > +igt_main
> > +{
> > +       static struct msm_pipe *pipe = NULL;
> > +
> > +       igt_fixture {
> > +               dev = igt_msm_dev_open();
> > +               pipe = igt_msm_pipe_open(dev, 0);
> > +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> > +               scratch = igt_msm_bo_map(scratch_bo);
> > +       }
> > +
> > +       igt_describe("Test sw hangcheck handling");
> > +       igt_subtest("hangcheck") {
> > +               igt_require(dev->gen >= 6);
> > +
> > +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> > +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
> 
> note that this depends on [1].. not sure if there is any constraint
> about landing igt tests before some debugfs they depend on lands
> upstream on the kernel side?
> 
> [1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1

The usual ordering dependency of kernel vs userspace, where both sides
are reviewed and ready to go before anything lands. But then the
actual merging with IGT is not so strict, IGT can go in first as long
as there's a consensus that the required kernel changes are going in
in finite time.

That said, IGT is supposed to do the right thing for kernels some time
back, especially LTS kernels, so this test needs to properly handle
the debugfs file missing regardless of merging order.

Some kind of igt_require check for the debugfs file takes care of
that.


-- 
Petri Latvala




> 
> BR,
> -R
> 
> > +
> > +               do_hang_test(pipe);
> > +
> > +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> > +       }
> > +
> > +       igt_describe("Test hw fault handling");
> > +       igt_subtest("gpu-fault") {
> > +               igt_require(dev->gen >= 6);
> > +
> > +               do_hang_test(pipe);
> > +       }
> > +
> > +       igt_describe("Test iova fault handling");
> > +       igt_subtest("iova-fault") {
> > +               struct msm_cmd *cmd;
> > +
> > +               igt_require(dev->gen >= 6);
> > +
> > +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> > +
> > +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> > +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> > +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> > +
> > +               wait_and_close(igt_msm_cmd_submit(cmd));
> > +       }
> > +
> > +       igt_fixture {
> > +               igt_msm_bo_free(scratch_bo);
> > +               igt_msm_pipe_close(pipe);
> > +               igt_msm_dev_close(dev);
> > +       }
> > +}
> > --
> > 2.31.1
> >

Re: [igt-dev] [PATCH igt v2 3/3] msm: Add recovery tests

[Petri Latvala]

On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
> >
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Add tests to exercise:
> >
> > 1. sw hangcheck timeout
> > 2. gpu fault (hang) recovery
> > 3. iova fault recovery
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> >  lib/igt_msm.h        |   3 +
> >  tests/meson.build    |   1 +
> >  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 176 insertions(+)
> >  create mode 100644 tests/msm_recovery.c
> >
> > diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> > index 1a66c806..421d23ed 100644
> > --- a/lib/igt_msm.h
> > +++ b/lib/igt_msm.h
> > @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
> >
> >  enum adreno_pm4_type3_packets {
> >         CP_NOP = 16,
> > +       CP_WAIT_MEM_GTE = 20,
> > +       CP_WAIT_REG_MEM = 60,
> > +       CP_MEM_WRITE = 61,
> >  };
> >
> >  static inline unsigned
> > diff --git a/tests/meson.build b/tests/meson.build
> > index 0af3e03a..166e3494 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -60,6 +60,7 @@ test_progs = [
> >         'kms_vrr',
> >         'kms_writeback',
> >         'meta_test',
> > +       'msm_recovery',
> >         'msm_submit',
> >         'panfrost_get_param',
> >         'panfrost_gem_new',
> > diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> > new file mode 100644
> > index 00000000..b71326b8
> > --- /dev/null
> > +++ b/tests/msm_recovery.c
> > @@ -0,0 +1,172 @@
> > +/*
> > + * Copyright © 2021 Google, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the next
> > + * paragraph) shall be included in all copies or substantial portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include <sys/poll.h>
> > +
> > +#include "igt.h"
> > +#include "igt_msm.h"
> > +
> > +static struct msm_device *dev;
> > +static struct msm_bo *scratch_bo;
> > +static uint32_t *scratch;
> > +
> > +/*
> > + * Helpers for cmdstream packet building:
> > + */
> > +
> > +static void
> > +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> > +{
> > +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> > +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> > +       msm_cmd_emit(cmd, ref);                            /* REF */
> > +}
> > +
> > +static void
> > +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> > +{
> > +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> > +       msm_cmd_emit(cmd, val);                            /* VAL */
> > +}
> > +
> > +/*
> > + * Helper to wait on a fence-fd:
> > + */
> > +static void
> > +wait_and_close(int fence_fd)
> > +{
> > +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> > +       close(fence_fd);
> > +}
> > +
> > +/*
> > + * Helper for hang tests.  Emits multiple submits, with one in the middle
> > + * that triggers a fault, and confirms that the submits before and after
> > + * the faulting one execute properly, ie. that the driver properly manages
> > + * to recover and re-queue the submits after the faulting submit;
> > + */
> > +static void
> > +do_hang_test(struct msm_pipe *pipe)
> > +{
> > +       struct msm_cmd *cmds[16];
> > +       int fence_fds[ARRAY_SIZE(cmds)];
> > +
> > +       memset(scratch, 0, 0x1000);
> > +
> > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> > +
> > +               cmds[i] = cmd;
> > +
> > +               /*
> > +                * Emit a packet to wait for scratch[0] to be >= 1
> > +                *
> > +                * This lets us force the GPU to wait until all the cmdstream is
> > +                * queued up.
> > +                */
> > +               wait_mem_gte(cmd, 0, 1);
> > +
> > +               if (i == 10) {
> > +                       msm_cmd_emit(cmd, 0xdeaddead);
> > +               }
> > +
> > +               /* Emit a packet to write scratch[1+i] = 2+i: */
> > +               mem_write(cmd, 1+i, 2+i);
> > +       }
> > +
> > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> > +       }
> > +
> > +       usleep(10000);
> > +
> > +       /* Let the WAIT_MEM_GTE complete: */
> > +       scratch[0] = 1;
> > +
> > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > +               wait_and_close(fence_fds[i]);
> > +               igt_msm_cmd_free(cmds[i]);
> > +               if (i == 10)
> > +                       continue;
> > +               igt_assert_eq(scratch[1+i], 2+i);
> > +       }
> > +}
> > +
> > +/*
> > + * Tests for drm/msm hangcheck, recovery, and fault handling
> > + */
> > +
> > +igt_main
> > +{
> > +       static struct msm_pipe *pipe = NULL;
> > +
> > +       igt_fixture {
> > +               dev = igt_msm_dev_open();
> > +               pipe = igt_msm_pipe_open(dev, 0);
> > +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> > +               scratch = igt_msm_bo_map(scratch_bo);
> > +       }
> > +
> > +       igt_describe("Test sw hangcheck handling");
> > +       igt_subtest("hangcheck") {
> > +               igt_require(dev->gen >= 6);
> > +
> > +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> > +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
> 
> note that this depends on [1].. not sure if there is any constraint
> about landing igt tests before some debugfs they depend on lands
> upstream on the kernel side?
> 
> [1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1

The usual ordering dependency of kernel vs userspace, where both sides
are reviewed and ready to go before anything lands. But then the
actual merging with IGT is not so strict, IGT can go in first as long
as there's a consensus that the required kernel changes are going in
in finite time.

That said, IGT is supposed to do the right thing for kernels some time
back, especially LTS kernels, so this test needs to properly handle
the debugfs file missing regardless of merging order.

Some kind of igt_require check for the debugfs file takes care of
that.


-- 
Petri Latvala




> 
> BR,
> -R
> 
> > +
> > +               do_hang_test(pipe);
> > +
> > +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> > +       }
> > +
> > +       igt_describe("Test hw fault handling");
> > +       igt_subtest("gpu-fault") {
> > +               igt_require(dev->gen >= 6);
> > +
> > +               do_hang_test(pipe);
> > +       }
> > +
> > +       igt_describe("Test iova fault handling");
> > +       igt_subtest("iova-fault") {
> > +               struct msm_cmd *cmd;
> > +
> > +               igt_require(dev->gen >= 6);
> > +
> > +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> > +
> > +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> > +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> > +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> > +
> > +               wait_and_close(igt_msm_cmd_submit(cmd));
> > +       }
> > +
> > +       igt_fixture {
> > +               igt_msm_bo_free(scratch_bo);
> > +               igt_msm_pipe_close(pipe);
> > +               igt_msm_dev_close(dev);
> > +       }
> > +}
> > --
> > 2.31.1
> >

Re: [PATCH igt v2 3/3] msm: Add recovery tests

[Rob Clark]

On Thu, Nov 11, 2021 at 4:13 AM Petri Latvala <petri.latvala@intel.com> wrote:
>
> On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> > On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
> > >
> > > From: Rob Clark <robdclark@chromium.org>
> > >
> > > Add tests to exercise:
> > >
> > > 1. sw hangcheck timeout
> > > 2. gpu fault (hang) recovery
> > > 3. iova fault recovery
> > >
> > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > ---
> > >  lib/igt_msm.h        |   3 +
> > >  tests/meson.build    |   1 +
> > >  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 176 insertions(+)
> > >  create mode 100644 tests/msm_recovery.c
> > >
> > > diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> > > index 1a66c806..421d23ed 100644
> > > --- a/lib/igt_msm.h
> > > +++ b/lib/igt_msm.h
> > > @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
> > >
> > >  enum adreno_pm4_type3_packets {
> > >         CP_NOP = 16,
> > > +       CP_WAIT_MEM_GTE = 20,
> > > +       CP_WAIT_REG_MEM = 60,
> > > +       CP_MEM_WRITE = 61,
> > >  };
> > >
> > >  static inline unsigned
> > > diff --git a/tests/meson.build b/tests/meson.build
> > > index 0af3e03a..166e3494 100644
> > > --- a/tests/meson.build
> > > +++ b/tests/meson.build
> > > @@ -60,6 +60,7 @@ test_progs = [
> > >         'kms_vrr',
> > >         'kms_writeback',
> > >         'meta_test',
> > > +       'msm_recovery',
> > >         'msm_submit',
> > >         'panfrost_get_param',
> > >         'panfrost_gem_new',
> > > diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> > > new file mode 100644
> > > index 00000000..b71326b8
> > > --- /dev/null
> > > +++ b/tests/msm_recovery.c
> > > @@ -0,0 +1,172 @@
> > > +/*
> > > + * Copyright © 2021 Google, Inc.
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > + * copy of this software and associated documentation files (the "Software"),
> > > + * to deal in the Software without restriction, including without limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > + * Software is furnished to do so, subject to the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice (including the next
> > > + * paragraph) shall be included in all copies or substantial portions of the
> > > + * Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > + * IN THE SOFTWARE.
> > > + */
> > > +
> > > +#include <sys/poll.h>
> > > +
> > > +#include "igt.h"
> > > +#include "igt_msm.h"
> > > +
> > > +static struct msm_device *dev;
> > > +static struct msm_bo *scratch_bo;
> > > +static uint32_t *scratch;
> > > +
> > > +/*
> > > + * Helpers for cmdstream packet building:
> > > + */
> > > +
> > > +static void
> > > +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> > > +{
> > > +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> > > +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> > > +       msm_cmd_emit(cmd, ref);                            /* REF */
> > > +}
> > > +
> > > +static void
> > > +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> > > +{
> > > +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> > > +       msm_cmd_emit(cmd, val);                            /* VAL */
> > > +}
> > > +
> > > +/*
> > > + * Helper to wait on a fence-fd:
> > > + */
> > > +static void
> > > +wait_and_close(int fence_fd)
> > > +{
> > > +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> > > +       close(fence_fd);
> > > +}
> > > +
> > > +/*
> > > + * Helper for hang tests.  Emits multiple submits, with one in the middle
> > > + * that triggers a fault, and confirms that the submits before and after
> > > + * the faulting one execute properly, ie. that the driver properly manages
> > > + * to recover and re-queue the submits after the faulting submit;
> > > + */
> > > +static void
> > > +do_hang_test(struct msm_pipe *pipe)
> > > +{
> > > +       struct msm_cmd *cmds[16];
> > > +       int fence_fds[ARRAY_SIZE(cmds)];
> > > +
> > > +       memset(scratch, 0, 0x1000);
> > > +
> > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > +
> > > +               cmds[i] = cmd;
> > > +
> > > +               /*
> > > +                * Emit a packet to wait for scratch[0] to be >= 1
> > > +                *
> > > +                * This lets us force the GPU to wait until all the cmdstream is
> > > +                * queued up.
> > > +                */
> > > +               wait_mem_gte(cmd, 0, 1);
> > > +
> > > +               if (i == 10) {
> > > +                       msm_cmd_emit(cmd, 0xdeaddead);
> > > +               }
> > > +
> > > +               /* Emit a packet to write scratch[1+i] = 2+i: */
> > > +               mem_write(cmd, 1+i, 2+i);
> > > +       }
> > > +
> > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> > > +       }
> > > +
> > > +       usleep(10000);
> > > +
> > > +       /* Let the WAIT_MEM_GTE complete: */
> > > +       scratch[0] = 1;
> > > +
> > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > +               wait_and_close(fence_fds[i]);
> > > +               igt_msm_cmd_free(cmds[i]);
> > > +               if (i == 10)
> > > +                       continue;
> > > +               igt_assert_eq(scratch[1+i], 2+i);
> > > +       }
> > > +}
> > > +
> > > +/*
> > > + * Tests for drm/msm hangcheck, recovery, and fault handling
> > > + */
> > > +
> > > +igt_main
> > > +{
> > > +       static struct msm_pipe *pipe = NULL;
> > > +
> > > +       igt_fixture {
> > > +               dev = igt_msm_dev_open();
> > > +               pipe = igt_msm_pipe_open(dev, 0);
> > > +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> > > +               scratch = igt_msm_bo_map(scratch_bo);
> > > +       }
> > > +
> > > +       igt_describe("Test sw hangcheck handling");
> > > +       igt_subtest("hangcheck") {
> > > +               igt_require(dev->gen >= 6);
> > > +
> > > +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
> >
> > note that this depends on [1].. not sure if there is any constraint
> > about landing igt tests before some debugfs they depend on lands
> > upstream on the kernel side?
> >
> > [1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1
>
> The usual ordering dependency of kernel vs userspace, where both sides
> are reviewed and ready to go before anything lands. But then the
> actual merging with IGT is not so strict, IGT can go in first as long
> as there's a consensus that the required kernel changes are going in
> in finite time.
>
> That said, IGT is supposed to do the right thing for kernels some time
> back, especially LTS kernels, so this test needs to properly handle
> the debugfs file missing regardless of merging order.
>
> Some kind of igt_require check for the debugfs file takes care of
> that.
>

Hmm, unless I'm overlooking something, I guess we need a helper to
check for the existence of a debugfs file?

BR,
-R

>
> --
> Petri Latvala
>
>
>
>
> >
> > BR,
> > -R
> >
> > > +
> > > +               do_hang_test(pipe);
> > > +
> > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> > > +       }
> > > +
> > > +       igt_describe("Test hw fault handling");
> > > +       igt_subtest("gpu-fault") {
> > > +               igt_require(dev->gen >= 6);
> > > +
> > > +               do_hang_test(pipe);
> > > +       }
> > > +
> > > +       igt_describe("Test iova fault handling");
> > > +       igt_subtest("iova-fault") {
> > > +               struct msm_cmd *cmd;
> > > +
> > > +               igt_require(dev->gen >= 6);
> > > +
> > > +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > +
> > > +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> > > +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> > > +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> > > +
> > > +               wait_and_close(igt_msm_cmd_submit(cmd));
> > > +       }
> > > +
> > > +       igt_fixture {
> > > +               igt_msm_bo_free(scratch_bo);
> > > +               igt_msm_pipe_close(pipe);
> > > +               igt_msm_dev_close(dev);
> > > +       }
> > > +}
> > > --
> > > 2.31.1
> > >

Re: [igt-dev] [PATCH igt v2 3/3] msm: Add recovery tests

[Rob Clark]

On Thu, Nov 11, 2021 at 4:13 AM Petri Latvala <petri.latvala@intel.com> wrote:
>
> On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> > On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
> > >
> > > From: Rob Clark <robdclark@chromium.org>
> > >
> > > Add tests to exercise:
> > >
> > > 1. sw hangcheck timeout
> > > 2. gpu fault (hang) recovery
> > > 3. iova fault recovery
> > >
> > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > ---
> > >  lib/igt_msm.h        |   3 +
> > >  tests/meson.build    |   1 +
> > >  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 176 insertions(+)
> > >  create mode 100644 tests/msm_recovery.c
> > >
> > > diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> > > index 1a66c806..421d23ed 100644
> > > --- a/lib/igt_msm.h
> > > +++ b/lib/igt_msm.h
> > > @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
> > >
> > >  enum adreno_pm4_type3_packets {
> > >         CP_NOP = 16,
> > > +       CP_WAIT_MEM_GTE = 20,
> > > +       CP_WAIT_REG_MEM = 60,
> > > +       CP_MEM_WRITE = 61,
> > >  };
> > >
> > >  static inline unsigned
> > > diff --git a/tests/meson.build b/tests/meson.build
> > > index 0af3e03a..166e3494 100644
> > > --- a/tests/meson.build
> > > +++ b/tests/meson.build
> > > @@ -60,6 +60,7 @@ test_progs = [
> > >         'kms_vrr',
> > >         'kms_writeback',
> > >         'meta_test',
> > > +       'msm_recovery',
> > >         'msm_submit',
> > >         'panfrost_get_param',
> > >         'panfrost_gem_new',
> > > diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> > > new file mode 100644
> > > index 00000000..b71326b8
> > > --- /dev/null
> > > +++ b/tests/msm_recovery.c
> > > @@ -0,0 +1,172 @@
> > > +/*
> > > + * Copyright © 2021 Google, Inc.
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > + * copy of this software and associated documentation files (the "Software"),
> > > + * to deal in the Software without restriction, including without limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > + * Software is furnished to do so, subject to the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice (including the next
> > > + * paragraph) shall be included in all copies or substantial portions of the
> > > + * Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > + * IN THE SOFTWARE.
> > > + */
> > > +
> > > +#include <sys/poll.h>
> > > +
> > > +#include "igt.h"
> > > +#include "igt_msm.h"
> > > +
> > > +static struct msm_device *dev;
> > > +static struct msm_bo *scratch_bo;
> > > +static uint32_t *scratch;
> > > +
> > > +/*
> > > + * Helpers for cmdstream packet building:
> > > + */
> > > +
> > > +static void
> > > +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> > > +{
> > > +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> > > +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> > > +       msm_cmd_emit(cmd, ref);                            /* REF */
> > > +}
> > > +
> > > +static void
> > > +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> > > +{
> > > +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> > > +       msm_cmd_emit(cmd, val);                            /* VAL */
> > > +}
> > > +
> > > +/*
> > > + * Helper to wait on a fence-fd:
> > > + */
> > > +static void
> > > +wait_and_close(int fence_fd)
> > > +{
> > > +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> > > +       close(fence_fd);
> > > +}
> > > +
> > > +/*
> > > + * Helper for hang tests.  Emits multiple submits, with one in the middle
> > > + * that triggers a fault, and confirms that the submits before and after
> > > + * the faulting one execute properly, ie. that the driver properly manages
> > > + * to recover and re-queue the submits after the faulting submit;
> > > + */
> > > +static void
> > > +do_hang_test(struct msm_pipe *pipe)
> > > +{
> > > +       struct msm_cmd *cmds[16];
> > > +       int fence_fds[ARRAY_SIZE(cmds)];
> > > +
> > > +       memset(scratch, 0, 0x1000);
> > > +
> > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > +
> > > +               cmds[i] = cmd;
> > > +
> > > +               /*
> > > +                * Emit a packet to wait for scratch[0] to be >= 1
> > > +                *
> > > +                * This lets us force the GPU to wait until all the cmdstream is
> > > +                * queued up.
> > > +                */
> > > +               wait_mem_gte(cmd, 0, 1);
> > > +
> > > +               if (i == 10) {
> > > +                       msm_cmd_emit(cmd, 0xdeaddead);
> > > +               }
> > > +
> > > +               /* Emit a packet to write scratch[1+i] = 2+i: */
> > > +               mem_write(cmd, 1+i, 2+i);
> > > +       }
> > > +
> > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> > > +       }
> > > +
> > > +       usleep(10000);
> > > +
> > > +       /* Let the WAIT_MEM_GTE complete: */
> > > +       scratch[0] = 1;
> > > +
> > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > +               wait_and_close(fence_fds[i]);
> > > +               igt_msm_cmd_free(cmds[i]);
> > > +               if (i == 10)
> > > +                       continue;
> > > +               igt_assert_eq(scratch[1+i], 2+i);
> > > +       }
> > > +}
> > > +
> > > +/*
> > > + * Tests for drm/msm hangcheck, recovery, and fault handling
> > > + */
> > > +
> > > +igt_main
> > > +{
> > > +       static struct msm_pipe *pipe = NULL;
> > > +
> > > +       igt_fixture {
> > > +               dev = igt_msm_dev_open();
> > > +               pipe = igt_msm_pipe_open(dev, 0);
> > > +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> > > +               scratch = igt_msm_bo_map(scratch_bo);
> > > +       }
> > > +
> > > +       igt_describe("Test sw hangcheck handling");
> > > +       igt_subtest("hangcheck") {
> > > +               igt_require(dev->gen >= 6);
> > > +
> > > +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
> >
> > note that this depends on [1].. not sure if there is any constraint
> > about landing igt tests before some debugfs they depend on lands
> > upstream on the kernel side?
> >
> > [1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1
>
> The usual ordering dependency of kernel vs userspace, where both sides
> are reviewed and ready to go before anything lands. But then the
> actual merging with IGT is not so strict, IGT can go in first as long
> as there's a consensus that the required kernel changes are going in
> in finite time.
>
> That said, IGT is supposed to do the right thing for kernels some time
> back, especially LTS kernels, so this test needs to properly handle
> the debugfs file missing regardless of merging order.
>
> Some kind of igt_require check for the debugfs file takes care of
> that.
>

Hmm, unless I'm overlooking something, I guess we need a helper to
check for the existence of a debugfs file?

BR,
-R

>
> --
> Petri Latvala
>
>
>
>
> >
> > BR,
> > -R
> >
> > > +
> > > +               do_hang_test(pipe);
> > > +
> > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> > > +       }
> > > +
> > > +       igt_describe("Test hw fault handling");
> > > +       igt_subtest("gpu-fault") {
> > > +               igt_require(dev->gen >= 6);
> > > +
> > > +               do_hang_test(pipe);
> > > +       }
> > > +
> > > +       igt_describe("Test iova fault handling");
> > > +       igt_subtest("iova-fault") {
> > > +               struct msm_cmd *cmd;
> > > +
> > > +               igt_require(dev->gen >= 6);
> > > +
> > > +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > +
> > > +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> > > +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> > > +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> > > +
> > > +               wait_and_close(igt_msm_cmd_submit(cmd));
> > > +       }
> > > +
> > > +       igt_fixture {
> > > +               igt_msm_bo_free(scratch_bo);
> > > +               igt_msm_pipe_close(pipe);
> > > +               igt_msm_dev_close(dev);
> > > +       }
> > > +}
> > > --
> > > 2.31.1
> > >

Re: [PATCH igt v2 3/3] msm: Add recovery tests

[Petri Latvala]

On Thu, Nov 11, 2021 at 09:35:16AM -0800, Rob Clark wrote:
> On Thu, Nov 11, 2021 at 4:13 AM Petri Latvala <petri.latvala@intel.com> wrote:
> >
> > On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> > > On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
> > > >
> > > > From: Rob Clark <robdclark@chromium.org>
> > > >
> > > > Add tests to exercise:
> > > >
> > > > 1. sw hangcheck timeout
> > > > 2. gpu fault (hang) recovery
> > > > 3. iova fault recovery
> > > >
> > > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > ---
> > > >  lib/igt_msm.h        |   3 +
> > > >  tests/meson.build    |   1 +
> > > >  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
> > > >  3 files changed, 176 insertions(+)
> > > >  create mode 100644 tests/msm_recovery.c
> > > >
> > > > diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> > > > index 1a66c806..421d23ed 100644
> > > > --- a/lib/igt_msm.h
> > > > +++ b/lib/igt_msm.h
> > > > @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
> > > >
> > > >  enum adreno_pm4_type3_packets {
> > > >         CP_NOP = 16,
> > > > +       CP_WAIT_MEM_GTE = 20,
> > > > +       CP_WAIT_REG_MEM = 60,
> > > > +       CP_MEM_WRITE = 61,
> > > >  };
> > > >
> > > >  static inline unsigned
> > > > diff --git a/tests/meson.build b/tests/meson.build
> > > > index 0af3e03a..166e3494 100644
> > > > --- a/tests/meson.build
> > > > +++ b/tests/meson.build
> > > > @@ -60,6 +60,7 @@ test_progs = [
> > > >         'kms_vrr',
> > > >         'kms_writeback',
> > > >         'meta_test',
> > > > +       'msm_recovery',
> > > >         'msm_submit',
> > > >         'panfrost_get_param',
> > > >         'panfrost_gem_new',
> > > > diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> > > > new file mode 100644
> > > > index 00000000..b71326b8
> > > > --- /dev/null
> > > > +++ b/tests/msm_recovery.c
> > > > @@ -0,0 +1,172 @@
> > > > +/*
> > > > + * Copyright © 2021 Google, Inc.
> > > > + *
> > > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > > + * copy of this software and associated documentation files (the "Software"),
> > > > + * to deal in the Software without restriction, including without limitation
> > > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > > + * Software is furnished to do so, subject to the following conditions:
> > > > + *
> > > > + * The above copyright notice and this permission notice (including the next
> > > > + * paragraph) shall be included in all copies or substantial portions of the
> > > > + * Software.
> > > > + *
> > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > > + * IN THE SOFTWARE.
> > > > + */
> > > > +
> > > > +#include <sys/poll.h>
> > > > +
> > > > +#include "igt.h"
> > > > +#include "igt_msm.h"
> > > > +
> > > > +static struct msm_device *dev;
> > > > +static struct msm_bo *scratch_bo;
> > > > +static uint32_t *scratch;
> > > > +
> > > > +/*
> > > > + * Helpers for cmdstream packet building:
> > > > + */
> > > > +
> > > > +static void
> > > > +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> > > > +{
> > > > +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> > > > +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> > > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> > > > +       msm_cmd_emit(cmd, ref);                            /* REF */
> > > > +}
> > > > +
> > > > +static void
> > > > +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> > > > +{
> > > > +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> > > > +       msm_cmd_emit(cmd, val);                            /* VAL */
> > > > +}
> > > > +
> > > > +/*
> > > > + * Helper to wait on a fence-fd:
> > > > + */
> > > > +static void
> > > > +wait_and_close(int fence_fd)
> > > > +{
> > > > +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> > > > +       close(fence_fd);
> > > > +}
> > > > +
> > > > +/*
> > > > + * Helper for hang tests.  Emits multiple submits, with one in the middle
> > > > + * that triggers a fault, and confirms that the submits before and after
> > > > + * the faulting one execute properly, ie. that the driver properly manages
> > > > + * to recover and re-queue the submits after the faulting submit;
> > > > + */
> > > > +static void
> > > > +do_hang_test(struct msm_pipe *pipe)
> > > > +{
> > > > +       struct msm_cmd *cmds[16];
> > > > +       int fence_fds[ARRAY_SIZE(cmds)];
> > > > +
> > > > +       memset(scratch, 0, 0x1000);
> > > > +
> > > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > > +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > > +
> > > > +               cmds[i] = cmd;
> > > > +
> > > > +               /*
> > > > +                * Emit a packet to wait for scratch[0] to be >= 1
> > > > +                *
> > > > +                * This lets us force the GPU to wait until all the cmdstream is
> > > > +                * queued up.
> > > > +                */
> > > > +               wait_mem_gte(cmd, 0, 1);
> > > > +
> > > > +               if (i == 10) {
> > > > +                       msm_cmd_emit(cmd, 0xdeaddead);
> > > > +               }
> > > > +
> > > > +               /* Emit a packet to write scratch[1+i] = 2+i: */
> > > > +               mem_write(cmd, 1+i, 2+i);
> > > > +       }
> > > > +
> > > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > > +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> > > > +       }
> > > > +
> > > > +       usleep(10000);
> > > > +
> > > > +       /* Let the WAIT_MEM_GTE complete: */
> > > > +       scratch[0] = 1;
> > > > +
> > > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > > +               wait_and_close(fence_fds[i]);
> > > > +               igt_msm_cmd_free(cmds[i]);
> > > > +               if (i == 10)
> > > > +                       continue;
> > > > +               igt_assert_eq(scratch[1+i], 2+i);
> > > > +       }
> > > > +}
> > > > +
> > > > +/*
> > > > + * Tests for drm/msm hangcheck, recovery, and fault handling
> > > > + */
> > > > +
> > > > +igt_main
> > > > +{
> > > > +       static struct msm_pipe *pipe = NULL;
> > > > +
> > > > +       igt_fixture {
> > > > +               dev = igt_msm_dev_open();
> > > > +               pipe = igt_msm_pipe_open(dev, 0);
> > > > +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> > > > +               scratch = igt_msm_bo_map(scratch_bo);
> > > > +       }
> > > > +
> > > > +       igt_describe("Test sw hangcheck handling");
> > > > +       igt_subtest("hangcheck") {
> > > > +               igt_require(dev->gen >= 6);
> > > > +
> > > > +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> > > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
> > >
> > > note that this depends on [1].. not sure if there is any constraint
> > > about landing igt tests before some debugfs they depend on lands
> > > upstream on the kernel side?
> > >
> > > [1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1
> >
> > The usual ordering dependency of kernel vs userspace, where both sides
> > are reviewed and ready to go before anything lands. But then the
> > actual merging with IGT is not so strict, IGT can go in first as long
> > as there's a consensus that the required kernel changes are going in
> > in finite time.
> >
> > That said, IGT is supposed to do the right thing for kernels some time
> > back, especially LTS kernels, so this test needs to properly handle
> > the debugfs file missing regardless of merging order.
> >
> > Some kind of igt_require check for the debugfs file takes care of
> > that.
> >
> 
> Hmm, unless I'm overlooking something, I guess we need a helper to
> check for the existence of a debugfs file?

Yeah =(

Unless the file supports reading.


-- 
Petri Latvala


> 
> BR,
> -R
> 
> >
> > --
> > Petri Latvala
> >
> >
> >
> >
> > >
> > > BR,
> > > -R
> > >
> > > > +
> > > > +               do_hang_test(pipe);
> > > > +
> > > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> > > > +       }
> > > > +
> > > > +       igt_describe("Test hw fault handling");
> > > > +       igt_subtest("gpu-fault") {
> > > > +               igt_require(dev->gen >= 6);
> > > > +
> > > > +               do_hang_test(pipe);
> > > > +       }
> > > > +
> > > > +       igt_describe("Test iova fault handling");
> > > > +       igt_subtest("iova-fault") {
> > > > +               struct msm_cmd *cmd;
> > > > +
> > > > +               igt_require(dev->gen >= 6);
> > > > +
> > > > +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > > +
> > > > +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > > +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> > > > +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> > > > +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> > > > +
> > > > +               wait_and_close(igt_msm_cmd_submit(cmd));
> > > > +       }
> > > > +
> > > > +       igt_fixture {
> > > > +               igt_msm_bo_free(scratch_bo);
> > > > +               igt_msm_pipe_close(pipe);
> > > > +               igt_msm_dev_close(dev);
> > > > +       }
> > > > +}
> > > > --
> > > > 2.31.1
> > > >

Re: [igt-dev] [PATCH igt v2 3/3] msm: Add recovery tests

[Petri Latvala]

On Thu, Nov 11, 2021 at 09:35:16AM -0800, Rob Clark wrote:
> On Thu, Nov 11, 2021 at 4:13 AM Petri Latvala <petri.latvala@intel.com> wrote:
> >
> > On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> > > On Wed, Nov 10, 2021 at 10:37 AM Rob Clark <robdclark@gmail.com> wrote:
> > > >
> > > > From: Rob Clark <robdclark@chromium.org>
> > > >
> > > > Add tests to exercise:
> > > >
> > > > 1. sw hangcheck timeout
> > > > 2. gpu fault (hang) recovery
> > > > 3. iova fault recovery
> > > >
> > > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > ---
> > > >  lib/igt_msm.h        |   3 +
> > > >  tests/meson.build    |   1 +
> > > >  tests/msm_recovery.c | 172 +++++++++++++++++++++++++++++++++++++++++++
> > > >  3 files changed, 176 insertions(+)
> > > >  create mode 100644 tests/msm_recovery.c
> > > >
> > > > diff --git a/lib/igt_msm.h b/lib/igt_msm.h
> > > > index 1a66c806..421d23ed 100644
> > > > --- a/lib/igt_msm.h
> > > > +++ b/lib/igt_msm.h
> > > > @@ -97,6 +97,9 @@ enum adreno_pm4_packet_type {
> > > >
> > > >  enum adreno_pm4_type3_packets {
> > > >         CP_NOP = 16,
> > > > +       CP_WAIT_MEM_GTE = 20,
> > > > +       CP_WAIT_REG_MEM = 60,
> > > > +       CP_MEM_WRITE = 61,
> > > >  };
> > > >
> > > >  static inline unsigned
> > > > diff --git a/tests/meson.build b/tests/meson.build
> > > > index 0af3e03a..166e3494 100644
> > > > --- a/tests/meson.build
> > > > +++ b/tests/meson.build
> > > > @@ -60,6 +60,7 @@ test_progs = [
> > > >         'kms_vrr',
> > > >         'kms_writeback',
> > > >         'meta_test',
> > > > +       'msm_recovery',
> > > >         'msm_submit',
> > > >         'panfrost_get_param',
> > > >         'panfrost_gem_new',
> > > > diff --git a/tests/msm_recovery.c b/tests/msm_recovery.c
> > > > new file mode 100644
> > > > index 00000000..b71326b8
> > > > --- /dev/null
> > > > +++ b/tests/msm_recovery.c
> > > > @@ -0,0 +1,172 @@
> > > > +/*
> > > > + * Copyright © 2021 Google, Inc.
> > > > + *
> > > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > > + * copy of this software and associated documentation files (the "Software"),
> > > > + * to deal in the Software without restriction, including without limitation
> > > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > > + * Software is furnished to do so, subject to the following conditions:
> > > > + *
> > > > + * The above copyright notice and this permission notice (including the next
> > > > + * paragraph) shall be included in all copies or substantial portions of the
> > > > + * Software.
> > > > + *
> > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > > + * IN THE SOFTWARE.
> > > > + */
> > > > +
> > > > +#include <sys/poll.h>
> > > > +
> > > > +#include "igt.h"
> > > > +#include "igt_msm.h"
> > > > +
> > > > +static struct msm_device *dev;
> > > > +static struct msm_bo *scratch_bo;
> > > > +static uint32_t *scratch;
> > > > +
> > > > +/*
> > > > + * Helpers for cmdstream packet building:
> > > > + */
> > > > +
> > > > +static void
> > > > +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref)
> > > > +{
> > > > +       msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4);
> > > > +       msm_cmd_emit(cmd, 0);                              /* RESERVED */
> > > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* POLL_ADDR_LO/HI */
> > > > +       msm_cmd_emit(cmd, ref);                            /* REF */
> > > > +}
> > > > +
> > > > +static void
> > > > +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val)
> > > > +{
> > > > +       msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > > +       msm_cmd_bo  (cmd, scratch_bo, offset_dwords * 4);  /* ADDR_LO/HI */
> > > > +       msm_cmd_emit(cmd, val);                            /* VAL */
> > > > +}
> > > > +
> > > > +/*
> > > > + * Helper to wait on a fence-fd:
> > > > + */
> > > > +static void
> > > > +wait_and_close(int fence_fd)
> > > > +{
> > > > +       poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1);
> > > > +       close(fence_fd);
> > > > +}
> > > > +
> > > > +/*
> > > > + * Helper for hang tests.  Emits multiple submits, with one in the middle
> > > > + * that triggers a fault, and confirms that the submits before and after
> > > > + * the faulting one execute properly, ie. that the driver properly manages
> > > > + * to recover and re-queue the submits after the faulting submit;
> > > > + */
> > > > +static void
> > > > +do_hang_test(struct msm_pipe *pipe)
> > > > +{
> > > > +       struct msm_cmd *cmds[16];
> > > > +       int fence_fds[ARRAY_SIZE(cmds)];
> > > > +
> > > > +       memset(scratch, 0, 0x1000);
> > > > +
> > > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > > +               struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > > +
> > > > +               cmds[i] = cmd;
> > > > +
> > > > +               /*
> > > > +                * Emit a packet to wait for scratch[0] to be >= 1
> > > > +                *
> > > > +                * This lets us force the GPU to wait until all the cmdstream is
> > > > +                * queued up.
> > > > +                */
> > > > +               wait_mem_gte(cmd, 0, 1);
> > > > +
> > > > +               if (i == 10) {
> > > > +                       msm_cmd_emit(cmd, 0xdeaddead);
> > > > +               }
> > > > +
> > > > +               /* Emit a packet to write scratch[1+i] = 2+i: */
> > > > +               mem_write(cmd, 1+i, 2+i);
> > > > +       }
> > > > +
> > > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > > +               fence_fds[i] = igt_msm_cmd_submit(cmds[i]);
> > > > +       }
> > > > +
> > > > +       usleep(10000);
> > > > +
> > > > +       /* Let the WAIT_MEM_GTE complete: */
> > > > +       scratch[0] = 1;
> > > > +
> > > > +       for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) {
> > > > +               wait_and_close(fence_fds[i]);
> > > > +               igt_msm_cmd_free(cmds[i]);
> > > > +               if (i == 10)
> > > > +                       continue;
> > > > +               igt_assert_eq(scratch[1+i], 2+i);
> > > > +       }
> > > > +}
> > > > +
> > > > +/*
> > > > + * Tests for drm/msm hangcheck, recovery, and fault handling
> > > > + */
> > > > +
> > > > +igt_main
> > > > +{
> > > > +       static struct msm_pipe *pipe = NULL;
> > > > +
> > > > +       igt_fixture {
> > > > +               dev = igt_msm_dev_open();
> > > > +               pipe = igt_msm_pipe_open(dev, 0);
> > > > +               scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC);
> > > > +               scratch = igt_msm_bo_map(scratch_bo);
> > > > +       }
> > > > +
> > > > +       igt_describe("Test sw hangcheck handling");
> > > > +       igt_subtest("hangcheck") {
> > > > +               igt_require(dev->gen >= 6);
> > > > +
> > > > +               /* Disable hw hang detection to force fallback to sw hangcheck: */
> > > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "Y");
> > >
> > > note that this depends on [1].. not sure if there is any constraint
> > > about landing igt tests before some debugfs they depend on lands
> > > upstream on the kernel side?
> > >
> > > [1] https://patchwork.freedesktop.org/patch/462625/?series=96725&rev=1
> >
> > The usual ordering dependency of kernel vs userspace, where both sides
> > are reviewed and ready to go before anything lands. But then the
> > actual merging with IGT is not so strict, IGT can go in first as long
> > as there's a consensus that the required kernel changes are going in
> > in finite time.
> >
> > That said, IGT is supposed to do the right thing for kernels some time
> > back, especially LTS kernels, so this test needs to properly handle
> > the debugfs file missing regardless of merging order.
> >
> > Some kind of igt_require check for the debugfs file takes care of
> > that.
> >
> 
> Hmm, unless I'm overlooking something, I guess we need a helper to
> check for the existence of a debugfs file?

Yeah =(

Unless the file supports reading.


-- 
Petri Latvala


> 
> BR,
> -R
> 
> >
> > --
> > Petri Latvala
> >
> >
> >
> >
> > >
> > > BR,
> > > -R
> > >
> > > > +
> > > > +               do_hang_test(pipe);
> > > > +
> > > > +               igt_debugfs_write(dev->fd, "disable_err_irq", "N");
> > > > +       }
> > > > +
> > > > +       igt_describe("Test hw fault handling");
> > > > +       igt_subtest("gpu-fault") {
> > > > +               igt_require(dev->gen >= 6);
> > > > +
> > > > +               do_hang_test(pipe);
> > > > +       }
> > > > +
> > > > +       igt_describe("Test iova fault handling");
> > > > +       igt_subtest("iova-fault") {
> > > > +               struct msm_cmd *cmd;
> > > > +
> > > > +               igt_require(dev->gen >= 6);
> > > > +
> > > > +               cmd = igt_msm_cmd_new(pipe, 0x1000);
> > > > +
> > > > +               msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3);
> > > > +               msm_cmd_emit(cmd, 0xdeaddead);           /* ADDR_LO */
> > > > +               msm_cmd_emit(cmd, 0x1);                  /* ADDR_HI */
> > > > +               msm_cmd_emit(cmd, 0x123);                /* VAL */
> > > > +
> > > > +               wait_and_close(igt_msm_cmd_submit(cmd));
> > > > +       }
> > > > +
> > > > +       igt_fixture {
> > > > +               igt_msm_bo_free(scratch_bo);
> > > > +               igt_msm_pipe_close(pipe);
> > > > +               igt_msm_dev_close(dev);
> > > > +       }
> > > > +}
> > > > --
> > > > 2.31.1
> > > >

[igt-dev] ✓ Fi.CI.BAT: success for msm: Add tests for gpu fault handling (rev2)

[Patchwork]

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== Series Details ==

Series: msm: Add tests for gpu fault handling (rev2)
URL   : https://patchwork.freedesktop.org/series/96721/
State : success

== Summary ==

CI Bug Log - changes from IGT_6277 -> IGTPW_6390
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/index.html

Participating hosts (34 -> 35)
------------------------------

  Additional (2): fi-kbl-soraka fi-icl-u2 
  Missing    (1): fi-bsw-cyan 

Known issues
------------

  Here are the changes found in IGTPW_6390 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][3] ([fdo#109271]) +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-soraka:      NOTRUN -> [INCOMPLETE][4] ([i915#4221])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-u2:          NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][6] -> [INCOMPLETE][7] ([i915#3921])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-u2:          NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][12] ([i915#3301])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-tgl-1115g4:      [FAIL][13] ([i915#1888]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [SKIP][15] ([fdo#109271]) -> [FAIL][16] ([i915#579])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4221]: https://gitlab.freedesktop.org/drm/intel/issues/4221
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6277 -> IGTPW_6390

  CI-20190529: 20190529
  CI_DRM_10863: de2d87964c398bd4de93d264192e7f69928cf9c8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6390: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/index.html
  IGT_6277: 7201d343fced07a1951feea119480d55bce787e4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@msm_recovery@gpu-fault
+igt@msm_recovery@hangcheck
+igt@msm_recovery@iova-fault

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/index.html

[-- Attachment #2: Type: text/html, Size: 6688 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for msm: Add tests for gpu fault handling (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30262 bytes --]

== Series Details ==

Series: msm: Add tests for gpu fault handling (rev2)
URL   : https://patchwork.freedesktop.org/series/96721/
State : success

== Summary ==

CI Bug Log - changes from IGT_6277_full -> IGTPW_6390_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/index.html

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in IGTPW_6390_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vecs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_ctx_persistence@engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-snb7/igt@gem_ctx_persistence@engines-mixed.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][4] -> [FAIL][5] ([i915#2846])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-glk9/igt@gem_exec_fair@basic-deadline.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk8/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@gem_exec_fair@basic-none-vip@rcs0.html
    - shard-glk:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk1/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          NOTRUN -> [FAIL][11] ([i915#2842]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-tglb2/igt@gem_exec_fair@basic-pace@bcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb7/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][16] -> [SKIP][17] ([fdo#109271]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][18] -> [FAIL][19] ([i915#2849])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@secure-non-master:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([fdo#112283])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@gem_exec_params@secure-non-master.html
    - shard-iclb:         NOTRUN -> [SKIP][21] ([fdo#112283])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb6/igt@gem_exec_params@secure-non-master.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-snb:          [PASS][22] -> [SKIP][23] ([fdo#109271])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-snb2/igt@gem_exec_suspend@basic-s3.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-snb5/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][24] -> [SKIP][25] ([i915#2190])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-tglb3/igt@gem_huc_copy@huc-copy.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@gem_huc_copy@huc-copy.html
    - shard-kbl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2190])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-iclb:         NOTRUN -> [SKIP][27] ([i915#4270])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb5/igt@gem_pxp@reject-modify-context-protection-off-1.html
    - shard-tglb:         NOTRUN -> [SKIP][28] ([i915#4270])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb1/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_render_copy@yf-tiled-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][29] ([i915#768])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb7/igt@gem_render_copy@yf-tiled-to-vebox-y-tiled.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([fdo#110542])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@gem_userptr_blits@coherency-sync.html
    - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109290])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb6/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([i915#3297]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb7/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][33] ([i915#3318])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl8/igt@gem_userptr_blits@vma-merge.html

  * igt@gen7_exec_parse@cmd-crossing-page:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#109289]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@gen7_exec_parse@cmd-crossing-page.html
    - shard-iclb:         NOTRUN -> [SKIP][35] ([fdo#109289])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb6/igt@gen7_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#2856]) +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][37] ([i915#2856])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb8/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-kbl:          NOTRUN -> [FAIL][38] ([i915#454])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl3/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-apl:          [PASS][39] -> [SKIP][40] ([fdo#109271])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-apl7/igt@i915_pm_dc@dc9-dpms.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl4/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - shard-glk:          NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#1937])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([fdo#109506] / [i915#2411])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-tglb:         NOTRUN -> [SKIP][43] ([fdo#109303])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@i915_query@query-topology-known-pci-ids.html

  * igt@i915_selftest@live@gt_lrc:
    - shard-tglb:         NOTRUN -> [DMESG-FAIL][44] ([i915#2373])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb3/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@gt_pm:
    - shard-tglb:         NOTRUN -> [DMESG-FAIL][45] ([i915#1759])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb3/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          NOTRUN -> [INCOMPLETE][46] ([i915#3921])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-snb2/igt@i915_selftest@live@hangcheck.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([i915#404])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([fdo#111614]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb2/igt@kms_big_fb@linear-8bpp-rotate-90.html
    - shard-iclb:         NOTRUN -> [SKIP][49] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb4/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3777]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][51] ([fdo#109271]) +100 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#110723])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([fdo#111615]) +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#3886]) +2 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
    - shard-tglb:         NOTRUN -> [SKIP][55] ([i915#3689] / [i915#3886])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#3886]) +4 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109278] / [i915#3886]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#3886]) +3 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([i915#3689]) +11 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-apl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl2/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@dp-edid-read:
    - shard-snb:          NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-snb6/igt@kms_chamelium@dp-edid-read.html
    - shard-iclb:         NOTRUN -> [SKIP][62] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb4/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_chamelium@vga-edid-read:
    - shard-glk:          NOTRUN -> [SKIP][63] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk2/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_color@pipe-d-ctm-blue-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][64] ([fdo#109278] / [i915#1149])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb5/igt@kms_color@pipe-d-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-75:
    - shard-kbl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [fdo#111827]) +26 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl6/igt@kms_color_chamelium@pipe-a-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([fdo#109284] / [fdo#111827]) +9 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb2/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html

  * igt@kms_content_protection@atomic:
    - shard-kbl:          NOTRUN -> [TIMEOUT][67] ([i915#1319]) +2 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl2/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@content_type_change:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#111828])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@kms_content_protection@content_type_change.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][69] ([i915#1319]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl2/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([i915#3319]) +4 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
    - shard-tglb:         NOTRUN -> [SKIP][71] ([i915#3359]) +3 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][72] ([fdo#109278]) +12 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb4/igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][73] ([fdo#109279] / [i915#3359])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][74] ([fdo#109274] / [fdo#109278])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb4/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-tglb:         NOTRUN -> [SKIP][75] ([i915#4103])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][76] ([i915#180] / [i915#636])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
    - shard-glk:          [PASS][77] -> [FAIL][78] ([i915#79])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend@a-edp1:
    - shard-tglb:         [PASS][79] -> [INCOMPLETE][80] ([i915#2411] / [i915#456])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-tglb2/igt@kms_flip@flip-vs-suspend@a-edp1.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-tglb:         NOTRUN -> [SKIP][81] ([i915#2587])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-kbl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2672])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([fdo#109280]) +6 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][84] ([fdo#109271]) +282 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][85] ([i915#180])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-glk:          NOTRUN -> [SKIP][86] ([fdo#109271]) +78 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-snb:          NOTRUN -> [SKIP][87] ([fdo#109271]) +65 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-snb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-tglb:         NOTRUN -> [SKIP][88] ([fdo#111825]) +27 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglb:         NOTRUN -> [SKIP][89] ([i915#1839])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-tglb:         [PASS][90] -> [INCOMPLETE][91] ([i915#456])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          NOTRUN -> [FAIL][92] ([fdo#108145] / [i915#265])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][93] ([i915#265])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-glk:          NOTRUN -> [FAIL][94] ([fdo#108145] / [i915#265])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
    - shard-kbl:          NOTRUN -> [FAIL][95] ([fdo#108145] / [i915#265]) +2 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([fdo#112054])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb3/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-iclb:         NOTRUN -> [SKIP][97] ([fdo#109274]) +4 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb2/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-kbl:          NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2733])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
    - shard-glk:          NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2733])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#658]) +4 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
    - shard-tglb:         NOTRUN -> [SKIP][101] ([i915#2920]) +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-iclb:         NOTRUN -> [SKIP][102] ([i915#658])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
    - shard-glk:          NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#658]) +2 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
    - shard-apl:          NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#658])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-tglb:         NOTRUN -> [SKIP][105] ([i915#1911])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb3/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         NOTRUN -> [SKIP][106] ([fdo#109441])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
    - shard-tglb:         NOTRUN -> [FAIL][107] ([i915#132] / [i915#3467]) +1 similar issue
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb7/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [PASS][108] -> [SKIP][109] ([fdo#109441]) +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb7/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][110] ([IGT#2])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl8/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-kbl:          NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#533]) +3 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl6/igt@kms_vblank@pipe-d-wait-idle.html
    - shard-apl:          NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#533]) +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-apl1/igt@kms_vblank@pipe-d-wait-idle.html
    - shard-glk:          NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#533])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk1/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-check-output:
    - shard-kbl:          NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#2437])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl3/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-tglb:         NOTRUN -> [SKIP][115] ([i915#2437])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@kms_writeback@writeback-fb-id.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][116] -> [FAIL][117] ([i915#1542])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-glk2/igt@perf@polling-parameterized.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk4/igt@perf@polling-parameterized.html

  * igt@prime_nv_api@i915_nv_import_twice:
    - shard-iclb:         NOTRUN -> [SKIP][118] ([fdo#109291]) +2 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb4/igt@prime_nv_api@i915_nv_import_twice.html

  * igt@prime_nv_pcopy@test3_1:
    - shard-tglb:         NOTRUN -> [SKIP][119] ([fdo#109291]) +3 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@prime_nv_pcopy@test3_1.html

  * igt@sysfs_clients@busy:
    - shard-tglb:         NOTRUN -> [SKIP][120] ([i915#2994]) +3 similar issues
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@sysfs_clients@busy.html

  * igt@sysfs_clients@fair-3:
    - shard-kbl:          NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#2994]) +4 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-kbl4/igt@sysfs_clients@fair-3.html
    - shard-glk:          NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2994]) +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk3/igt@sysfs_clients@fair-3.html

  * igt@sysfs_clients@fair-7:
    - shard-iclb:         NOTRUN -> [SKIP][123] ([i915#2994])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb4/igt@sysfs_clients@fair-7.html

  * igt@sysfs_heartbeat_interval@precise@vecs0:
    - shard-iclb:         [PASS][124] -> [FAIL][125] ([i915#1755])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-iclb7/igt@sysfs_heartbeat_interval@precise@vecs0.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb6/igt@sysfs_heartbeat_interval@precise@vecs0.html
    - shard-tglb:         [PASS][126] -> [FAIL][127] ([i915#1755])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-tglb7/igt@sysfs_heartbeat_interval@precise@vecs0.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb8/igt@sysfs_heartbeat_interval@precise@vecs0.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][128] ([i915#658]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-iclb8/igt@feature_discovery@psr2.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-tglb:         [INCOMPLETE][130] ([i915#456]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-tglb6/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [FAIL][132] ([i915#2842]) -> [PASS][133] +4 similar issues
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-iclb:         [FAIL][134] ([i915#2842]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6277/shard-iclb3/igt@gem_exec_fair@basic-pace@vecs0.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/shard-iclb6/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_mmap@basic:
    - shard-glk:          [DMESG-WARN][136] ([i915#118]) -> [PASS][137] +4 similar issues
   [136]: https://intel-gfx-ci.01.org/tree/drm-

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6390/index.html

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