* [PATCH v2 0/4] Add OPP table for RZ/G2L SoC
@ 2021-11-12 8:09 Biju Das
2021-11-12 8:10 ` [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro Biju Das
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Biju Das @ 2021-11-12 8:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
This patch series aims to add OPP table for RZ/G2L SoC.
Supported frequencies are 1.2GHz, 600MHz, 300MHz and 150MHz.
V1->v2:
* Fixed typo cluster1_opp->cluster0_opp
Biju Das (4):
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
arm64: dts: renesas: r9a07g044: Sort psci node
arm64: dts: renesas: r9a07g044: Add OPP table
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 36 ++++++++++++++++++++--
drivers/clk/renesas/r9a07g044-cpg.c | 11 ++++++-
drivers/clk/renesas/rzg2l-cpg.h | 2 ++
3 files changed, 45 insertions(+), 4 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
2021-11-12 8:09 [PATCH v2 0/4] Add OPP table for RZ/G2L SoC Biju Das
@ 2021-11-12 8:10 ` Biju Das
2021-11-18 10:30 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 2/4] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV Biju Das
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Biju Das @ 2021-11-12 8:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU
frequency. Define CPG_PL1_DDIV, so that we can register it as a
clock divider in later patch.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* No change
---
drivers/clk/renesas/rzg2l-cpg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 484c7cee2629..fce4a8f35410 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -9,6 +9,7 @@
#ifndef __RENESAS_RZG2L_CPG_H__
#define __RENESAS_RZG2L_CPG_H__
+#define CPG_PL1_DDIV (0x200)
#define CPG_PL2_DDIV (0x204)
#define CPG_PL3A_DDIV (0x208)
#define CPG_PL2SDHI_DSEL (0x218)
@@ -29,6 +30,7 @@
#define DDIV_PACK(offset, bitpos, size) \
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
+#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)
#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/4] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
2021-11-12 8:09 [PATCH v2 0/4] Add OPP table for RZ/G2L SoC Biju Das
2021-11-12 8:10 ` [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro Biju Das
@ 2021-11-12 8:10 ` Biju Das
2021-11-18 10:31 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 3/4] arm64: dts: renesas: r9a07g044: Sort psci node Biju Das
2021-11-12 8:10 ` [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table Biju Das
3 siblings, 1 reply; 10+ messages in thread
From: Biju Das @ 2021-11-12 8:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual
Rev.1.00.
This patch adds clock divider table "dtable_1_8" and switches to
DEF_DIV for "I" clock.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V1->V2:
* No change
---
drivers/clk/renesas/r9a07g044-cpg.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 91643b4e1c9c..4893815cddd8 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -56,6 +56,14 @@ enum clk_ids {
};
/* Divider tables */
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
static const struct clk_div_table dtable_1_32[] = {
{0, 1},
{1, 2},
@@ -110,7 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
/* Core output clk */
- DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
+ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
+ CLK_DIVIDER_HIWORD_MASK),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/4] arm64: dts: renesas: r9a07g044: Sort psci node
2021-11-12 8:09 [PATCH v2 0/4] Add OPP table for RZ/G2L SoC Biju Das
2021-11-12 8:10 ` [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro Biju Das
2021-11-12 8:10 ` [PATCH v2 2/4] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV Biju Das
@ 2021-11-12 8:10 ` Biju Das
2021-11-24 14:14 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table Biju Das
3 siblings, 1 reply; 10+ messages in thread
From: Biju Das @ 2021-11-12 8:10 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Sort psci node alphabetically.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* No change
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 485ef5f0fea1..43a5d359519a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -42,11 +42,6 @@
clock-frequency = <0>;
};
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -85,6 +80,11 @@
};
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table
2021-11-12 8:09 [PATCH v2 0/4] Add OPP table for RZ/G2L SoC Biju Das
` (2 preceding siblings ...)
2021-11-12 8:10 ` [PATCH v2 3/4] arm64: dts: renesas: r9a07g044: Sort psci node Biju Das
@ 2021-11-12 8:10 ` Biju Das
2021-11-24 15:02 ` Geert Uytterhoeven
3 siblings, 1 reply; 10+ messages in thread
From: Biju Das @ 2021-11-12 8:10 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add OPP table for RZ/G2L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V1->v2:
* Fixed typo cluster1_opp->cluster0_opp
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 43a5d359519a..ccb788de6654 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -42,6 +42,32 @@
clock-frequency = <0>;
};
+ cluster0_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -63,6 +89,8 @@
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
@@ -71,6 +99,8 @@
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
2021-11-12 8:10 ` [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro Biju Das
@ 2021-11-18 10:30 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2021-11-18 10:30 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Linux-Renesas, linux-clk, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU
> frequency. Define CPG_PL1_DDIV, so that we can register it as a
> clock divider in later patch.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/4] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
2021-11-12 8:10 ` [PATCH v2 2/4] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV Biju Das
@ 2021-11-18 10:31 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2021-11-18 10:31 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual
> Rev.1.00.
>
> This patch adds clock divider table "dtable_1_8" and switches to
> DEF_DIV for "I" clock.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: renesas: r9a07g044: Sort psci node
2021-11-12 8:10 ` [PATCH v2 3/4] arm64: dts: renesas: r9a07g044: Sort psci node Biju Das
@ 2021-11-24 14:14 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2021-11-24 14:14 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Geert Uytterhoeven, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Sort psci node alphabetically.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table
2021-11-12 8:10 ` [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table Biju Das
@ 2021-11-24 15:02 ` Geert Uytterhoeven
2021-11-24 15:08 ` Biju Das
0 siblings, 1 reply; 10+ messages in thread
From: Geert Uytterhoeven @ 2021-11-24 15:02 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add OPP table for RZ/G2L SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> V1->v2:
> * Fixed typo cluster1_opp->cluster0_opp
Thanks for the update!
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -42,6 +42,32 @@
> clock-frequency = <0>;
> };
>
> + cluster0_opp: opp_table {
"make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/opp/opp-v2.yaml"
doesn't like the node name.
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table
2021-11-24 15:02 ` Geert Uytterhoeven
@ 2021-11-24 15:08 ` Biju Das
0 siblings, 0 replies; 10+ messages in thread
From: Biju Das @ 2021-11-24 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table
>
> Hi Biju,
>
> On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add OPP table for RZ/G2L SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > V1->v2:
> > * Fixed typo cluster1_opp->cluster0_opp
>
> Thanks for the update!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -42,6 +42,32 @@
> > clock-frequency = <0>;
> > };
> >
> > + cluster0_opp: opp_table {
>
> "make dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/opp/opp-v2.yaml"
> doesn't like the node name.
OK, Will check and send the fix as v3 for this patch.
Regards,
Biju
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-11-24 15:08 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-12 8:09 [PATCH v2 0/4] Add OPP table for RZ/G2L SoC Biju Das
2021-11-12 8:10 ` [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro Biju Das
2021-11-18 10:30 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 2/4] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV Biju Das
2021-11-18 10:31 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 3/4] arm64: dts: renesas: r9a07g044: Sort psci node Biju Das
2021-11-24 14:14 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table Biju Das
2021-11-24 15:02 ` Geert Uytterhoeven
2021-11-24 15:08 ` Biju Das
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