* [PULL 0/2] riscv-to-apply queue
@ 2021-11-17 9:20 Alistair Francis
2021-11-17 9:20 ` [PULL 1/2] target/riscv: machine: Sort the .subsections Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Alistair Francis @ 2021-11-17 9:20 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
The following changes since commit 8d5fcb1990bc64b62c0bc12121fe510940be5664:
Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2021-11-17 07:41:08 +0100)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211117-1
for you to fetch changes up to c94c239496256f1f1cb589825d052c2f3e26ebf6:
meson.build: Merge riscv32 and riscv64 cpu family (2021-11-17 19:18:22 +1000)
----------------------------------------------------------------
Sixth RISC-V PR for QEMU 6.2
- Fix build for riscv hosts
- Soft code alphabetically
----------------------------------------------------------------
Bin Meng (1):
target/riscv: machine: Sort the .subsections
Richard Henderson (1):
meson.build: Merge riscv32 and riscv64 cpu family
meson.build | 6 ++++
target/riscv/machine.c | 92 +++++++++++++++++++++++++-------------------------
2 files changed, 52 insertions(+), 46 deletions(-)
^ permalink raw reply [flat|nested] 4+ messages in thread* [PULL 1/2] target/riscv: machine: Sort the .subsections 2021-11-17 9:20 [PULL 0/2] riscv-to-apply queue Alistair Francis @ 2021-11-17 9:20 ` Alistair Francis 2021-11-17 9:20 ` [PULL 2/2] meson.build: Merge riscv32 and riscv64 cpu family Alistair Francis 2021-11-17 11:34 ` [PULL 0/2] riscv-to-apply queue Richard Henderson 2 siblings, 0 replies; 4+ messages in thread From: Alistair Francis @ 2021-11-17 9:20 UTC (permalink / raw) To: qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis From: Bin Meng <bin.meng@windriver.com> Move the codes around so that the order of .subsections matches the one they are referenced in vmstate_riscv_cpu. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211030030606.32297-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/machine.c | 92 +++++++++++++++++++++--------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 7b4c739564..ad8248ebfd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -76,20 +76,50 @@ static bool hyper_needed(void *opaque) return riscv_has_ext(env, RVH); } -static bool vector_needed(void *opaque) -{ - RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; +static const VMStateDescription vmstate_hyper = { + .name = "cpu/hyper", + .version_id = 1, + .minimum_version_id = 1, + .needed = hyper_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.hstatus, RISCVCPU), + VMSTATE_UINTTL(env.hedeleg, RISCVCPU), + VMSTATE_UINTTL(env.hideleg, RISCVCPU), + VMSTATE_UINTTL(env.hcounteren, RISCVCPU), + VMSTATE_UINTTL(env.htval, RISCVCPU), + VMSTATE_UINTTL(env.htinst, RISCVCPU), + VMSTATE_UINTTL(env.hgatp, RISCVCPU), + VMSTATE_UINT64(env.htimedelta, RISCVCPU), - return riscv_has_ext(env, RVV); -} + VMSTATE_UINT64(env.vsstatus, RISCVCPU), + VMSTATE_UINTTL(env.vstvec, RISCVCPU), + VMSTATE_UINTTL(env.vsscratch, RISCVCPU), + VMSTATE_UINTTL(env.vsepc, RISCVCPU), + VMSTATE_UINTTL(env.vscause, RISCVCPU), + VMSTATE_UINTTL(env.vstval, RISCVCPU), + VMSTATE_UINTTL(env.vsatp, RISCVCPU), -static bool pointermasking_needed(void *opaque) + VMSTATE_UINTTL(env.mtval2, RISCVCPU), + VMSTATE_UINTTL(env.mtinst, RISCVCPU), + + VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), + VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), + VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), + VMSTATE_UINTTL(env.scause_hs, RISCVCPU), + VMSTATE_UINTTL(env.stval_hs, RISCVCPU), + VMSTATE_UINTTL(env.satp_hs, RISCVCPU), + VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + +static bool vector_needed(void *opaque) { RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; - return riscv_has_ext(env, RVJ); + return riscv_has_ext(env, RVV); } static const VMStateDescription vmstate_vector = { @@ -108,6 +138,14 @@ static const VMStateDescription vmstate_vector = { } }; +static bool pointermasking_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_has_ext(env, RVJ); +} + static const VMStateDescription vmstate_pointermasking = { .name = "cpu/pointer_masking", .version_id = 1, @@ -126,44 +164,6 @@ static const VMStateDescription vmstate_pointermasking = { } }; -static const VMStateDescription vmstate_hyper = { - .name = "cpu/hyper", - .version_id = 1, - .minimum_version_id = 1, - .needed = hyper_needed, - .fields = (VMStateField[]) { - VMSTATE_UINTTL(env.hstatus, RISCVCPU), - VMSTATE_UINTTL(env.hedeleg, RISCVCPU), - VMSTATE_UINTTL(env.hideleg, RISCVCPU), - VMSTATE_UINTTL(env.hcounteren, RISCVCPU), - VMSTATE_UINTTL(env.htval, RISCVCPU), - VMSTATE_UINTTL(env.htinst, RISCVCPU), - VMSTATE_UINTTL(env.hgatp, RISCVCPU), - VMSTATE_UINT64(env.htimedelta, RISCVCPU), - - VMSTATE_UINT64(env.vsstatus, RISCVCPU), - VMSTATE_UINTTL(env.vstvec, RISCVCPU), - VMSTATE_UINTTL(env.vsscratch, RISCVCPU), - VMSTATE_UINTTL(env.vsepc, RISCVCPU), - VMSTATE_UINTTL(env.vscause, RISCVCPU), - VMSTATE_UINTTL(env.vstval, RISCVCPU), - VMSTATE_UINTTL(env.vsatp, RISCVCPU), - - VMSTATE_UINTTL(env.mtval2, RISCVCPU), - VMSTATE_UINTTL(env.mtinst, RISCVCPU), - - VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), - VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), - VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), - VMSTATE_UINTTL(env.scause_hs, RISCVCPU), - VMSTATE_UINTTL(env.stval_hs, RISCVCPU), - VMSTATE_UINTTL(env.satp_hs, RISCVCPU), - VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), - - VMSTATE_END_OF_LIST() - } -}; - const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, -- 2.31.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PULL 2/2] meson.build: Merge riscv32 and riscv64 cpu family 2021-11-17 9:20 [PULL 0/2] riscv-to-apply queue Alistair Francis 2021-11-17 9:20 ` [PULL 1/2] target/riscv: machine: Sort the .subsections Alistair Francis @ 2021-11-17 9:20 ` Alistair Francis 2021-11-17 11:34 ` [PULL 0/2] riscv-to-apply queue Richard Henderson 2 siblings, 0 replies; 4+ messages in thread From: Alistair Francis @ 2021-11-17 9:20 UTC (permalink / raw) To: qemu-devel Cc: alistair23, Richard Henderson, Philippe Mathieu-Daudé, Alistair Francis From: Richard Henderson <richard.henderson@linaro.org> In ba0e73336200, we merged riscv32 and riscv64 in configure. However, meson does not treat them the same. We need to merge them here as well. Fixes: ba0e73336200 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211116095042.335224-1-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- meson.build | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meson.build b/meson.build index 36540e0794..e2d38a43e6 100644 --- a/meson.build +++ b/meson.build @@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() + +# Unify riscv* to a single family. +if cpu in ['riscv32', 'riscv64'] + cpu = 'riscv' +endif + targetos = host_machine.system() if cpu in ['x86', 'x86_64'] -- 2.31.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PULL 0/2] riscv-to-apply queue 2021-11-17 9:20 [PULL 0/2] riscv-to-apply queue Alistair Francis 2021-11-17 9:20 ` [PULL 1/2] target/riscv: machine: Sort the .subsections Alistair Francis 2021-11-17 9:20 ` [PULL 2/2] meson.build: Merge riscv32 and riscv64 cpu family Alistair Francis @ 2021-11-17 11:34 ` Richard Henderson 2 siblings, 0 replies; 4+ messages in thread From: Richard Henderson @ 2021-11-17 11:34 UTC (permalink / raw) To: Alistair Francis, qemu-devel; +Cc: alistair23, Alistair Francis On 11/17/21 10:20 AM, Alistair Francis wrote: > From: Alistair Francis <alistair.francis@wdc.com> > > The following changes since commit 8d5fcb1990bc64b62c0bc12121fe510940be5664: > > Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2021-11-17 07:41:08 +0100) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211117-1 > > for you to fetch changes up to c94c239496256f1f1cb589825d052c2f3e26ebf6: > > meson.build: Merge riscv32 and riscv64 cpu family (2021-11-17 19:18:22 +1000) > > ---------------------------------------------------------------- > Sixth RISC-V PR for QEMU 6.2 > > - Fix build for riscv hosts > - Soft code alphabetically > > ---------------------------------------------------------------- > Bin Meng (1): > target/riscv: machine: Sort the .subsections > > Richard Henderson (1): > meson.build: Merge riscv32 and riscv64 cpu family > > meson.build | 6 ++++ > target/riscv/machine.c | 92 +++++++++++++++++++++++++------------------------- > 2 files changed, 52 insertions(+), 46 deletions(-) > Applied, thanks. r~ ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-11-17 11:36 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-11-17 9:20 [PULL 0/2] riscv-to-apply queue Alistair Francis 2021-11-17 9:20 ` [PULL 1/2] target/riscv: machine: Sort the .subsections Alistair Francis 2021-11-17 9:20 ` [PULL 2/2] meson.build: Merge riscv32 and riscv64 cpu family Alistair Francis 2021-11-17 11:34 ` [PULL 0/2] riscv-to-apply queue Richard Henderson
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