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From: Sean Anderson <sean.anderson@seco.com>
To: u-boot@lists.denx.de, Peng Fan <peng.fan@nxp.com>,
	Jaehoon Chung <jh80.chung@samsung.com>
Cc: Haibo Chen <haibo.chen@nxp.com>,
	Fabio Estevam <festevam@gmail.com>, Yangbo Lu <yangbo.lu@nxp.com>,
	Michael Walle <michael@walle.cc>,
	Sean Anderson <sean.anderson@seco.com>
Subject: [PATCH v3 03/12] mmc: fsl_esdhc_imx: fix voltage validation
Date: Tue, 23 Nov 2021 15:03:38 -0500	[thread overview]
Message-ID: <20211123200347.3772343-4-sean.anderson@seco.com> (raw)
In-Reply-To: <20211123200347.3772343-1-sean.anderson@seco.com>

[ fsl_esdhc commit 5b05fc0310cd933acf76ee661577c6b07a95e684 ]

Voltage validation should be done by CMD8. Current comparison between
mmc_cfg voltages and host voltage capabilities is meaningless.
So drop current comparison and let voltage validation is through CMD8.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---

(no changes since v1)

 drivers/mmc/fsl_esdhc_imx.c | 35 +++++++++++++----------------------
 include/fsl_esdhc_imx.h     | 12 ++++++------
 2 files changed, 19 insertions(+), 28 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 121f9182f6..f4ccb19d9f 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1167,7 +1167,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 {
 	struct mmc_config *cfg;
 	struct fsl_esdhc *regs;
-	u32 caps, voltage_caps;
+	u32 caps;
 	int ret;
 
 	if (!priv)
@@ -1206,9 +1206,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 	memset(cfg, '\0', sizeof(*cfg));
 #endif
 
-	voltage_caps = 0;
 	caps = esdhc_read32(&regs->hostcapblt);
-
 #ifdef CONFIG_MCF5441x
 	/*
 	 * MCF5441x RM declares in more points that sdhc clock speed must
@@ -1219,31 +1217,24 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
-	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
-			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
+	caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
 #endif
 
-	if (caps & ESDHC_HOSTCAPBLT_VS18)
-		voltage_caps |= MMC_VDD_165_195;
-	if (caps & ESDHC_HOSTCAPBLT_VS30)
-		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
-	if (caps & ESDHC_HOSTCAPBLT_VS33)
-		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
+#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+	caps |= HOSTCAPBLT_VS33;
+#endif
+
+	if (caps & HOSTCAPBLT_VS18)
+		cfg->voltages |= MMC_VDD_165_195;
+	if (caps & HOSTCAPBLT_VS30)
+		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+	if (caps & HOSTCAPBLT_VS33)
+		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 
 	cfg->name = "FSL_SDHC";
 #if !CONFIG_IS_ENABLED(DM_MMC)
 	cfg->ops = &esdhc_ops;
 #endif
-#ifdef CONFIG_SYS_SD_VOLTAGE
-	cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
-#else
-	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-#endif
-	if ((cfg->voltages & voltage_caps) == 0) {
-		printf("voltage not supported by controller\n");
-		return -1;
-	}
-
 	if (priv->bus_width == 8)
 		cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 	else if (priv->bus_width == 4)
@@ -1261,7 +1252,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 			cfg->host_caps &= ~MMC_MODE_4BIT;
 	}
 
-	if (caps & ESDHC_HOSTCAPBLT_HSS)
+	if (caps & HOSTCAPBLT_HSS)
 		cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 12e9163382..4ae932858e 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -164,12 +164,12 @@
 #define BLKATTR_SIZE(x)	(x & 0x1fff)
 #define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
 
-#define ESDHC_HOSTCAPBLT_VS18	0x04000000
-#define ESDHC_HOSTCAPBLT_VS30	0x02000000
-#define ESDHC_HOSTCAPBLT_VS33	0x01000000
-#define ESDHC_HOSTCAPBLT_SRS	0x00800000
-#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
-#define ESDHC_HOSTCAPBLT_HSS	0x00200000
+#define HOSTCAPBLT_VS18	0x04000000
+#define HOSTCAPBLT_VS30	0x02000000
+#define HOSTCAPBLT_VS33	0x01000000
+#define HOSTCAPBLT_SRS	0x00800000
+#define HOSTCAPBLT_DMAS	0x00400000
+#define HOSTCAPBLT_HSS	0x00200000
 
 #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
 
-- 
2.25.1


  parent reply	other threads:[~2021-11-23 20:04 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20211123200412epcas1p32bd625558b9aa40fa49cd0b23039e59a@epcas1p3.samsung.com>
2021-11-23 20:03 ` [PATCH v3 00/12] fsl_esdhc_imx: port several patches from fsl_esdhc Sean Anderson
2021-11-23 20:03   ` [PATCH v3 01/12] mmc: fsl_esdhc_imx: make BLK as hard requirement of DM_MMC Sean Anderson
2021-11-23 20:03   ` [PATCH v3 02/12] mmc: fsl_esdhc_imx: remove redundant DM_MMC checking Sean Anderson
2021-11-23 20:03   ` Sean Anderson [this message]
2021-11-23 20:03   ` [PATCH v3 04/12] mmc: fsl_esdhc_imx: clean up bus width configuration code Sean Anderson
2021-11-23 20:03   ` [PATCH v3 05/12] mmc: fsl_esdhc_imx: drop redundant code for non-removable feature Sean Anderson
2021-11-23 20:03   ` [PATCH v3 06/12] mmc: fsl_esdhc_imx: fix mmc->clock with actual clock Sean Anderson
2021-11-23 20:03   ` [PATCH v3 07/12] mmc: fsl_esdhc_imx: simplify 64bit check for SDMA transfers Sean Anderson
2021-11-23 20:03   ` [PATCH v3 08/12] mmc: fsl_esdhc_imx: use dma-mapping API Sean Anderson
2021-11-23 20:03   ` [PATCH v3 09/12] mmc: fsl_esdhc_imx: simplify esdhc_setup_data() Sean Anderson
2021-11-23 20:03   ` [PATCH v3 10/12] mmc: fsl_esdhc_imx: replace most #ifdefs by IS_ENABLED() Sean Anderson
2021-11-23 20:03   ` [PATCH v3 11/12] mmc: fsl_esdhc_imx: Replace more #ifdefs by if Sean Anderson
2021-11-23 20:03   ` [PATCH v3 12/12] mmc: fsl_esdhc_imx: set sysctl register for clock initialization Sean Anderson
2022-01-03 23:19   ` [PATCH v3 00/12] fsl_esdhc_imx: port several patches from fsl_esdhc Jaehoon Chung
2022-01-04 16:16   ` [RESEND PATCH v3 01/12] mmc: fsl_esdhc_imx: make BLK as hard requirement of DM_MMC Sean Anderson
2022-01-11  1:14     ` Jaehoon Chung
2022-01-11 16:15       ` Sean Anderson

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