From: Pratyush Yadav <p.yadav@ti.com> To: Nishanth Menon <nm@ti.com> Cc: Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>, Vignesh Raghavendra <vigneshr@ti.com>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-omap@vger.kernel.org>, Peng Fan <peng.fan@nxp.com> Subject: Re: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets Date: Fri, 3 Dec 2021 16:37:34 +0530 [thread overview] Message-ID: <20211203110734.23e2t356s45ux5mu@ti.com> (raw) In-Reply-To: <20211113043638.4358-1-nm@ti.com> On 12/11/21 10:36PM, Nishanth Menon wrote: > A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of ^^^ Same as previous patch, do you mean A72? J7200 does not have an A53 core and this cache node is for A72 cores anyway. With this fixed, Reviewed-by: Pratyush Yadav <p.yadav@ti.com> > 64 bytes and 16-way set-associative cache structure. > > 1MB of L2 / 64 (line length) = 16384 ways > 16384 ways / 16 = 1024 sets > > Fix the l2 cache-sets. > > [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system > [2] https://www.ti.com/lit/pdf/spruiu1 > > Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") > Reported-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Nishanth Menon <nm@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > index 958587d3a33d..64fef4e67d76 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > @@ -86,7 +86,7 @@ L2_0: l2-cache0 { > cache-level = <2>; > cache-size = <0x100000>; > cache-line-size = <64>; > - cache-sets = <2048>; > + cache-sets = <1024>; > next-level-cache = <&msmc_l3>; > }; > -- Regards, Pratyush Yadav Texas Instruments Inc.
WARNING: multiple messages have this Message-ID (diff)
From: Pratyush Yadav <p.yadav@ti.com> To: Nishanth Menon <nm@ti.com> Cc: Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>, Vignesh Raghavendra <vigneshr@ti.com>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-omap@vger.kernel.org>, Peng Fan <peng.fan@nxp.com> Subject: Re: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets Date: Fri, 3 Dec 2021 16:37:34 +0530 [thread overview] Message-ID: <20211203110734.23e2t356s45ux5mu@ti.com> (raw) In-Reply-To: <20211113043638.4358-1-nm@ti.com> On 12/11/21 10:36PM, Nishanth Menon wrote: > A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of ^^^ Same as previous patch, do you mean A72? J7200 does not have an A53 core and this cache node is for A72 cores anyway. With this fixed, Reviewed-by: Pratyush Yadav <p.yadav@ti.com> > 64 bytes and 16-way set-associative cache structure. > > 1MB of L2 / 64 (line length) = 16384 ways > 16384 ways / 16 = 1024 sets > > Fix the l2 cache-sets. > > [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system > [2] https://www.ti.com/lit/pdf/spruiu1 > > Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") > Reported-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Nishanth Menon <nm@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > index 958587d3a33d..64fef4e67d76 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > @@ -86,7 +86,7 @@ L2_0: l2-cache0 { > cache-level = <2>; > cache-size = <0x100000>; > cache-line-size = <64>; > - cache-sets = <2048>; > + cache-sets = <1024>; > next-level-cache = <&msmc_l3>; > }; > -- Regards, Pratyush Yadav Texas Instruments Inc. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-03 11:07 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-13 4:36 [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets Nishanth Menon 2021-11-13 4:36 ` Nishanth Menon 2021-12-03 11:07 ` Pratyush Yadav [this message] 2021-12-03 11:07 ` Pratyush Yadav 2021-12-06 13:10 ` Vignesh Raghavendra 2021-12-06 13:10 ` Vignesh Raghavendra
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