All of lore.kernel.org
 help / color / mirror / Atom feed
From: Leo Yan <leo.yan@linaro.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: John Garry <john.garry@huawei.com>,
	Jean-Philippe Brucker <jean-philippe@linaro.org>,
	mark.rutland@arm.com, devicetree@vger.kernel.org,
	iommu@lists.linux-foundation.org, uchida.jun@socionext.com,
	will@kernel.org, linux-arm-kernel@lists.infradead.org,
	robh+dt@kernel.org
Subject: Re: [PATCH v2 3/3] perf/smmuv3: Synthesize IIDR from CoreSight ID registers
Date: Tue, 7 Dec 2021 21:20:07 +0800	[thread overview]
Message-ID: <20211207132007.GB255238@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <d60110c4-c179-45d6-512d-3d058caac974@arm.com>

On Tue, Dec 07, 2021 at 12:48:13PM +0000, Robin Murphy wrote:
> On 2021-12-07 12:28, John Garry via iommu wrote:
> > On 07/12/2021 12:04, Robin Murphy wrote:
> > > > > 
> > > > So is there some userspace part to go with this now?
> > > 
> > > FWIW I've not looked into it - is it just a case of someone knocking
> > > out some JSON from the MMU-600/700 TRMs, or is there still mroe to
> > > do?
> > 
> > That should just be it.

Hope I didn't arrive too late :)

Yes, I think we just missed two things: the DT binding for SMMUv3 PMU
which is just addressed by this patchset; and the PMU event aliasing
for SMMUv3 PMU, before I inquired with John and John said he would
upstream the related patches after kernel can export a IIDR value via
sysfs node.

Seems to me, after this patchset for DT binding and PMU event alias
patches are landed to the mainline kernel, it would be perfect.

> > > I had the impression that *some* part of the process was stalled
> > > until implementations can start providing meaningful IIDRs, but I
> > > wasn't sure whether that was tooling or just data. I just work the
> > > low-level enablement angle :)
> > 
> > Tooling should be ok, but I would just like to see more of these JSONs
> > so any tooling issues can be ironed out.
> 
> Sounds good - Jean, Leo, is that something Linaro might like to pick up as
> part of the PMCG interest, or shall I make a note on my to-do list for the
> new year?

I took a look for current patch for using PIDR to synthesize IIDR, it
looks good to me.  But I tested it on Hisilicon D06 board and observed
the composed IIDR values are still zeros.

I added a printk sentence to dump iidr value at the end of the function
smmu_pmu_get_iidr():

  leoy@ubuntu:~$ dmesg | grep iidr
  [   28.674087] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.8.auto: iidr=0x0
  [   28.705239] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.9.auto: iidr=0x0
  [   28.729924] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.10.auto: iidr=0x0
  [   28.754855] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.11.auto: iidr=0x0
  [   28.779811] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.12.auto: iidr=0x0
  [   28.804755] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.13.auto: iidr=0x0
  [   28.829825] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.14.auto: iidr=0x0
  [   28.854767] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.15.auto: iidr=0x0

Please confirm if this is expected or not?  I think this might
introduce difficulty for John for the PMU event alias patches, which
is dependent on a non-zero IIDR.

At last, very appreciate your (Jean-Philippe, Robin and John) help!

Thanks,
Leo

WARNING: multiple messages have this Message-ID (diff)
From: Leo Yan <leo.yan@linaro.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: John Garry <john.garry@huawei.com>,
	Jean-Philippe Brucker <jean-philippe@linaro.org>,
	mark.rutland@arm.com, devicetree@vger.kernel.org,
	iommu@lists.linux-foundation.org, uchida.jun@socionext.com,
	will@kernel.org, linux-arm-kernel@lists.infradead.org,
	robh+dt@kernel.org
Subject: Re: [PATCH v2 3/3] perf/smmuv3: Synthesize IIDR from CoreSight ID registers
Date: Tue, 7 Dec 2021 21:20:07 +0800	[thread overview]
Message-ID: <20211207132007.GB255238@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <d60110c4-c179-45d6-512d-3d058caac974@arm.com>

On Tue, Dec 07, 2021 at 12:48:13PM +0000, Robin Murphy wrote:
> On 2021-12-07 12:28, John Garry via iommu wrote:
> > On 07/12/2021 12:04, Robin Murphy wrote:
> > > > > 
> > > > So is there some userspace part to go with this now?
> > > 
> > > FWIW I've not looked into it - is it just a case of someone knocking
> > > out some JSON from the MMU-600/700 TRMs, or is there still mroe to
> > > do?
> > 
> > That should just be it.

Hope I didn't arrive too late :)

Yes, I think we just missed two things: the DT binding for SMMUv3 PMU
which is just addressed by this patchset; and the PMU event aliasing
for SMMUv3 PMU, before I inquired with John and John said he would
upstream the related patches after kernel can export a IIDR value via
sysfs node.

Seems to me, after this patchset for DT binding and PMU event alias
patches are landed to the mainline kernel, it would be perfect.

> > > I had the impression that *some* part of the process was stalled
> > > until implementations can start providing meaningful IIDRs, but I
> > > wasn't sure whether that was tooling or just data. I just work the
> > > low-level enablement angle :)
> > 
> > Tooling should be ok, but I would just like to see more of these JSONs
> > so any tooling issues can be ironed out.
> 
> Sounds good - Jean, Leo, is that something Linaro might like to pick up as
> part of the PMCG interest, or shall I make a note on my to-do list for the
> new year?

I took a look for current patch for using PIDR to synthesize IIDR, it
looks good to me.  But I tested it on Hisilicon D06 board and observed
the composed IIDR values are still zeros.

I added a printk sentence to dump iidr value at the end of the function
smmu_pmu_get_iidr():

  leoy@ubuntu:~$ dmesg | grep iidr
  [   28.674087] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.8.auto: iidr=0x0
  [   28.705239] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.9.auto: iidr=0x0
  [   28.729924] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.10.auto: iidr=0x0
  [   28.754855] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.11.auto: iidr=0x0
  [   28.779811] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.12.auto: iidr=0x0
  [   28.804755] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.13.auto: iidr=0x0
  [   28.829825] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.14.auto: iidr=0x0
  [   28.854767] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.15.auto: iidr=0x0

Please confirm if this is expected or not?  I think this might
introduce difficulty for John for the PMU event alias patches, which
is dependent on a non-zero IIDR.

At last, very appreciate your (Jean-Philippe, Robin and John) help!

Thanks,
Leo

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Leo Yan <leo.yan@linaro.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: mark.rutland@arm.com,
	Jean-Philippe Brucker <jean-philippe@linaro.org>,
	devicetree@vger.kernel.org, iommu@lists.linux-foundation.org,
	robh+dt@kernel.org, uchida.jun@socionext.com, will@kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/3] perf/smmuv3: Synthesize IIDR from CoreSight ID registers
Date: Tue, 7 Dec 2021 21:20:07 +0800	[thread overview]
Message-ID: <20211207132007.GB255238@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <d60110c4-c179-45d6-512d-3d058caac974@arm.com>

On Tue, Dec 07, 2021 at 12:48:13PM +0000, Robin Murphy wrote:
> On 2021-12-07 12:28, John Garry via iommu wrote:
> > On 07/12/2021 12:04, Robin Murphy wrote:
> > > > > 
> > > > So is there some userspace part to go with this now?
> > > 
> > > FWIW I've not looked into it - is it just a case of someone knocking
> > > out some JSON from the MMU-600/700 TRMs, or is there still mroe to
> > > do?
> > 
> > That should just be it.

Hope I didn't arrive too late :)

Yes, I think we just missed two things: the DT binding for SMMUv3 PMU
which is just addressed by this patchset; and the PMU event aliasing
for SMMUv3 PMU, before I inquired with John and John said he would
upstream the related patches after kernel can export a IIDR value via
sysfs node.

Seems to me, after this patchset for DT binding and PMU event alias
patches are landed to the mainline kernel, it would be perfect.

> > > I had the impression that *some* part of the process was stalled
> > > until implementations can start providing meaningful IIDRs, but I
> > > wasn't sure whether that was tooling or just data. I just work the
> > > low-level enablement angle :)
> > 
> > Tooling should be ok, but I would just like to see more of these JSONs
> > so any tooling issues can be ironed out.
> 
> Sounds good - Jean, Leo, is that something Linaro might like to pick up as
> part of the PMCG interest, or shall I make a note on my to-do list for the
> new year?

I took a look for current patch for using PIDR to synthesize IIDR, it
looks good to me.  But I tested it on Hisilicon D06 board and observed
the composed IIDR values are still zeros.

I added a printk sentence to dump iidr value at the end of the function
smmu_pmu_get_iidr():

  leoy@ubuntu:~$ dmesg | grep iidr
  [   28.674087] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.8.auto: iidr=0x0
  [   28.705239] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.9.auto: iidr=0x0
  [   28.729924] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.10.auto: iidr=0x0
  [   28.754855] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.11.auto: iidr=0x0
  [   28.779811] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.12.auto: iidr=0x0
  [   28.804755] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.13.auto: iidr=0x0
  [   28.829825] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.14.auto: iidr=0x0
  [   28.854767] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.15.auto: iidr=0x0

Please confirm if this is expected or not?  I think this might
introduce difficulty for John for the PMU event alias patches, which
is dependent on a non-zero IIDR.

At last, very appreciate your (Jean-Philippe, Robin and John) help!

Thanks,
Leo
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  reply	other threads:[~2021-12-07 13:20 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-17 14:48 [PATCH v2 0/3] perf/smmuv3: Support devicetree Jean-Philippe Brucker
2021-11-17 14:48 ` Jean-Philippe Brucker
2021-11-17 14:48 ` Jean-Philippe Brucker
2021-11-17 14:48 ` [PATCH v2 1/3] dt-bindings: Add Arm SMMUv3 PMCG binding Jean-Philippe Brucker
2021-11-17 14:48   ` Jean-Philippe Brucker
2021-11-17 14:48   ` Jean-Philippe Brucker
2021-11-17 14:48 ` [PATCH v2 2/3] perf/smmuv3: Add devicetree support Jean-Philippe Brucker
2021-11-17 14:48   ` Jean-Philippe Brucker
2021-11-17 14:48   ` Jean-Philippe Brucker
2021-11-17 14:48 ` [PATCH v2 3/3] perf/smmuv3: Synthesize IIDR from CoreSight ID registers Jean-Philippe Brucker
2021-11-17 14:48   ` Jean-Philippe Brucker
2021-11-17 14:48   ` Jean-Philippe Brucker
2021-12-07  9:14   ` John Garry
2021-12-07  9:14     ` John Garry
2021-12-07  9:14     ` John Garry via iommu
2021-12-07 12:04     ` Robin Murphy
2021-12-07 12:04       ` Robin Murphy
2021-12-07 12:04       ` Robin Murphy
2021-12-07 12:28       ` John Garry
2021-12-07 12:28         ` John Garry
2021-12-07 12:28         ` John Garry via iommu
2021-12-07 12:48         ` Robin Murphy
2021-12-07 12:48           ` Robin Murphy
2021-12-07 12:48           ` Robin Murphy
2021-12-07 13:20           ` Leo Yan [this message]
2021-12-07 13:20             ` Leo Yan
2021-12-07 13:20             ` Leo Yan
2021-12-07 13:46             ` Robin Murphy
2021-12-07 13:46               ` Robin Murphy
2021-12-07 13:46               ` Robin Murphy
2021-12-07 13:59               ` Leo Yan
2021-12-07 13:59                 ` Leo Yan
2021-12-07 13:59                 ` Leo Yan
2021-12-07 14:00                 ` John Garry
2021-12-07 14:00                   ` John Garry
2021-12-07 14:00                   ` John Garry via iommu
2021-12-07 14:04                   ` Leo Yan
2021-12-07 14:04                     ` Leo Yan
2021-12-07 14:04                     ` Leo Yan
2021-12-14 14:04 ` [PATCH v2 0/3] perf/smmuv3: Support devicetree Will Deacon
2021-12-14 14:04   ` Will Deacon
2021-12-14 14:04   ` Will Deacon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211207132007.GB255238@leoy-ThinkPad-X240s \
    --to=leo.yan@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=iommu@lists.linux-foundation.org \
    --cc=jean-philippe@linaro.org \
    --cc=john.garry@huawei.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=mark.rutland@arm.com \
    --cc=robh+dt@kernel.org \
    --cc=robin.murphy@arm.com \
    --cc=uchida.jun@socionext.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.