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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	alistair23@gmail.com, Alistair Francis <Alistair.Francis@wdc.com>,
	bmeng.cn@gmail.com
Subject: [PATCH 1/7] hw/intc: sifive_plic: Add a reset function
Date: Wed,  8 Dec 2021 16:42:46 +1000	[thread overview]
Message-ID: <20211208064252.375360-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211208064252.375360-1-alistair.francis@opensource.wdc.com>

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 877e76877c..35f097799a 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -355,6 +355,17 @@ static const MemoryRegionOps sifive_plic_ops = {
     }
 };
 
+static void sifive_plic_reset(DeviceState *dev)
+{
+    SiFivePLICState *s = SIFIVE_PLIC(dev);
+
+    memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
+    memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
+    memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
+    memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
+    memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
+}
+
 /*
  * parse PLIC hart/mode address offset config
  *
@@ -501,6 +512,7 @@ static void sifive_plic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
+    dc->reset = sifive_plic_reset;
     device_class_set_props(dc, sifive_plic_properties);
     dc->realize = sifive_plic_realize;
     dc->vmsd = &vmstate_sifive_plic;
-- 
2.31.1



  reply	other threads:[~2021-12-08  6:52 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-08  6:42 [PATCH 0/7] A collection of RISC-V cleanups and improvements Alistair Francis
2021-12-08  6:42 ` Alistair Francis [this message]
2021-12-08 12:00   ` [PATCH 1/7] hw/intc: sifive_plic: Add a reset function Philippe Mathieu-Daudé
2021-12-08 12:00     ` Philippe Mathieu-Daudé
2021-12-10  2:12     ` Alistair Francis
2021-12-10  2:12       ` Alistair Francis
2021-12-08  6:42 ` [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2021-12-08 17:30   ` Richard Henderson
2021-12-08 17:30     ` Richard Henderson
2021-12-08  6:42 ` [PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2021-12-08  6:42 ` [PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-12-08  6:42 ` [PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2021-12-08  6:42 ` [PATCH 6/7] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2021-12-08  6:42 ` [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2021-12-08 11:51   ` Philippe Mathieu-Daudé
2021-12-08 11:51     ` Philippe Mathieu-Daudé
2021-12-10  7:10   ` Markus Armbruster
2021-12-10  7:10     ` Markus Armbruster

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