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From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@opensource.wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	bmeng.cn@gmail.com, alistair23@gmail.com
Subject: Re: [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function
Date: Wed, 8 Dec 2021 09:30:22 -0800	[thread overview]
Message-ID: <670c37f6-092b-f569-d984-1f640c12346d@linaro.org> (raw)
In-Reply-To: <20211208064252.375360-3-alistair.francis@opensource.wdc.com>

On 12/7/21 10:42 PM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>   hw/intc/sifive_plic.c | 82 +++++++++++++++++--------------------------
>   1 file changed, 33 insertions(+), 49 deletions(-)
> 
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 35f097799a..c1fa689868 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -33,6 +33,17 @@
>   
>   #define RISCV_DEBUG_PLIC 0
>   
> +static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
> +{
> +    uint32_t end = base + num;
> +
> +    if (addr >= base && addr < end) {
> +        return true;
> +    }
> +
> +    return false;
> +}

It may well not matter for your use case, but this will fail for addresses at the end of 
the range.  Better as

     return addr >= base && addr - base < num;


r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@opensource.wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	alistair23@gmail.com, bmeng.cn@gmail.com
Subject: Re: [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function
Date: Wed, 8 Dec 2021 09:30:22 -0800	[thread overview]
Message-ID: <670c37f6-092b-f569-d984-1f640c12346d@linaro.org> (raw)
In-Reply-To: <20211208064252.375360-3-alistair.francis@opensource.wdc.com>

On 12/7/21 10:42 PM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>   hw/intc/sifive_plic.c | 82 +++++++++++++++++--------------------------
>   1 file changed, 33 insertions(+), 49 deletions(-)
> 
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 35f097799a..c1fa689868 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -33,6 +33,17 @@
>   
>   #define RISCV_DEBUG_PLIC 0
>   
> +static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
> +{
> +    uint32_t end = base + num;
> +
> +    if (addr >= base && addr < end) {
> +        return true;
> +    }
> +
> +    return false;
> +}

It may well not matter for your use case, but this will fail for addresses at the end of 
the range.  Better as

     return addr >= base && addr - base < num;


r~


  reply	other threads:[~2021-12-08 17:31 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-08  6:42 [PATCH 0/7] A collection of RISC-V cleanups and improvements Alistair Francis
2021-12-08  6:42 ` [PATCH 1/7] hw/intc: sifive_plic: Add a reset function Alistair Francis
2021-12-08 12:00   ` Philippe Mathieu-Daudé
2021-12-08 12:00     ` Philippe Mathieu-Daudé
2021-12-10  2:12     ` Alistair Francis
2021-12-10  2:12       ` Alistair Francis
2021-12-08  6:42 ` [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2021-12-08 17:30   ` Richard Henderson [this message]
2021-12-08 17:30     ` Richard Henderson
2021-12-08  6:42 ` [PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2021-12-08  6:42 ` [PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-12-08  6:42 ` [PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2021-12-08  6:42 ` [PATCH 6/7] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2021-12-08  6:42 ` [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2021-12-08 11:51   ` Philippe Mathieu-Daudé
2021-12-08 11:51     ` Philippe Mathieu-Daudé
2021-12-10  7:10   ` Markus Armbruster
2021-12-10  7:10     ` Markus Armbruster

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