* [PATCH v5 0/4] Add Naneng combo PHY support for RK3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Changes in v5: - modify description for ssc and ext-refclk - remove apb reset - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name - rename node name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Fix dtschema/dtc warnings/errors - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. - Move phy0 to rk3568.dtsi Johan Jonker (1): dt-bindings: mfd: syscon: add naneng combo phy register compatible Yifeng Zhao (3): dt-bindings: phy: rockchip: Add Naneng combo PHY bindings phy: rockchip: add naneng combo phy for RK3568 arm64: dts: rockchip: add naneng combo phy nodes for rk3568 .../devicetree/bindings/mfd/syscon.yaml | 2 + .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++ drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 7 files changed, 823 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 0/4] Add Naneng combo PHY support for RK3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Changes in v5: - modify description for ssc and ext-refclk - remove apb reset - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name - rename node name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Fix dtschema/dtc warnings/errors - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. - Move phy0 to rk3568.dtsi Johan Jonker (1): dt-bindings: mfd: syscon: add naneng combo phy register compatible Yifeng Zhao (3): dt-bindings: phy: rockchip: Add Naneng combo PHY bindings phy: rockchip: add naneng combo phy for RK3568 arm64: dts: rockchip: add naneng combo phy nodes for rk3568 .../devicetree/bindings/mfd/syscon.yaml | 2 + .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++ drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 7 files changed, 823 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -- 2.17.1 ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 0/4] Add Naneng combo PHY support for RK3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Changes in v5: - modify description for ssc and ext-refclk - remove apb reset - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name - rename node name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Fix dtschema/dtc warnings/errors - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. - Move phy0 to rk3568.dtsi Johan Jonker (1): dt-bindings: mfd: syscon: add naneng combo phy register compatible Yifeng Zhao (3): dt-bindings: phy: rockchip: Add Naneng combo PHY bindings phy: rockchip: add naneng combo phy for RK3568 arm64: dts: rockchip: add naneng combo phy nodes for rk3568 .../devicetree/bindings/mfd/syscon.yaml | 2 + .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++ drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 7 files changed, 823 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 0/4] Add Naneng combo PHY support for RK3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Changes in v5: - modify description for ssc and ext-refclk - remove apb reset - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name - rename node name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Fix dtschema/dtc warnings/errors - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. - Move phy0 to rk3568.dtsi Johan Jonker (1): dt-bindings: mfd: syscon: add naneng combo phy register compatible Yifeng Zhao (3): dt-bindings: phy: rockchip: Add Naneng combo PHY bindings phy: rockchip: add naneng combo phy for RK3568 arm64: dts: rockchip: add naneng combo phy nodes for rk3568 .../devicetree/bindings/mfd/syscon.yaml | 2 + .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++ drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 7 files changed, 823 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -- 2.17.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 1/4] dt-bindings: mfd: syscon: add naneng combo phy register compatible 2021-12-15 9:56 ` Yifeng Zhao (?) (?) @ 2021-12-15 9:56 ` Yifeng Zhao -1 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao From: Johan Jonker <jbx6244@gmail.com> Add naneng combo phy register compatible. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index fdd96e378df0..e9bb96ab9446 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -52,6 +52,8 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3568-pipe-grf + - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 1/4] dt-bindings: mfd: syscon: add naneng combo phy register compatible @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao From: Johan Jonker <jbx6244@gmail.com> Add naneng combo phy register compatible. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index fdd96e378df0..e9bb96ab9446 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -52,6 +52,8 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3568-pipe-grf + - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg -- 2.17.1 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 1/4] dt-bindings: mfd: syscon: add naneng combo phy register compatible @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao From: Johan Jonker <jbx6244@gmail.com> Add naneng combo phy register compatible. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index fdd96e378df0..e9bb96ab9446 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -52,6 +52,8 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3568-pipe-grf + - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg -- 2.17.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 1/4] dt-bindings: mfd: syscon: add naneng combo phy register compatible @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao From: Johan Jonker <jbx6244@gmail.com> Add naneng combo phy register compatible. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index fdd96e378df0..e9bb96ab9446 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -52,6 +52,8 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3568-pipe-grf + - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings 2021-12-15 9:56 ` Yifeng Zhao (?) (?) @ 2021-12-15 9:56 ` Yifeng Zhao -1 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the compatible strings for the Naneng combo PHY found on rockchip SoC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - modify description for ssc and ext-refclk - remove apb reset Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: None Changes in v2: - Fix dtschema/dtc warnings/errors .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml new file mode 100644 index 000000000000..6b2db5e39f76 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC Naneng Combo Phy Device Tree Bindings + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-naneng-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: reference clock + - description: apb clock + - description: pipe clock + + clock-names: + items: + - const: ref + - const: apb + - const: pipe + + resets: + items: + - description: exclusive PHY reset line + + rockchip,dis-u3otg0-port: + type: boolean + description: + Disable the u3otg0 port. + + rockchip,dis-u3otg1-port: + type: boolean + description: + Disable the u3otg1 port. + + rockchip,enable-ssc: + type: boolean + description: + The option SSC can be enabled for U3, SATA and PCIE. + Most commercially available platforms use SSC to reduce EMI. + + rockchip,ext-refclk: + type: boolean + description: + Many PCIe connections, especially backplane connections, + require a synchronous reference clock between the two link partners. + To achieve this a common clock source, referred to as REFCLK in + the PCI Express Card Electromechanical Specification, + should be used by both ends of the PCIe link. + In PCIe mode, the reference clock can choose to use internal clock + or external clock. + By default, the internal clock is selected, The PCIe PHY provides + 100MHz differential clock output(optional with SSC) for system applications. + When selecting This option to used external reference clock, a externally + 100MHz differential clock is needs to be provided for PCIe PHY. + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional phy settings are accessed through GRF regs. + + rockchip,pipe-phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional pipe settings are accessed through GRF regs. + + rockchip,sgmii-mac-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 0 + description: + Select gmac0 or gmac1 to be used as SGMII controller. + + "#phy-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - rockchip,pipe-grf + - rockchip,pipe-phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0xfdc50000 0x1000>; + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0xfdc70000 0x1000>; + }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0xfe820000 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the compatible strings for the Naneng combo PHY found on rockchip SoC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - modify description for ssc and ext-refclk - remove apb reset Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: None Changes in v2: - Fix dtschema/dtc warnings/errors .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml new file mode 100644 index 000000000000..6b2db5e39f76 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC Naneng Combo Phy Device Tree Bindings + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-naneng-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: reference clock + - description: apb clock + - description: pipe clock + + clock-names: + items: + - const: ref + - const: apb + - const: pipe + + resets: + items: + - description: exclusive PHY reset line + + rockchip,dis-u3otg0-port: + type: boolean + description: + Disable the u3otg0 port. + + rockchip,dis-u3otg1-port: + type: boolean + description: + Disable the u3otg1 port. + + rockchip,enable-ssc: + type: boolean + description: + The option SSC can be enabled for U3, SATA and PCIE. + Most commercially available platforms use SSC to reduce EMI. + + rockchip,ext-refclk: + type: boolean + description: + Many PCIe connections, especially backplane connections, + require a synchronous reference clock between the two link partners. + To achieve this a common clock source, referred to as REFCLK in + the PCI Express Card Electromechanical Specification, + should be used by both ends of the PCIe link. + In PCIe mode, the reference clock can choose to use internal clock + or external clock. + By default, the internal clock is selected, The PCIe PHY provides + 100MHz differential clock output(optional with SSC) for system applications. + When selecting This option to used external reference clock, a externally + 100MHz differential clock is needs to be provided for PCIe PHY. + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional phy settings are accessed through GRF regs. + + rockchip,pipe-phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional pipe settings are accessed through GRF regs. + + rockchip,sgmii-mac-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 0 + description: + Select gmac0 or gmac1 to be used as SGMII controller. + + "#phy-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - rockchip,pipe-grf + - rockchip,pipe-phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0xfdc50000 0x1000>; + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0xfdc70000 0x1000>; + }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0xfe820000 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + }; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the compatible strings for the Naneng combo PHY found on rockchip SoC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - modify description for ssc and ext-refclk - remove apb reset Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: None Changes in v2: - Fix dtschema/dtc warnings/errors .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml new file mode 100644 index 000000000000..6b2db5e39f76 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC Naneng Combo Phy Device Tree Bindings + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-naneng-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: reference clock + - description: apb clock + - description: pipe clock + + clock-names: + items: + - const: ref + - const: apb + - const: pipe + + resets: + items: + - description: exclusive PHY reset line + + rockchip,dis-u3otg0-port: + type: boolean + description: + Disable the u3otg0 port. + + rockchip,dis-u3otg1-port: + type: boolean + description: + Disable the u3otg1 port. + + rockchip,enable-ssc: + type: boolean + description: + The option SSC can be enabled for U3, SATA and PCIE. + Most commercially available platforms use SSC to reduce EMI. + + rockchip,ext-refclk: + type: boolean + description: + Many PCIe connections, especially backplane connections, + require a synchronous reference clock between the two link partners. + To achieve this a common clock source, referred to as REFCLK in + the PCI Express Card Electromechanical Specification, + should be used by both ends of the PCIe link. + In PCIe mode, the reference clock can choose to use internal clock + or external clock. + By default, the internal clock is selected, The PCIe PHY provides + 100MHz differential clock output(optional with SSC) for system applications. + When selecting This option to used external reference clock, a externally + 100MHz differential clock is needs to be provided for PCIe PHY. + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional phy settings are accessed through GRF regs. + + rockchip,pipe-phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional pipe settings are accessed through GRF regs. + + rockchip,sgmii-mac-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 0 + description: + Select gmac0 or gmac1 to be used as SGMII controller. + + "#phy-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - rockchip,pipe-grf + - rockchip,pipe-phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0xfdc50000 0x1000>; + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0xfdc70000 0x1000>; + }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0xfe820000 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the compatible strings for the Naneng combo PHY found on rockchip SoC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - modify description for ssc and ext-refclk - remove apb reset Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: None Changes in v2: - Fix dtschema/dtc warnings/errors .../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml new file mode 100644 index 000000000000..6b2db5e39f76 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC Naneng Combo Phy Device Tree Bindings + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-naneng-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: reference clock + - description: apb clock + - description: pipe clock + + clock-names: + items: + - const: ref + - const: apb + - const: pipe + + resets: + items: + - description: exclusive PHY reset line + + rockchip,dis-u3otg0-port: + type: boolean + description: + Disable the u3otg0 port. + + rockchip,dis-u3otg1-port: + type: boolean + description: + Disable the u3otg1 port. + + rockchip,enable-ssc: + type: boolean + description: + The option SSC can be enabled for U3, SATA and PCIE. + Most commercially available platforms use SSC to reduce EMI. + + rockchip,ext-refclk: + type: boolean + description: + Many PCIe connections, especially backplane connections, + require a synchronous reference clock between the two link partners. + To achieve this a common clock source, referred to as REFCLK in + the PCI Express Card Electromechanical Specification, + should be used by both ends of the PCIe link. + In PCIe mode, the reference clock can choose to use internal clock + or external clock. + By default, the internal clock is selected, The PCIe PHY provides + 100MHz differential clock output(optional with SSC) for system applications. + When selecting This option to used external reference clock, a externally + 100MHz differential clock is needs to be provided for PCIe PHY. + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional phy settings are accessed through GRF regs. + + rockchip,pipe-phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional pipe settings are accessed through GRF regs. + + rockchip,sgmii-mac-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 0 + description: + Select gmac0 or gmac1 to be used as SGMII controller. + + "#phy-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - rockchip,pipe-grf + - rockchip,pipe-phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0xfdc50000 0x1000>; + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0xfdc70000 0x1000>; + }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0xfe820000 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + }; -- 2.17.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 2021-12-15 9:56 ` Yifeng Zhao (?) (?) @ 2021-12-15 9:56 ` Yifeng Zhao -1 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This patch implements a combo phy driver for Rockchip SoCs with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. Changes in v2: - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 3 files changed, 627 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index e812adad7242..9022e395c056 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY Enable this to support the Rockchip MIPI/LVDS/TTL PHY with Innosilicon IP block. +config PHY_ROCKCHIP_NANENG_COMBO_PHY + tristate "Rockchip NANENG COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII + combo PHY with NaNeng IP block. + config PHY_ROCKCHIP_PCIE tristate "Rockchip PCIe PHY Driver" depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index f0eec212b2aa..a5041efb5b8f 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c new file mode 100644 index 000000000000..4fa150dbe7eb --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PIPE USB3.0 PCIE SATA combphy driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <dt-bindings/phy/phy.h> + +#define BIT_WRITEABLE_SHIFT 16 +#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) +#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) +#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) + +/* RK3568 T22 COMBO PHY REG */ +#define RK3568_T22_PHYREG5 0x14 +#define T22_PHYREG5_PLL_DIV_MASK GENMASK(7, 6) +#define T22_PHYREG5_PLL_DIV_SHIFT 6 +#define T22_PHYREG5_PLL_DIV_2 1 + +#define RK3568_T22_PHYREG6 0x18 +#define T22_PHYREG6_TX_RTERM_MASK GENMASK(7, 4) +#define T22_PHYREG6_TX_RTERM_SHIFT 4 +#define T22_PHYREG6_TX_RTERM_50OHM 8 +#define T22_PHYREG6_RX_RTERM_MASK GENMASK(3, 0) +#define T22_PHYREG6_RX_RTERM_SHIFT 0 +#define T22_PHYREG6_RX_RTERM_44OHM 15 + +#define RK3568_T22_PHYREG7 0x1C +#define T22_PHYREG7_SSC_EN BIT(4) + +#define RK3568_T22_PHYREG10 0x28 +#define T22_PHYREG10_SU_TRIM_0_7 0xF0 + +#define RK3568_T22_PHYREG11 0x2C +#define T22_PHYREG11_PLL_LPF_ADJ_VALUE 4 + +#define RK3568_T22_PHYREG12 0x30 +#define T22_PHYREG12_RESISTER_MASK GENMASK(5, 4) +#define T22_PHYREG12_RESISTER_SHIFT 0x4 +#define T22_PHYREG12_RESISTER_HIGH_Z 3 +#define T22_PHYREG12_CKRCV_AMP0 BIT(7) + +#define RK3568_T22_PHYREG13 0x34 +#define T22_PHYREG13_CKRCV_AMP1 BIT(0) + +#define RK3568_T22_PHYREG14 0x38 +#define T22_PHYREG14_CTLE_EN BIT(0) +#define T22_PHYREG14_SSC_CNT_MASK GENMASK(7, 6) +#define T22_PHYREG14_SSC_CNT_SHIFT 6 +#define T22_PHYREG14_SSC_CNT_VALUE 1 + +#define RK3568_T22_PHYREG15 0x3C +#define T22_PHYREG15_SSC_CNT_VALUE 0x5f + +#define RK3568_T22_PHYREG17 0x44 +#define T22_PHYREG17_PLL_LOOP 0x32 + +#define RK3568_T22_PHYREG31 0x7C +#define T22_PHYREG31_SSC_MASK GENMASK(7, 4) +#define T22_PHYREG31_SSC_DIR_SHIFT 4 +#define T22_PHYREG31_SSC_UPWARD 0 +#define T22_PHYREG31_SSC_DOWNWARD 1 +#define T22_PHYREG31_SSC_OFFSET_SHIFT 6 +#define T22_PHYREG31_SSC_OFFSET_500PPM 1 + +#define RK3568_T22_PHYREG32 0x80 +#define T22_PHYREG32_PLL_KVCO_MASK GENMASK(4, 2) +#define T22_PHYREG32_PLL_KVCO_SHIFT 2 +#define T22_PHYREG32_PLL_KVCO_VALUE 2 + +struct rockchip_combphy_priv; + +struct combphy_reg { + u16 offset; + u16 bitend; + u16 bitstart; + u16 disable; + u16 enable; +}; + +struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; + struct combphy_reg pipe_rate_sel; + struct combphy_reg pipe_rxterm_sel; + struct combphy_reg pipe_txelec_sel; + struct combphy_reg pipe_txcomp_sel; + struct combphy_reg pipe_clk_ext; + struct combphy_reg pipe_sel_usb; + struct combphy_reg pipe_sel_qsgmii; + struct combphy_reg pipe_phy_status; + struct combphy_reg con0_for_pcie; + struct combphy_reg con1_for_pcie; + struct combphy_reg con2_for_pcie; + struct combphy_reg con3_for_pcie; + struct combphy_reg con0_for_sata; + struct combphy_reg con1_for_sata; + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; +}; + +struct rockchip_combphy_cfg { + const struct rockchip_combphy_grfcfg *grfcfg; + int (*combphy_cfg)(struct rockchip_combphy_priv *priv); +}; + +struct rockchip_combphy_priv { + u8 mode; + void __iomem *mmio; + int num_clks; + struct clk_bulk_data *clks; + struct device *dev; + struct regmap *pipe_grf; + struct regmap *phy_grf; + struct phy *phy; + struct reset_control *phy_rst; + const struct rockchip_combphy_cfg *cfg; + bool enable_ssc; + bool ext_refclk; + struct clk *refclk; +}; + +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, + int mask, int val, int reg) +{ + unsigned int temp; + + temp = readl(priv->mmio + reg); + temp = (temp & ~(mask)) | val; + writel(temp, priv->mmio + reg); +} + +static int rockchip_combphy_param_write(struct regmap *base, + const struct combphy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 mask, val; + + mask = GENMASK(cfg->pipe_phy_status.bitend, + cfg->pipe_phy_status.bitstart); + + regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); + val = (val & mask) >> cfg->pipe_phy_status.bitstart; + + return val; +} + +static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + case PHY_TYPE_USB3: + case PHY_TYPE_SATA: + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + if (priv->cfg->combphy_cfg) + ret = priv->cfg->combphy_cfg(priv); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + if (ret) + dev_err(priv->dev, "failed to init phy for phy mode %x\n", priv->mode); + + return ret; +} + +static int rockchip_combphy_init(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(priv->dev, "failed to enable clks\n"); + return ret; + } + + ret = rockchip_combphy_set_mode(priv); + if (ret) + goto err_clk; + + ret = reset_control_deassert(priv->phy_rst); + if (ret) + goto err_clk; + + if (priv->mode == PHY_TYPE_USB3) { + ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, + priv, val, + val == cfg->pipe_phy_status.enable, + 10, 1000); + if (ret) + dev_warn(priv->dev, "wait phy status ready timeout\n"); + } + + return 0; + +err_clk: + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + + return ret; +} + +static int rockchip_combphy_exit(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->phy_rst); + + return 0; +} + +static const struct phy_ops rochchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, + .owner = THIS_MODULE, +}; + +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) +{ + struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->mode != PHY_NONE && priv->mode != args->args[0]) + dev_warn(dev, "phy type select %d overwriting type %d\n", + args->args[0], priv->mode); + + priv->mode = args->args[0]; + + return priv->phy; +} + +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; + int mac_id; + int i; + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -EINVAL; + + priv->refclk = NULL; + for (i = 0; i < priv->num_clks; i++) { + if (!strncmp(priv->clks[i].id, "ref", 3)) { + priv->refclk = priv->clks[i].clk; + break; + } + } + + if (!priv->refclk) { + dev_err(dev, "no refclk found\n"); + return -EINVAL; + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + if (device_property_present(dev, "rockchip,dis-u3otg0-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, + false); + + if (device_property_present(dev, "rockchip,dis-u3otg1-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, + false); + + priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); + + priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); + + if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) && + (mac_id > 0)) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + true); + else + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + false); + + priv->phy_rst = devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); + + return 0; +} + +static int rockchip_combphy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_combphy_priv *priv; + const struct rockchip_combphy_cfg *phy_cfg; + struct resource *res; + int ret; + + phy_cfg = of_device_get_match_data(dev); + if (!phy_cfg) { + dev_err(dev, "no OF match data provided\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->dev = dev; + priv->mode = PHY_NONE; + priv->cfg = phy_cfg; + + ret = rockchip_combphy_parse_dt(dev, priv); + if (ret) + return ret; + + ret = reset_control_assert(priv->phy_rst); + if (ret) { + dev_err(dev, "failed to reset phy\n"); + return ret; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + /* Enable adaptive CTLE for USB3.0 Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + + /* Set PLL KVCO fine tuning signals. */ + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT, + RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + /* Set PLL input clock divider 1/2. */ + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT, + RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ + val = T22_PHYREG6_TX_RTERM_50OHM << T22_PHYREG6_TX_RTERM_SHIFT; + val |= T22_PHYREG6_RX_RTERM_44OHM << T22_PHYREG6_RX_RTERM_SHIFT; + writel(val, priv->mmio + RK3568_T22_PHYREG6); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + break; + + case PHY_TYPE_SGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); + break; + + case PHY_TYPE_QSGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); + break; + + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ + val = T22_PHYREG14_SSC_CNT_VALUE << T22_PHYREG14_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG14_SSC_CNT_MASK, + val, RK3568_T22_PHYREG14); + + writel(T22_PHYREG15_SSC_CNT_VALUE, priv->mmio + RK3568_T22_PHYREG15); + } + break; + + case REF_CLOCK_25MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ + val = T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + val, RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + val = T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + val, RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT; + val |= T22_PHYREG31_SSC_OFFSET_500PPM << T22_PHYREG31_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, val, RK3568_T22_PHYREG31); + writel(val, priv->mmio + RK3568_T22_PHYREG31); + } + break; + + default: + dev_err(priv->dev, "unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { + val = T22_PHYREG12_RESISTER_HIGH_Z << T22_PHYREG12_RESISTER_SHIFT; + val |= T22_PHYREG12_CKRCV_AMP0; + rockchip_combphy_updatel(priv, T22_PHYREG12_RESISTER_MASK, val, RK3568_T22_PHYREG12); + + val = readl(priv->mmio + RK3568_T22_PHYREG13); + val |= T22_PHYREG13_CKRCV_AMP1; + writel(val, priv->mmio + RK3568_T22_PHYREG13); + } + } + + if (priv->enable_ssc) { + val = readl(priv->mmio + RK3568_T22_PHYREG7); + val |= T22_PHYREG7_SSC_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG7); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, + .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .grfcfg = &rk3568_combphy_grfcfgs, + .combphy_cfg = rk3568_combphy_cfg, +}; + +static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); + +static struct platform_driver rockchip_combphy_driver = { + .probe = rockchip_combphy_probe, + .driver = { + .name = "rockchip-naneng-combphy", + .of_match_table = rockchip_combphy_of_match, + }, +}; +module_platform_driver(rockchip_combphy_driver); + +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This patch implements a combo phy driver for Rockchip SoCs with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. Changes in v2: - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 3 files changed, 627 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index e812adad7242..9022e395c056 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY Enable this to support the Rockchip MIPI/LVDS/TTL PHY with Innosilicon IP block. +config PHY_ROCKCHIP_NANENG_COMBO_PHY + tristate "Rockchip NANENG COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII + combo PHY with NaNeng IP block. + config PHY_ROCKCHIP_PCIE tristate "Rockchip PCIe PHY Driver" depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index f0eec212b2aa..a5041efb5b8f 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c new file mode 100644 index 000000000000..4fa150dbe7eb --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PIPE USB3.0 PCIE SATA combphy driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <dt-bindings/phy/phy.h> + +#define BIT_WRITEABLE_SHIFT 16 +#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) +#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) +#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) + +/* RK3568 T22 COMBO PHY REG */ +#define RK3568_T22_PHYREG5 0x14 +#define T22_PHYREG5_PLL_DIV_MASK GENMASK(7, 6) +#define T22_PHYREG5_PLL_DIV_SHIFT 6 +#define T22_PHYREG5_PLL_DIV_2 1 + +#define RK3568_T22_PHYREG6 0x18 +#define T22_PHYREG6_TX_RTERM_MASK GENMASK(7, 4) +#define T22_PHYREG6_TX_RTERM_SHIFT 4 +#define T22_PHYREG6_TX_RTERM_50OHM 8 +#define T22_PHYREG6_RX_RTERM_MASK GENMASK(3, 0) +#define T22_PHYREG6_RX_RTERM_SHIFT 0 +#define T22_PHYREG6_RX_RTERM_44OHM 15 + +#define RK3568_T22_PHYREG7 0x1C +#define T22_PHYREG7_SSC_EN BIT(4) + +#define RK3568_T22_PHYREG10 0x28 +#define T22_PHYREG10_SU_TRIM_0_7 0xF0 + +#define RK3568_T22_PHYREG11 0x2C +#define T22_PHYREG11_PLL_LPF_ADJ_VALUE 4 + +#define RK3568_T22_PHYREG12 0x30 +#define T22_PHYREG12_RESISTER_MASK GENMASK(5, 4) +#define T22_PHYREG12_RESISTER_SHIFT 0x4 +#define T22_PHYREG12_RESISTER_HIGH_Z 3 +#define T22_PHYREG12_CKRCV_AMP0 BIT(7) + +#define RK3568_T22_PHYREG13 0x34 +#define T22_PHYREG13_CKRCV_AMP1 BIT(0) + +#define RK3568_T22_PHYREG14 0x38 +#define T22_PHYREG14_CTLE_EN BIT(0) +#define T22_PHYREG14_SSC_CNT_MASK GENMASK(7, 6) +#define T22_PHYREG14_SSC_CNT_SHIFT 6 +#define T22_PHYREG14_SSC_CNT_VALUE 1 + +#define RK3568_T22_PHYREG15 0x3C +#define T22_PHYREG15_SSC_CNT_VALUE 0x5f + +#define RK3568_T22_PHYREG17 0x44 +#define T22_PHYREG17_PLL_LOOP 0x32 + +#define RK3568_T22_PHYREG31 0x7C +#define T22_PHYREG31_SSC_MASK GENMASK(7, 4) +#define T22_PHYREG31_SSC_DIR_SHIFT 4 +#define T22_PHYREG31_SSC_UPWARD 0 +#define T22_PHYREG31_SSC_DOWNWARD 1 +#define T22_PHYREG31_SSC_OFFSET_SHIFT 6 +#define T22_PHYREG31_SSC_OFFSET_500PPM 1 + +#define RK3568_T22_PHYREG32 0x80 +#define T22_PHYREG32_PLL_KVCO_MASK GENMASK(4, 2) +#define T22_PHYREG32_PLL_KVCO_SHIFT 2 +#define T22_PHYREG32_PLL_KVCO_VALUE 2 + +struct rockchip_combphy_priv; + +struct combphy_reg { + u16 offset; + u16 bitend; + u16 bitstart; + u16 disable; + u16 enable; +}; + +struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; + struct combphy_reg pipe_rate_sel; + struct combphy_reg pipe_rxterm_sel; + struct combphy_reg pipe_txelec_sel; + struct combphy_reg pipe_txcomp_sel; + struct combphy_reg pipe_clk_ext; + struct combphy_reg pipe_sel_usb; + struct combphy_reg pipe_sel_qsgmii; + struct combphy_reg pipe_phy_status; + struct combphy_reg con0_for_pcie; + struct combphy_reg con1_for_pcie; + struct combphy_reg con2_for_pcie; + struct combphy_reg con3_for_pcie; + struct combphy_reg con0_for_sata; + struct combphy_reg con1_for_sata; + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; +}; + +struct rockchip_combphy_cfg { + const struct rockchip_combphy_grfcfg *grfcfg; + int (*combphy_cfg)(struct rockchip_combphy_priv *priv); +}; + +struct rockchip_combphy_priv { + u8 mode; + void __iomem *mmio; + int num_clks; + struct clk_bulk_data *clks; + struct device *dev; + struct regmap *pipe_grf; + struct regmap *phy_grf; + struct phy *phy; + struct reset_control *phy_rst; + const struct rockchip_combphy_cfg *cfg; + bool enable_ssc; + bool ext_refclk; + struct clk *refclk; +}; + +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, + int mask, int val, int reg) +{ + unsigned int temp; + + temp = readl(priv->mmio + reg); + temp = (temp & ~(mask)) | val; + writel(temp, priv->mmio + reg); +} + +static int rockchip_combphy_param_write(struct regmap *base, + const struct combphy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 mask, val; + + mask = GENMASK(cfg->pipe_phy_status.bitend, + cfg->pipe_phy_status.bitstart); + + regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); + val = (val & mask) >> cfg->pipe_phy_status.bitstart; + + return val; +} + +static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + case PHY_TYPE_USB3: + case PHY_TYPE_SATA: + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + if (priv->cfg->combphy_cfg) + ret = priv->cfg->combphy_cfg(priv); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + if (ret) + dev_err(priv->dev, "failed to init phy for phy mode %x\n", priv->mode); + + return ret; +} + +static int rockchip_combphy_init(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(priv->dev, "failed to enable clks\n"); + return ret; + } + + ret = rockchip_combphy_set_mode(priv); + if (ret) + goto err_clk; + + ret = reset_control_deassert(priv->phy_rst); + if (ret) + goto err_clk; + + if (priv->mode == PHY_TYPE_USB3) { + ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, + priv, val, + val == cfg->pipe_phy_status.enable, + 10, 1000); + if (ret) + dev_warn(priv->dev, "wait phy status ready timeout\n"); + } + + return 0; + +err_clk: + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + + return ret; +} + +static int rockchip_combphy_exit(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->phy_rst); + + return 0; +} + +static const struct phy_ops rochchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, + .owner = THIS_MODULE, +}; + +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) +{ + struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->mode != PHY_NONE && priv->mode != args->args[0]) + dev_warn(dev, "phy type select %d overwriting type %d\n", + args->args[0], priv->mode); + + priv->mode = args->args[0]; + + return priv->phy; +} + +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; + int mac_id; + int i; + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -EINVAL; + + priv->refclk = NULL; + for (i = 0; i < priv->num_clks; i++) { + if (!strncmp(priv->clks[i].id, "ref", 3)) { + priv->refclk = priv->clks[i].clk; + break; + } + } + + if (!priv->refclk) { + dev_err(dev, "no refclk found\n"); + return -EINVAL; + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + if (device_property_present(dev, "rockchip,dis-u3otg0-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, + false); + + if (device_property_present(dev, "rockchip,dis-u3otg1-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, + false); + + priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); + + priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); + + if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) && + (mac_id > 0)) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + true); + else + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + false); + + priv->phy_rst = devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); + + return 0; +} + +static int rockchip_combphy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_combphy_priv *priv; + const struct rockchip_combphy_cfg *phy_cfg; + struct resource *res; + int ret; + + phy_cfg = of_device_get_match_data(dev); + if (!phy_cfg) { + dev_err(dev, "no OF match data provided\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->dev = dev; + priv->mode = PHY_NONE; + priv->cfg = phy_cfg; + + ret = rockchip_combphy_parse_dt(dev, priv); + if (ret) + return ret; + + ret = reset_control_assert(priv->phy_rst); + if (ret) { + dev_err(dev, "failed to reset phy\n"); + return ret; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + /* Enable adaptive CTLE for USB3.0 Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + + /* Set PLL KVCO fine tuning signals. */ + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT, + RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + /* Set PLL input clock divider 1/2. */ + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT, + RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ + val = T22_PHYREG6_TX_RTERM_50OHM << T22_PHYREG6_TX_RTERM_SHIFT; + val |= T22_PHYREG6_RX_RTERM_44OHM << T22_PHYREG6_RX_RTERM_SHIFT; + writel(val, priv->mmio + RK3568_T22_PHYREG6); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + break; + + case PHY_TYPE_SGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); + break; + + case PHY_TYPE_QSGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); + break; + + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ + val = T22_PHYREG14_SSC_CNT_VALUE << T22_PHYREG14_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG14_SSC_CNT_MASK, + val, RK3568_T22_PHYREG14); + + writel(T22_PHYREG15_SSC_CNT_VALUE, priv->mmio + RK3568_T22_PHYREG15); + } + break; + + case REF_CLOCK_25MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ + val = T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + val, RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + val = T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + val, RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT; + val |= T22_PHYREG31_SSC_OFFSET_500PPM << T22_PHYREG31_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, val, RK3568_T22_PHYREG31); + writel(val, priv->mmio + RK3568_T22_PHYREG31); + } + break; + + default: + dev_err(priv->dev, "unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { + val = T22_PHYREG12_RESISTER_HIGH_Z << T22_PHYREG12_RESISTER_SHIFT; + val |= T22_PHYREG12_CKRCV_AMP0; + rockchip_combphy_updatel(priv, T22_PHYREG12_RESISTER_MASK, val, RK3568_T22_PHYREG12); + + val = readl(priv->mmio + RK3568_T22_PHYREG13); + val |= T22_PHYREG13_CKRCV_AMP1; + writel(val, priv->mmio + RK3568_T22_PHYREG13); + } + } + + if (priv->enable_ssc) { + val = readl(priv->mmio + RK3568_T22_PHYREG7); + val |= T22_PHYREG7_SSC_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG7); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, + .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .grfcfg = &rk3568_combphy_grfcfgs, + .combphy_cfg = rk3568_combphy_cfg, +}; + +static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); + +static struct platform_driver rockchip_combphy_driver = { + .probe = rockchip_combphy_probe, + .driver = { + .name = "rockchip-naneng-combphy", + .of_match_table = rockchip_combphy_of_match, + }, +}; +module_platform_driver(rockchip_combphy_driver); + +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This patch implements a combo phy driver for Rockchip SoCs with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. Changes in v2: - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 3 files changed, 627 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index e812adad7242..9022e395c056 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY Enable this to support the Rockchip MIPI/LVDS/TTL PHY with Innosilicon IP block. +config PHY_ROCKCHIP_NANENG_COMBO_PHY + tristate "Rockchip NANENG COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII + combo PHY with NaNeng IP block. + config PHY_ROCKCHIP_PCIE tristate "Rockchip PCIe PHY Driver" depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index f0eec212b2aa..a5041efb5b8f 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c new file mode 100644 index 000000000000..4fa150dbe7eb --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PIPE USB3.0 PCIE SATA combphy driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <dt-bindings/phy/phy.h> + +#define BIT_WRITEABLE_SHIFT 16 +#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) +#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) +#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) + +/* RK3568 T22 COMBO PHY REG */ +#define RK3568_T22_PHYREG5 0x14 +#define T22_PHYREG5_PLL_DIV_MASK GENMASK(7, 6) +#define T22_PHYREG5_PLL_DIV_SHIFT 6 +#define T22_PHYREG5_PLL_DIV_2 1 + +#define RK3568_T22_PHYREG6 0x18 +#define T22_PHYREG6_TX_RTERM_MASK GENMASK(7, 4) +#define T22_PHYREG6_TX_RTERM_SHIFT 4 +#define T22_PHYREG6_TX_RTERM_50OHM 8 +#define T22_PHYREG6_RX_RTERM_MASK GENMASK(3, 0) +#define T22_PHYREG6_RX_RTERM_SHIFT 0 +#define T22_PHYREG6_RX_RTERM_44OHM 15 + +#define RK3568_T22_PHYREG7 0x1C +#define T22_PHYREG7_SSC_EN BIT(4) + +#define RK3568_T22_PHYREG10 0x28 +#define T22_PHYREG10_SU_TRIM_0_7 0xF0 + +#define RK3568_T22_PHYREG11 0x2C +#define T22_PHYREG11_PLL_LPF_ADJ_VALUE 4 + +#define RK3568_T22_PHYREG12 0x30 +#define T22_PHYREG12_RESISTER_MASK GENMASK(5, 4) +#define T22_PHYREG12_RESISTER_SHIFT 0x4 +#define T22_PHYREG12_RESISTER_HIGH_Z 3 +#define T22_PHYREG12_CKRCV_AMP0 BIT(7) + +#define RK3568_T22_PHYREG13 0x34 +#define T22_PHYREG13_CKRCV_AMP1 BIT(0) + +#define RK3568_T22_PHYREG14 0x38 +#define T22_PHYREG14_CTLE_EN BIT(0) +#define T22_PHYREG14_SSC_CNT_MASK GENMASK(7, 6) +#define T22_PHYREG14_SSC_CNT_SHIFT 6 +#define T22_PHYREG14_SSC_CNT_VALUE 1 + +#define RK3568_T22_PHYREG15 0x3C +#define T22_PHYREG15_SSC_CNT_VALUE 0x5f + +#define RK3568_T22_PHYREG17 0x44 +#define T22_PHYREG17_PLL_LOOP 0x32 + +#define RK3568_T22_PHYREG31 0x7C +#define T22_PHYREG31_SSC_MASK GENMASK(7, 4) +#define T22_PHYREG31_SSC_DIR_SHIFT 4 +#define T22_PHYREG31_SSC_UPWARD 0 +#define T22_PHYREG31_SSC_DOWNWARD 1 +#define T22_PHYREG31_SSC_OFFSET_SHIFT 6 +#define T22_PHYREG31_SSC_OFFSET_500PPM 1 + +#define RK3568_T22_PHYREG32 0x80 +#define T22_PHYREG32_PLL_KVCO_MASK GENMASK(4, 2) +#define T22_PHYREG32_PLL_KVCO_SHIFT 2 +#define T22_PHYREG32_PLL_KVCO_VALUE 2 + +struct rockchip_combphy_priv; + +struct combphy_reg { + u16 offset; + u16 bitend; + u16 bitstart; + u16 disable; + u16 enable; +}; + +struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; + struct combphy_reg pipe_rate_sel; + struct combphy_reg pipe_rxterm_sel; + struct combphy_reg pipe_txelec_sel; + struct combphy_reg pipe_txcomp_sel; + struct combphy_reg pipe_clk_ext; + struct combphy_reg pipe_sel_usb; + struct combphy_reg pipe_sel_qsgmii; + struct combphy_reg pipe_phy_status; + struct combphy_reg con0_for_pcie; + struct combphy_reg con1_for_pcie; + struct combphy_reg con2_for_pcie; + struct combphy_reg con3_for_pcie; + struct combphy_reg con0_for_sata; + struct combphy_reg con1_for_sata; + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; +}; + +struct rockchip_combphy_cfg { + const struct rockchip_combphy_grfcfg *grfcfg; + int (*combphy_cfg)(struct rockchip_combphy_priv *priv); +}; + +struct rockchip_combphy_priv { + u8 mode; + void __iomem *mmio; + int num_clks; + struct clk_bulk_data *clks; + struct device *dev; + struct regmap *pipe_grf; + struct regmap *phy_grf; + struct phy *phy; + struct reset_control *phy_rst; + const struct rockchip_combphy_cfg *cfg; + bool enable_ssc; + bool ext_refclk; + struct clk *refclk; +}; + +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, + int mask, int val, int reg) +{ + unsigned int temp; + + temp = readl(priv->mmio + reg); + temp = (temp & ~(mask)) | val; + writel(temp, priv->mmio + reg); +} + +static int rockchip_combphy_param_write(struct regmap *base, + const struct combphy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 mask, val; + + mask = GENMASK(cfg->pipe_phy_status.bitend, + cfg->pipe_phy_status.bitstart); + + regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); + val = (val & mask) >> cfg->pipe_phy_status.bitstart; + + return val; +} + +static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + case PHY_TYPE_USB3: + case PHY_TYPE_SATA: + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + if (priv->cfg->combphy_cfg) + ret = priv->cfg->combphy_cfg(priv); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + if (ret) + dev_err(priv->dev, "failed to init phy for phy mode %x\n", priv->mode); + + return ret; +} + +static int rockchip_combphy_init(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(priv->dev, "failed to enable clks\n"); + return ret; + } + + ret = rockchip_combphy_set_mode(priv); + if (ret) + goto err_clk; + + ret = reset_control_deassert(priv->phy_rst); + if (ret) + goto err_clk; + + if (priv->mode == PHY_TYPE_USB3) { + ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, + priv, val, + val == cfg->pipe_phy_status.enable, + 10, 1000); + if (ret) + dev_warn(priv->dev, "wait phy status ready timeout\n"); + } + + return 0; + +err_clk: + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + + return ret; +} + +static int rockchip_combphy_exit(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->phy_rst); + + return 0; +} + +static const struct phy_ops rochchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, + .owner = THIS_MODULE, +}; + +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) +{ + struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->mode != PHY_NONE && priv->mode != args->args[0]) + dev_warn(dev, "phy type select %d overwriting type %d\n", + args->args[0], priv->mode); + + priv->mode = args->args[0]; + + return priv->phy; +} + +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; + int mac_id; + int i; + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -EINVAL; + + priv->refclk = NULL; + for (i = 0; i < priv->num_clks; i++) { + if (!strncmp(priv->clks[i].id, "ref", 3)) { + priv->refclk = priv->clks[i].clk; + break; + } + } + + if (!priv->refclk) { + dev_err(dev, "no refclk found\n"); + return -EINVAL; + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + if (device_property_present(dev, "rockchip,dis-u3otg0-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, + false); + + if (device_property_present(dev, "rockchip,dis-u3otg1-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, + false); + + priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); + + priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); + + if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) && + (mac_id > 0)) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + true); + else + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + false); + + priv->phy_rst = devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); + + return 0; +} + +static int rockchip_combphy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_combphy_priv *priv; + const struct rockchip_combphy_cfg *phy_cfg; + struct resource *res; + int ret; + + phy_cfg = of_device_get_match_data(dev); + if (!phy_cfg) { + dev_err(dev, "no OF match data provided\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->dev = dev; + priv->mode = PHY_NONE; + priv->cfg = phy_cfg; + + ret = rockchip_combphy_parse_dt(dev, priv); + if (ret) + return ret; + + ret = reset_control_assert(priv->phy_rst); + if (ret) { + dev_err(dev, "failed to reset phy\n"); + return ret; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + /* Enable adaptive CTLE for USB3.0 Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + + /* Set PLL KVCO fine tuning signals. */ + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT, + RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + /* Set PLL input clock divider 1/2. */ + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT, + RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ + val = T22_PHYREG6_TX_RTERM_50OHM << T22_PHYREG6_TX_RTERM_SHIFT; + val |= T22_PHYREG6_RX_RTERM_44OHM << T22_PHYREG6_RX_RTERM_SHIFT; + writel(val, priv->mmio + RK3568_T22_PHYREG6); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + break; + + case PHY_TYPE_SGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); + break; + + case PHY_TYPE_QSGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); + break; + + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ + val = T22_PHYREG14_SSC_CNT_VALUE << T22_PHYREG14_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG14_SSC_CNT_MASK, + val, RK3568_T22_PHYREG14); + + writel(T22_PHYREG15_SSC_CNT_VALUE, priv->mmio + RK3568_T22_PHYREG15); + } + break; + + case REF_CLOCK_25MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ + val = T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + val, RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + val = T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + val, RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT; + val |= T22_PHYREG31_SSC_OFFSET_500PPM << T22_PHYREG31_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, val, RK3568_T22_PHYREG31); + writel(val, priv->mmio + RK3568_T22_PHYREG31); + } + break; + + default: + dev_err(priv->dev, "unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { + val = T22_PHYREG12_RESISTER_HIGH_Z << T22_PHYREG12_RESISTER_SHIFT; + val |= T22_PHYREG12_CKRCV_AMP0; + rockchip_combphy_updatel(priv, T22_PHYREG12_RESISTER_MASK, val, RK3568_T22_PHYREG12); + + val = readl(priv->mmio + RK3568_T22_PHYREG13); + val |= T22_PHYREG13_CKRCV_AMP1; + writel(val, priv->mmio + RK3568_T22_PHYREG13); + } + } + + if (priv->enable_ssc) { + val = readl(priv->mmio + RK3568_T22_PHYREG7); + val |= T22_PHYREG7_SSC_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG7); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, + .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .grfcfg = &rk3568_combphy_grfcfgs, + .combphy_cfg = rk3568_combphy_cfg, +}; + +static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); + +static struct platform_driver rockchip_combphy_driver = { + .probe = rockchip_combphy_probe, + .driver = { + .name = "rockchip-naneng-combphy", + .of_match_table = rockchip_combphy_of_match, + }, +}; +module_platform_driver(rockchip_combphy_driver); + +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao This patch implements a combo phy driver for Rockchip SoCs with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. Changes in v2: - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++ 3 files changed, 627 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index e812adad7242..9022e395c056 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY Enable this to support the Rockchip MIPI/LVDS/TTL PHY with Innosilicon IP block. +config PHY_ROCKCHIP_NANENG_COMBO_PHY + tristate "Rockchip NANENG COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII + combo PHY with NaNeng IP block. + config PHY_ROCKCHIP_PCIE tristate "Rockchip PCIe PHY Driver" depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index f0eec212b2aa..a5041efb5b8f 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c new file mode 100644 index 000000000000..4fa150dbe7eb --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PIPE USB3.0 PCIE SATA combphy driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <dt-bindings/phy/phy.h> + +#define BIT_WRITEABLE_SHIFT 16 +#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) +#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) +#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) + +/* RK3568 T22 COMBO PHY REG */ +#define RK3568_T22_PHYREG5 0x14 +#define T22_PHYREG5_PLL_DIV_MASK GENMASK(7, 6) +#define T22_PHYREG5_PLL_DIV_SHIFT 6 +#define T22_PHYREG5_PLL_DIV_2 1 + +#define RK3568_T22_PHYREG6 0x18 +#define T22_PHYREG6_TX_RTERM_MASK GENMASK(7, 4) +#define T22_PHYREG6_TX_RTERM_SHIFT 4 +#define T22_PHYREG6_TX_RTERM_50OHM 8 +#define T22_PHYREG6_RX_RTERM_MASK GENMASK(3, 0) +#define T22_PHYREG6_RX_RTERM_SHIFT 0 +#define T22_PHYREG6_RX_RTERM_44OHM 15 + +#define RK3568_T22_PHYREG7 0x1C +#define T22_PHYREG7_SSC_EN BIT(4) + +#define RK3568_T22_PHYREG10 0x28 +#define T22_PHYREG10_SU_TRIM_0_7 0xF0 + +#define RK3568_T22_PHYREG11 0x2C +#define T22_PHYREG11_PLL_LPF_ADJ_VALUE 4 + +#define RK3568_T22_PHYREG12 0x30 +#define T22_PHYREG12_RESISTER_MASK GENMASK(5, 4) +#define T22_PHYREG12_RESISTER_SHIFT 0x4 +#define T22_PHYREG12_RESISTER_HIGH_Z 3 +#define T22_PHYREG12_CKRCV_AMP0 BIT(7) + +#define RK3568_T22_PHYREG13 0x34 +#define T22_PHYREG13_CKRCV_AMP1 BIT(0) + +#define RK3568_T22_PHYREG14 0x38 +#define T22_PHYREG14_CTLE_EN BIT(0) +#define T22_PHYREG14_SSC_CNT_MASK GENMASK(7, 6) +#define T22_PHYREG14_SSC_CNT_SHIFT 6 +#define T22_PHYREG14_SSC_CNT_VALUE 1 + +#define RK3568_T22_PHYREG15 0x3C +#define T22_PHYREG15_SSC_CNT_VALUE 0x5f + +#define RK3568_T22_PHYREG17 0x44 +#define T22_PHYREG17_PLL_LOOP 0x32 + +#define RK3568_T22_PHYREG31 0x7C +#define T22_PHYREG31_SSC_MASK GENMASK(7, 4) +#define T22_PHYREG31_SSC_DIR_SHIFT 4 +#define T22_PHYREG31_SSC_UPWARD 0 +#define T22_PHYREG31_SSC_DOWNWARD 1 +#define T22_PHYREG31_SSC_OFFSET_SHIFT 6 +#define T22_PHYREG31_SSC_OFFSET_500PPM 1 + +#define RK3568_T22_PHYREG32 0x80 +#define T22_PHYREG32_PLL_KVCO_MASK GENMASK(4, 2) +#define T22_PHYREG32_PLL_KVCO_SHIFT 2 +#define T22_PHYREG32_PLL_KVCO_VALUE 2 + +struct rockchip_combphy_priv; + +struct combphy_reg { + u16 offset; + u16 bitend; + u16 bitstart; + u16 disable; + u16 enable; +}; + +struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; + struct combphy_reg pipe_rate_sel; + struct combphy_reg pipe_rxterm_sel; + struct combphy_reg pipe_txelec_sel; + struct combphy_reg pipe_txcomp_sel; + struct combphy_reg pipe_clk_ext; + struct combphy_reg pipe_sel_usb; + struct combphy_reg pipe_sel_qsgmii; + struct combphy_reg pipe_phy_status; + struct combphy_reg con0_for_pcie; + struct combphy_reg con1_for_pcie; + struct combphy_reg con2_for_pcie; + struct combphy_reg con3_for_pcie; + struct combphy_reg con0_for_sata; + struct combphy_reg con1_for_sata; + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; +}; + +struct rockchip_combphy_cfg { + const struct rockchip_combphy_grfcfg *grfcfg; + int (*combphy_cfg)(struct rockchip_combphy_priv *priv); +}; + +struct rockchip_combphy_priv { + u8 mode; + void __iomem *mmio; + int num_clks; + struct clk_bulk_data *clks; + struct device *dev; + struct regmap *pipe_grf; + struct regmap *phy_grf; + struct phy *phy; + struct reset_control *phy_rst; + const struct rockchip_combphy_cfg *cfg; + bool enable_ssc; + bool ext_refclk; + struct clk *refclk; +}; + +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, + int mask, int val, int reg) +{ + unsigned int temp; + + temp = readl(priv->mmio + reg); + temp = (temp & ~(mask)) | val; + writel(temp, priv->mmio + reg); +} + +static int rockchip_combphy_param_write(struct regmap *base, + const struct combphy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 mask, val; + + mask = GENMASK(cfg->pipe_phy_status.bitend, + cfg->pipe_phy_status.bitstart); + + regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); + val = (val & mask) >> cfg->pipe_phy_status.bitstart; + + return val; +} + +static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + case PHY_TYPE_USB3: + case PHY_TYPE_SATA: + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + if (priv->cfg->combphy_cfg) + ret = priv->cfg->combphy_cfg(priv); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + if (ret) + dev_err(priv->dev, "failed to init phy for phy mode %x\n", priv->mode); + + return ret; +} + +static int rockchip_combphy_init(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(priv->dev, "failed to enable clks\n"); + return ret; + } + + ret = rockchip_combphy_set_mode(priv); + if (ret) + goto err_clk; + + ret = reset_control_deassert(priv->phy_rst); + if (ret) + goto err_clk; + + if (priv->mode == PHY_TYPE_USB3) { + ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, + priv, val, + val == cfg->pipe_phy_status.enable, + 10, 1000); + if (ret) + dev_warn(priv->dev, "wait phy status ready timeout\n"); + } + + return 0; + +err_clk: + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + + return ret; +} + +static int rockchip_combphy_exit(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->phy_rst); + + return 0; +} + +static const struct phy_ops rochchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, + .owner = THIS_MODULE, +}; + +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) +{ + struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->mode != PHY_NONE && priv->mode != args->args[0]) + dev_warn(dev, "phy type select %d overwriting type %d\n", + args->args[0], priv->mode); + + priv->mode = args->args[0]; + + return priv->phy; +} + +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; + int mac_id; + int i; + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -EINVAL; + + priv->refclk = NULL; + for (i = 0; i < priv->num_clks; i++) { + if (!strncmp(priv->clks[i].id, "ref", 3)) { + priv->refclk = priv->clks[i].clk; + break; + } + } + + if (!priv->refclk) { + dev_err(dev, "no refclk found\n"); + return -EINVAL; + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + if (device_property_present(dev, "rockchip,dis-u3otg0-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, + false); + + if (device_property_present(dev, "rockchip,dis-u3otg1-port")) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, + false); + + priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); + + priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); + + if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) && + (mac_id > 0)) + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + true); + else + rockchip_combphy_param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + false); + + priv->phy_rst = devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); + + return 0; +} + +static int rockchip_combphy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_combphy_priv *priv; + const struct rockchip_combphy_cfg *phy_cfg; + struct resource *res; + int ret; + + phy_cfg = of_device_get_match_data(dev); + if (!phy_cfg) { + dev_err(dev, "no OF match data provided\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->dev = dev; + priv->mode = PHY_NONE; + priv->cfg = phy_cfg; + + ret = rockchip_combphy_parse_dt(dev, priv); + if (ret) + return ret; + + ret = reset_control_assert(priv->phy_rst); + if (ret) { + dev_err(dev, "failed to reset phy\n"); + return ret; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum. */ + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, + T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT, + RK3568_T22_PHYREG31); + + /* Enable adaptive CTLE for USB3.0 Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + + /* Set PLL KVCO fine tuning signals. */ + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT, + RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + /* Set PLL input clock divider 1/2. */ + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT, + RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ + val = readl(priv->mmio + RK3568_T22_PHYREG14); + val |= T22_PHYREG14_CTLE_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG14); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ + val = T22_PHYREG6_TX_RTERM_50OHM << T22_PHYREG6_TX_RTERM_SHIFT; + val |= T22_PHYREG6_RX_RTERM_44OHM << T22_PHYREG6_RX_RTERM_SHIFT; + writel(val, priv->mmio + RK3568_T22_PHYREG6); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + break; + + case PHY_TYPE_SGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); + break; + + case PHY_TYPE_QSGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); + break; + + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ + val = T22_PHYREG14_SSC_CNT_VALUE << T22_PHYREG14_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG14_SSC_CNT_MASK, + val, RK3568_T22_PHYREG14); + + writel(T22_PHYREG15_SSC_CNT_VALUE, priv->mmio + RK3568_T22_PHYREG15); + } + break; + + case REF_CLOCK_25MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ + val = T22_PHYREG32_PLL_KVCO_VALUE << T22_PHYREG32_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG32_PLL_KVCO_MASK, + val, RK3568_T22_PHYREG32); + + /* Enable controlling random jitter. */ + writel(T22_PHYREG11_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_T22_PHYREG11); + + val = T22_PHYREG5_PLL_DIV_2 << T22_PHYREG5_PLL_DIV_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG5_PLL_DIV_MASK, + val, RK3568_T22_PHYREG5); + + writel(T22_PHYREG17_PLL_LOOP, priv->mmio + RK3568_T22_PHYREG17); + writel(T22_PHYREG10_SU_TRIM_0_7, priv->mmio + RK3568_T22_PHYREG10); + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = T22_PHYREG31_SSC_DOWNWARD << T22_PHYREG31_SSC_DIR_SHIFT; + val |= T22_PHYREG31_SSC_OFFSET_500PPM << T22_PHYREG31_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, T22_PHYREG31_SSC_MASK, val, RK3568_T22_PHYREG31); + writel(val, priv->mmio + RK3568_T22_PHYREG31); + } + break; + + default: + dev_err(priv->dev, "unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { + val = T22_PHYREG12_RESISTER_HIGH_Z << T22_PHYREG12_RESISTER_SHIFT; + val |= T22_PHYREG12_CKRCV_AMP0; + rockchip_combphy_updatel(priv, T22_PHYREG12_RESISTER_MASK, val, RK3568_T22_PHYREG12); + + val = readl(priv->mmio + RK3568_T22_PHYREG13); + val |= T22_PHYREG13_CKRCV_AMP1; + writel(val, priv->mmio + RK3568_T22_PHYREG13); + } + } + + if (priv->enable_ssc) { + val = readl(priv->mmio + RK3568_T22_PHYREG7); + val |= T22_PHYREG7_SSC_EN; + writel(val, priv->mmio + RK3568_T22_PHYREG7); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, + .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .grfcfg = &rk3568_combphy_grfcfgs, + .combphy_cfg = rk3568_combphy_cfg, +}; + +static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); + +static struct platform_driver rockchip_combphy_driver = { + .probe = rockchip_combphy_probe, + .driver = { + .name = "rockchip-naneng-combphy", + .of_match_table = rockchip_combphy_of_match, + }, +}; +module_platform_driver(rockchip_combphy_driver); + +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 2021-12-15 9:56 ` Yifeng Zhao ` (2 preceding siblings ...) (?) @ 2021-12-15 22:47 ` kernel test robot -1 siblings, 0 replies; 34+ messages in thread From: kernel test robot @ 2021-12-15 22:47 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: kbuild-all, robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy Hi Yifeng, Thank you for the patch! Yet something to improve: [auto build test ERROR on rockchip/for-next] [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c 20 21 #define BIT_WRITEABLE_SHIFT 16 > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 25 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-15 22:47 ` kernel test robot 0 siblings, 0 replies; 34+ messages in thread From: kernel test robot @ 2021-12-15 22:47 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 3058 bytes --] Hi Yifeng, Thank you for the patch! Yet something to improve: [auto build test ERROR on rockchip/for-next] [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp(a)intel.com/config) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c 20 21 #define BIT_WRITEABLE_SHIFT 16 > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 25 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-15 22:47 ` kernel test robot 0 siblings, 0 replies; 34+ messages in thread From: kernel test robot @ 2021-12-15 22:47 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: kbuild-all, robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy Hi Yifeng, Thank you for the patch! Yet something to improve: [auto build test ERROR on rockchip/for-next] [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c 20 21 #define BIT_WRITEABLE_SHIFT 16 > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 25 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-15 22:47 ` kernel test robot 0 siblings, 0 replies; 34+ messages in thread From: kernel test robot @ 2021-12-15 22:47 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: kbuild-all, robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy Hi Yifeng, Thank you for the patch! Yet something to improve: [auto build test ERROR on rockchip/for-next] [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c 20 21 #define BIT_WRITEABLE_SHIFT 16 > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 25 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-15 22:47 ` kernel test robot 0 siblings, 0 replies; 34+ messages in thread From: kernel test robot @ 2021-12-15 22:47 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: kbuild-all, robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy Hi Yifeng, Thank you for the patch! Yet something to improve: [auto build test ERROR on rockchip/for-next] [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) | ^~~~~~~~~~ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' 490 | case REF_CLOCK_24MHz: | ^~~~~~~~~~~~~~~ vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c 20 21 #define BIT_WRITEABLE_SHIFT 16 > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 25 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 2021-12-15 22:47 ` kernel test robot ` (2 preceding siblings ...) (?) @ 2021-12-23 11:19 ` Vinod Koul -1 siblings, 0 replies; 34+ messages in thread From: Vinod Koul @ 2021-12-23 11:19 UTC (permalink / raw) To: kernel test robot Cc: Yifeng Zhao, heiko, kbuild-all, robh+dt, jbx6244, devicetree, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy On 16-12-21, 06:47, kernel test robot wrote: > Hi Yifeng, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on rockchip/for-next] > [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch] > > url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next > config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) > compiler: aarch64-linux-gcc (GCC) 11.2.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 > git remote add linux-review https://github.com/0day-ci/linux > git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 > # save the config file to linux build tree > mkdir build_dir > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > > All errors (new ones prefixed by >>): > > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': > >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ You need to add the header to your driver for this > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > > > vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > > 20 > 21 #define BIT_WRITEABLE_SHIFT 16 > > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) > 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) > 25 > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org -- ~Vinod ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-23 11:19 ` Vinod Koul 0 siblings, 0 replies; 34+ messages in thread From: Vinod Koul @ 2021-12-23 11:19 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 3289 bytes --] On 16-12-21, 06:47, kernel test robot wrote: > Hi Yifeng, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on rockchip/for-next] > [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch] > > url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next > config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp(a)intel.com/config) > compiler: aarch64-linux-gcc (GCC) 11.2.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 > git remote add linux-review https://github.com/0day-ci/linux > git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 > # save the config file to linux build tree > mkdir build_dir > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > > All errors (new ones prefixed by >>): > > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': > >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ You need to add the header to your driver for this > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > > > vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > > 20 > 21 #define BIT_WRITEABLE_SHIFT 16 > > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) > 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) > 25 > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org -- ~Vinod ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-23 11:19 ` Vinod Koul 0 siblings, 0 replies; 34+ messages in thread From: Vinod Koul @ 2021-12-23 11:19 UTC (permalink / raw) To: kernel test robot Cc: Yifeng Zhao, heiko, kbuild-all, robh+dt, jbx6244, devicetree, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy On 16-12-21, 06:47, kernel test robot wrote: > Hi Yifeng, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on rockchip/for-next] > [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch] > > url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next > config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) > compiler: aarch64-linux-gcc (GCC) 11.2.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 > git remote add linux-review https://github.com/0day-ci/linux > git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 > # save the config file to linux build tree > mkdir build_dir > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > > All errors (new ones prefixed by >>): > > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': > >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ You need to add the header to your driver for this > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > > > vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > > 20 > 21 #define BIT_WRITEABLE_SHIFT 16 > > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) > 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) > 25 > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org -- ~Vinod _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-23 11:19 ` Vinod Koul 0 siblings, 0 replies; 34+ messages in thread From: Vinod Koul @ 2021-12-23 11:19 UTC (permalink / raw) To: kernel test robot Cc: Yifeng Zhao, heiko, kbuild-all, robh+dt, jbx6244, devicetree, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy On 16-12-21, 06:47, kernel test robot wrote: > Hi Yifeng, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on rockchip/for-next] > [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch] > > url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next > config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) > compiler: aarch64-linux-gcc (GCC) 11.2.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 > git remote add linux-review https://github.com/0day-ci/linux > git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 > # save the config file to linux build tree > mkdir build_dir > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > > All errors (new ones prefixed by >>): > > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': > >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ You need to add the header to your driver for this > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > > > vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > > 20 > 21 #define BIT_WRITEABLE_SHIFT 16 > > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) > 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) > 25 > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org -- ~Vinod -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 @ 2021-12-23 11:19 ` Vinod Koul 0 siblings, 0 replies; 34+ messages in thread From: Vinod Koul @ 2021-12-23 11:19 UTC (permalink / raw) To: kernel test robot Cc: Yifeng Zhao, heiko, kbuild-all, robh+dt, jbx6244, devicetree, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy On 16-12-21, 06:47, kernel test robot wrote: > Hi Yifeng, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on rockchip/for-next] > [also build test ERROR on robh/for-next lee-mfd/for-mfd-next v5.16-rc5 next-20211214] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch] > > url: https://github.com/0day-ci/linux/commits/Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next > config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211216/202112160605.2BqI0hlK-lkp@intel.com/config) > compiler: aarch64-linux-gcc (GCC) 11.2.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/0day-ci/linux/commit/5e4ddb08d86d5232174d88483f29e96272a4b6c0 > git remote add linux-review https://github.com/0day-ci/linux > git fetch --no-tags linux-review Yifeng-Zhao/Add-Naneng-combo-PHY-support-for-RK3568/20211215-180610 > git checkout 5e4ddb08d86d5232174d88483f29e96272a4b6c0 > # save the config file to linux build tree > mkdir build_dir > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > > All errors (new ones prefixed by >>): > > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c: In function 'rk3568_combphy_cfg': > >> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: error: 'HZ_PER_MHZ' undeclared (first use in this function) > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ You need to add the header to your driver for this > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:22:47: note: each undeclared identifier is reported only once for each function it appears in > 22 | #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > | ^~~~~~~~~~ > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c:490:14: note: in expansion of macro 'REF_CLOCK_24MHz' > 490 | case REF_CLOCK_24MHz: > | ^~~~~~~~~~~~~~~ > > > vim +/HZ_PER_MHZ +22 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > > 20 > 21 #define BIT_WRITEABLE_SHIFT 16 > > 22 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) > 23 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) > 24 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) > 25 > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org -- ~Vinod _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 2021-12-15 9:56 ` Yifeng Zhao (?) (?) @ 2021-12-15 9:56 ` Yifeng Zhao -1 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - remove apb reset Changes in v4: - rename node name - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Move phy0 to rk3568.dtsi arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2fd313a295f8..91a0b798b857 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -71,6 +76,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index a68033a23975..93f230f799f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -218,11 +218,26 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -1141,6 +1156,38 @@ status = "disabled"; }; + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - remove apb reset Changes in v4: - rename node name - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Move phy0 to rk3568.dtsi arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2fd313a295f8..91a0b798b857 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -71,6 +76,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index a68033a23975..93f230f799f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -218,11 +218,26 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -1141,6 +1156,38 @@ status = "disabled"; }; + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - remove apb reset Changes in v4: - rename node name - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Move phy0 to rk3568.dtsi arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2fd313a295f8..91a0b798b857 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -71,6 +76,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index a68033a23975..93f230f799f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -218,11 +218,26 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -1141,6 +1156,38 @@ status = "disabled"; }; + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 @ 2021-12-15 9:56 ` Yifeng Zhao 0 siblings, 0 replies; 34+ messages in thread From: Yifeng Zhao @ 2021-12-15 9:56 UTC (permalink / raw) To: heiko Cc: robh+dt, jbx6244, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang, Yifeng Zhao Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Changes in v5: - remove apb reset Changes in v4: - rename node name - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Move phy0 to rk3568.dtsi arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2fd313a295f8..91a0b798b857 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -71,6 +76,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index a68033a23975..93f230f799f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -218,11 +218,26 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -1141,6 +1156,38 @@ status = "disabled"; }; + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; -- 2.17.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 2021-12-15 9:56 ` Yifeng Zhao (?) (?) @ 2021-12-16 12:19 ` Johan Jonker -1 siblings, 0 replies; 34+ messages in thread From: Johan Jonker @ 2021-12-16 12:19 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: robh+dt, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang Hi Heiko, Yifeng, Could you advise whether we should change the DT layout and driver a bit. Some properties don't really fit to one particular phy node, so move them to a parent node. Maybe replace rockchip,sgmii-mac-sel by a node in phy 1 and 2 ?? Also there are two USB3.0 Controllers, one can use as USB3.0 OTG Controller, another one can use as USB3.0 Host Controller only. Yet properties are called: rockchip,dis-u3otg0-port, rockchip,dis-u3otg1-port. Maybe replace them by a node ?? Unknown capabilities of future (rk3588) Naneng versions (combined host and otg ??) Maybe follow more in line with the phy-rockchip-inno-usb2.c and phy-rockchip-usb.c drivers. Could you confirm combo PHY on the RK3566 lacks the QSGMII/SGMII stuff? (Lack of rk3566 TRM) With so many differences maybe use separate compatible string and keep the DT nodes completely apart. (rockchip,rk3566-naneng-combphy, rockchip,rk3568-naneng-combphy) Johan ================================ combphy: combphy { compatible = "rockchip,rk3568-naneng-combphy"; ======== rockchip,ext-refclk; rockchip,enable-ssc; rockchip,pipe-grf = <&pipegrf>; ======== #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; combphy0: combi-phy@fe820000 { reg = <0x0 0xfe820000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY0>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; #phy-cells = <1>; status = "disabled"; u3phy0_otg: otg-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === }; }; combphy1: combi-phy@fe830000 { reg = <0x0 0xfe830000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY1>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; #phy-cells = <1>; status = "disabled"; u3phy0_host: host-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === } sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; combphy2: combi-phy@fe840000 { reg = <0x0 0xfe840000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY2>; rockchip,pipe-phy-grf = <&pipe_phy_grf2>; #phy-cells = <1>; status = "disabled"; sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; } ============== Example from phy-rockchip-usb.c: for_each_available_child_of_node(dev->of_node, child) { err = rockchip_combphy_init(phy_base, child); if (err) { of_node_put(child); return err; } } ============== Example from phy-rockchip-inno-usb2.c: /* initialize otg/host port separately */ if (of_node_name_eq(child_np, "host-port")) { ret = rockchip_usb3phy_host_port_init(rphy, rport, child_np); if (ret) goto put_child; } else { ret = rockchip_usb3phy_otg_port_init(rphy, rport, child_np); if (ret) goto put_child; } =============== Example from dwmac-rk.c: /* Multiple Naneng phy controllers need * to be distinguished. */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res) { int i = 0; while (ops->regs[i]) { if (ops->regs[i] == res->start) { bsp_priv->id = i; break; } i++; } } ================ On 12/15/21 10:56 AM, Yifeng Zhao wrote: > Add the core dt-node for the rk3568's naneng combo phys. > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > --- > > Changes in v5: > - remove apb reset > > Changes in v4: > - rename node name > - remove reset-names > - move #phy-cells > - add rockchip,rk3568-pipe-grf > - add rockchip,rk3568-pipe-phy-grf > > Changes in v3: > - Move pipe_phy_grf0 to rk3568.dtsi > > Changes in v2: > - Move phy0 to rk3568.dtsi > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ > 2 files changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > index 2fd313a295f8..91a0b798b857 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -8,6 +8,11 @@ > / { > compatible = "rockchip,rk3568"; > > + pipe_phy_grf0: syscon@fdc70000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc70000 0x0 0x1000>; > + }; > + > qos_pcie3x1: qos@fe190080 { > compatible = "rockchip,rk3568-qos", "syscon"; > reg = <0x0 0xfe190080 0x0 0x20>; > @@ -71,6 +76,22 @@ > queue0 {}; > }; > }; > + > + combphy0: phy@fe820000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe820000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY0_REF>, > + <&cru PCLK_PIPEPHY0>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY0>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > }; > > &cpu0_opp_table { > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index a68033a23975..93f230f799f1 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -218,11 +218,26 @@ > }; > }; > > + pipegrf: syscon@fdc50000 { > + compatible = "rockchip,rk3568-pipe-grf", "syscon"; > + reg = <0x0 0xfdc50000 0x0 0x1000>; > + }; > + > grf: syscon@fdc60000 { > compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; > reg = <0x0 0xfdc60000 0x0 0x10000>; > }; > > + pipe_phy_grf1: syscon@fdc80000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc80000 0x0 0x1000>; > + }; > + > + pipe_phy_grf2: syscon@fdc90000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc90000 0x0 0x1000>; > + }; > + > pmucru: clock-controller@fdd00000 { > compatible = "rockchip,rk3568-pmucru"; > reg = <0x0 0xfdd00000 0x0 0x1000>; > @@ -1141,6 +1156,38 @@ > status = "disabled"; > }; > > + combphy1: phy@fe830000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe830000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY1_REF>, > + <&cru PCLK_PIPEPHY1>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY1>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > + combphy2: phy@fe840000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe840000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY2_REF>, > + <&cru PCLK_PIPEPHY2>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY2>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > pinctrl: pinctrl { > compatible = "rockchip,rk3568-pinctrl"; > rockchip,grf = <&grf>; > ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 @ 2021-12-16 12:19 ` Johan Jonker 0 siblings, 0 replies; 34+ messages in thread From: Johan Jonker @ 2021-12-16 12:19 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: robh+dt, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang Hi Heiko, Yifeng, Could you advise whether we should change the DT layout and driver a bit. Some properties don't really fit to one particular phy node, so move them to a parent node. Maybe replace rockchip,sgmii-mac-sel by a node in phy 1 and 2 ?? Also there are two USB3.0 Controllers, one can use as USB3.0 OTG Controller, another one can use as USB3.0 Host Controller only. Yet properties are called: rockchip,dis-u3otg0-port, rockchip,dis-u3otg1-port. Maybe replace them by a node ?? Unknown capabilities of future (rk3588) Naneng versions (combined host and otg ??) Maybe follow more in line with the phy-rockchip-inno-usb2.c and phy-rockchip-usb.c drivers. Could you confirm combo PHY on the RK3566 lacks the QSGMII/SGMII stuff? (Lack of rk3566 TRM) With so many differences maybe use separate compatible string and keep the DT nodes completely apart. (rockchip,rk3566-naneng-combphy, rockchip,rk3568-naneng-combphy) Johan ================================ combphy: combphy { compatible = "rockchip,rk3568-naneng-combphy"; ======== rockchip,ext-refclk; rockchip,enable-ssc; rockchip,pipe-grf = <&pipegrf>; ======== #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; combphy0: combi-phy@fe820000 { reg = <0x0 0xfe820000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY0>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; #phy-cells = <1>; status = "disabled"; u3phy0_otg: otg-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === }; }; combphy1: combi-phy@fe830000 { reg = <0x0 0xfe830000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY1>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; #phy-cells = <1>; status = "disabled"; u3phy0_host: host-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === } sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; combphy2: combi-phy@fe840000 { reg = <0x0 0xfe840000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY2>; rockchip,pipe-phy-grf = <&pipe_phy_grf2>; #phy-cells = <1>; status = "disabled"; sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; } ============== Example from phy-rockchip-usb.c: for_each_available_child_of_node(dev->of_node, child) { err = rockchip_combphy_init(phy_base, child); if (err) { of_node_put(child); return err; } } ============== Example from phy-rockchip-inno-usb2.c: /* initialize otg/host port separately */ if (of_node_name_eq(child_np, "host-port")) { ret = rockchip_usb3phy_host_port_init(rphy, rport, child_np); if (ret) goto put_child; } else { ret = rockchip_usb3phy_otg_port_init(rphy, rport, child_np); if (ret) goto put_child; } =============== Example from dwmac-rk.c: /* Multiple Naneng phy controllers need * to be distinguished. */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res) { int i = 0; while (ops->regs[i]) { if (ops->regs[i] == res->start) { bsp_priv->id = i; break; } i++; } } ================ On 12/15/21 10:56 AM, Yifeng Zhao wrote: > Add the core dt-node for the rk3568's naneng combo phys. > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > --- > > Changes in v5: > - remove apb reset > > Changes in v4: > - rename node name > - remove reset-names > - move #phy-cells > - add rockchip,rk3568-pipe-grf > - add rockchip,rk3568-pipe-phy-grf > > Changes in v3: > - Move pipe_phy_grf0 to rk3568.dtsi > > Changes in v2: > - Move phy0 to rk3568.dtsi > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ > 2 files changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > index 2fd313a295f8..91a0b798b857 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -8,6 +8,11 @@ > / { > compatible = "rockchip,rk3568"; > > + pipe_phy_grf0: syscon@fdc70000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc70000 0x0 0x1000>; > + }; > + > qos_pcie3x1: qos@fe190080 { > compatible = "rockchip,rk3568-qos", "syscon"; > reg = <0x0 0xfe190080 0x0 0x20>; > @@ -71,6 +76,22 @@ > queue0 {}; > }; > }; > + > + combphy0: phy@fe820000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe820000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY0_REF>, > + <&cru PCLK_PIPEPHY0>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY0>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > }; > > &cpu0_opp_table { > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index a68033a23975..93f230f799f1 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -218,11 +218,26 @@ > }; > }; > > + pipegrf: syscon@fdc50000 { > + compatible = "rockchip,rk3568-pipe-grf", "syscon"; > + reg = <0x0 0xfdc50000 0x0 0x1000>; > + }; > + > grf: syscon@fdc60000 { > compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; > reg = <0x0 0xfdc60000 0x0 0x10000>; > }; > > + pipe_phy_grf1: syscon@fdc80000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc80000 0x0 0x1000>; > + }; > + > + pipe_phy_grf2: syscon@fdc90000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc90000 0x0 0x1000>; > + }; > + > pmucru: clock-controller@fdd00000 { > compatible = "rockchip,rk3568-pmucru"; > reg = <0x0 0xfdd00000 0x0 0x1000>; > @@ -1141,6 +1156,38 @@ > status = "disabled"; > }; > > + combphy1: phy@fe830000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe830000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY1_REF>, > + <&cru PCLK_PIPEPHY1>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY1>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > + combphy2: phy@fe840000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe840000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY2_REF>, > + <&cru PCLK_PIPEPHY2>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY2>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > pinctrl: pinctrl { > compatible = "rockchip,rk3568-pinctrl"; > rockchip,grf = <&grf>; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 @ 2021-12-16 12:19 ` Johan Jonker 0 siblings, 0 replies; 34+ messages in thread From: Johan Jonker @ 2021-12-16 12:19 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: robh+dt, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang Hi Heiko, Yifeng, Could you advise whether we should change the DT layout and driver a bit. Some properties don't really fit to one particular phy node, so move them to a parent node. Maybe replace rockchip,sgmii-mac-sel by a node in phy 1 and 2 ?? Also there are two USB3.0 Controllers, one can use as USB3.0 OTG Controller, another one can use as USB3.0 Host Controller only. Yet properties are called: rockchip,dis-u3otg0-port, rockchip,dis-u3otg1-port. Maybe replace them by a node ?? Unknown capabilities of future (rk3588) Naneng versions (combined host and otg ??) Maybe follow more in line with the phy-rockchip-inno-usb2.c and phy-rockchip-usb.c drivers. Could you confirm combo PHY on the RK3566 lacks the QSGMII/SGMII stuff? (Lack of rk3566 TRM) With so many differences maybe use separate compatible string and keep the DT nodes completely apart. (rockchip,rk3566-naneng-combphy, rockchip,rk3568-naneng-combphy) Johan ================================ combphy: combphy { compatible = "rockchip,rk3568-naneng-combphy"; ======== rockchip,ext-refclk; rockchip,enable-ssc; rockchip,pipe-grf = <&pipegrf>; ======== #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; combphy0: combi-phy@fe820000 { reg = <0x0 0xfe820000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY0>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; #phy-cells = <1>; status = "disabled"; u3phy0_otg: otg-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === }; }; combphy1: combi-phy@fe830000 { reg = <0x0 0xfe830000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY1>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; #phy-cells = <1>; status = "disabled"; u3phy0_host: host-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === } sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; combphy2: combi-phy@fe840000 { reg = <0x0 0xfe840000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY2>; rockchip,pipe-phy-grf = <&pipe_phy_grf2>; #phy-cells = <1>; status = "disabled"; sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; } ============== Example from phy-rockchip-usb.c: for_each_available_child_of_node(dev->of_node, child) { err = rockchip_combphy_init(phy_base, child); if (err) { of_node_put(child); return err; } } ============== Example from phy-rockchip-inno-usb2.c: /* initialize otg/host port separately */ if (of_node_name_eq(child_np, "host-port")) { ret = rockchip_usb3phy_host_port_init(rphy, rport, child_np); if (ret) goto put_child; } else { ret = rockchip_usb3phy_otg_port_init(rphy, rport, child_np); if (ret) goto put_child; } =============== Example from dwmac-rk.c: /* Multiple Naneng phy controllers need * to be distinguished. */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res) { int i = 0; while (ops->regs[i]) { if (ops->regs[i] == res->start) { bsp_priv->id = i; break; } i++; } } ================ On 12/15/21 10:56 AM, Yifeng Zhao wrote: > Add the core dt-node for the rk3568's naneng combo phys. > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > --- > > Changes in v5: > - remove apb reset > > Changes in v4: > - rename node name > - remove reset-names > - move #phy-cells > - add rockchip,rk3568-pipe-grf > - add rockchip,rk3568-pipe-phy-grf > > Changes in v3: > - Move pipe_phy_grf0 to rk3568.dtsi > > Changes in v2: > - Move phy0 to rk3568.dtsi > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ > 2 files changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > index 2fd313a295f8..91a0b798b857 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -8,6 +8,11 @@ > / { > compatible = "rockchip,rk3568"; > > + pipe_phy_grf0: syscon@fdc70000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc70000 0x0 0x1000>; > + }; > + > qos_pcie3x1: qos@fe190080 { > compatible = "rockchip,rk3568-qos", "syscon"; > reg = <0x0 0xfe190080 0x0 0x20>; > @@ -71,6 +76,22 @@ > queue0 {}; > }; > }; > + > + combphy0: phy@fe820000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe820000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY0_REF>, > + <&cru PCLK_PIPEPHY0>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY0>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > }; > > &cpu0_opp_table { > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index a68033a23975..93f230f799f1 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -218,11 +218,26 @@ > }; > }; > > + pipegrf: syscon@fdc50000 { > + compatible = "rockchip,rk3568-pipe-grf", "syscon"; > + reg = <0x0 0xfdc50000 0x0 0x1000>; > + }; > + > grf: syscon@fdc60000 { > compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; > reg = <0x0 0xfdc60000 0x0 0x10000>; > }; > > + pipe_phy_grf1: syscon@fdc80000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc80000 0x0 0x1000>; > + }; > + > + pipe_phy_grf2: syscon@fdc90000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc90000 0x0 0x1000>; > + }; > + > pmucru: clock-controller@fdd00000 { > compatible = "rockchip,rk3568-pmucru"; > reg = <0x0 0xfdd00000 0x0 0x1000>; > @@ -1141,6 +1156,38 @@ > status = "disabled"; > }; > > + combphy1: phy@fe830000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe830000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY1_REF>, > + <&cru PCLK_PIPEPHY1>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY1>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > + combphy2: phy@fe840000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe840000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY2_REF>, > + <&cru PCLK_PIPEPHY2>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY2>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > pinctrl: pinctrl { > compatible = "rockchip,rk3568-pinctrl"; > rockchip,grf = <&grf>; > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 @ 2021-12-16 12:19 ` Johan Jonker 0 siblings, 0 replies; 34+ messages in thread From: Johan Jonker @ 2021-12-16 12:19 UTC (permalink / raw) To: Yifeng Zhao, heiko Cc: robh+dt, devicetree, vkoul, michael.riesch, linux-rockchip, linux-arm-kernel, linux-kernel, linux-phy, kishon, p.zabel, cl, kever.yang Hi Heiko, Yifeng, Could you advise whether we should change the DT layout and driver a bit. Some properties don't really fit to one particular phy node, so move them to a parent node. Maybe replace rockchip,sgmii-mac-sel by a node in phy 1 and 2 ?? Also there are two USB3.0 Controllers, one can use as USB3.0 OTG Controller, another one can use as USB3.0 Host Controller only. Yet properties are called: rockchip,dis-u3otg0-port, rockchip,dis-u3otg1-port. Maybe replace them by a node ?? Unknown capabilities of future (rk3588) Naneng versions (combined host and otg ??) Maybe follow more in line with the phy-rockchip-inno-usb2.c and phy-rockchip-usb.c drivers. Could you confirm combo PHY on the RK3566 lacks the QSGMII/SGMII stuff? (Lack of rk3566 TRM) With so many differences maybe use separate compatible string and keep the DT nodes completely apart. (rockchip,rk3566-naneng-combphy, rockchip,rk3568-naneng-combphy) Johan ================================ combphy: combphy { compatible = "rockchip,rk3568-naneng-combphy"; ======== rockchip,ext-refclk; rockchip,enable-ssc; rockchip,pipe-grf = <&pipegrf>; ======== #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; combphy0: combi-phy@fe820000 { reg = <0x0 0xfe820000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY0>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; #phy-cells = <1>; status = "disabled"; u3phy0_otg: otg-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === }; }; combphy1: combi-phy@fe830000 { reg = <0x0 0xfe830000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY1>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; #phy-cells = <1>; status = "disabled"; u3phy0_host: host-port { === /* ??? */ #phy-cells = <0>; status = "disabled"; === } sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; combphy2: combi-phy@fe840000 { reg = <0x0 0xfe840000 0x0 0x100>; clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, <&cru PCLK_PIPE>; clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY2>; rockchip,pipe-phy-grf = <&pipe_phy_grf2>; #phy-cells = <1>; status = "disabled"; sgmii_port: sgmii-port { /* ??? */ status = "disabled"; } }; } ============== Example from phy-rockchip-usb.c: for_each_available_child_of_node(dev->of_node, child) { err = rockchip_combphy_init(phy_base, child); if (err) { of_node_put(child); return err; } } ============== Example from phy-rockchip-inno-usb2.c: /* initialize otg/host port separately */ if (of_node_name_eq(child_np, "host-port")) { ret = rockchip_usb3phy_host_port_init(rphy, rport, child_np); if (ret) goto put_child; } else { ret = rockchip_usb3phy_otg_port_init(rphy, rport, child_np); if (ret) goto put_child; } =============== Example from dwmac-rk.c: /* Multiple Naneng phy controllers need * to be distinguished. */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res) { int i = 0; while (ops->regs[i]) { if (ops->regs[i] == res->start) { bsp_priv->id = i; break; } i++; } } ================ On 12/15/21 10:56 AM, Yifeng Zhao wrote: > Add the core dt-node for the rk3568's naneng combo phys. > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > --- > > Changes in v5: > - remove apb reset > > Changes in v4: > - rename node name > - remove reset-names > - move #phy-cells > - add rockchip,rk3568-pipe-grf > - add rockchip,rk3568-pipe-phy-grf > > Changes in v3: > - Move pipe_phy_grf0 to rk3568.dtsi > > Changes in v2: > - Move phy0 to rk3568.dtsi > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ > 2 files changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > index 2fd313a295f8..91a0b798b857 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -8,6 +8,11 @@ > / { > compatible = "rockchip,rk3568"; > > + pipe_phy_grf0: syscon@fdc70000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc70000 0x0 0x1000>; > + }; > + > qos_pcie3x1: qos@fe190080 { > compatible = "rockchip,rk3568-qos", "syscon"; > reg = <0x0 0xfe190080 0x0 0x20>; > @@ -71,6 +76,22 @@ > queue0 {}; > }; > }; > + > + combphy0: phy@fe820000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe820000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY0_REF>, > + <&cru PCLK_PIPEPHY0>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY0>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > }; > > &cpu0_opp_table { > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index a68033a23975..93f230f799f1 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -218,11 +218,26 @@ > }; > }; > > + pipegrf: syscon@fdc50000 { > + compatible = "rockchip,rk3568-pipe-grf", "syscon"; > + reg = <0x0 0xfdc50000 0x0 0x1000>; > + }; > + > grf: syscon@fdc60000 { > compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; > reg = <0x0 0xfdc60000 0x0 0x10000>; > }; > > + pipe_phy_grf1: syscon@fdc80000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc80000 0x0 0x1000>; > + }; > + > + pipe_phy_grf2: syscon@fdc90000 { > + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > + reg = <0x0 0xfdc90000 0x0 0x1000>; > + }; > + > pmucru: clock-controller@fdd00000 { > compatible = "rockchip,rk3568-pmucru"; > reg = <0x0 0xfdd00000 0x0 0x1000>; > @@ -1141,6 +1156,38 @@ > status = "disabled"; > }; > > + combphy1: phy@fe830000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe830000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY1_REF>, > + <&cru PCLK_PIPEPHY1>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY1>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > + combphy2: phy@fe840000 { > + compatible = "rockchip,rk3568-naneng-combphy"; > + reg = <0x0 0xfe840000 0x0 0x100>; > + clocks = <&pmucru CLK_PCIEPHY2_REF>, > + <&cru PCLK_PIPEPHY2>, > + <&cru PCLK_PIPE>; > + clock-names = "ref", "apb", "pipe"; > + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; > + assigned-clock-rates = <100000000>; > + resets = <&cru SRST_PIPEPHY2>; > + rockchip,pipe-grf = <&pipegrf>; > + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > + > pinctrl: pinctrl { > compatible = "rockchip,rk3568-pinctrl"; > rockchip,grf = <&grf>; > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2021-12-23 11:21 UTC | newest] Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-15 9:56 [PATCH v5 0/4] Add Naneng combo PHY support for RK3568 Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` [PATCH v5 1/4] dt-bindings: mfd: syscon: add naneng combo phy register compatible Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` [PATCH v5 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 22:47 ` kernel test robot 2021-12-15 22:47 ` kernel test robot 2021-12-15 22:47 ` kernel test robot 2021-12-15 22:47 ` kernel test robot 2021-12-15 22:47 ` kernel test robot 2021-12-23 11:19 ` Vinod Koul 2021-12-23 11:19 ` Vinod Koul 2021-12-23 11:19 ` Vinod Koul 2021-12-23 11:19 ` Vinod Koul 2021-12-23 11:19 ` Vinod Koul 2021-12-15 9:56 ` [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-15 9:56 ` Yifeng Zhao 2021-12-16 12:19 ` Johan Jonker 2021-12-16 12:19 ` Johan Jonker 2021-12-16 12:19 ` Johan Jonker 2021-12-16 12:19 ` Johan Jonker
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