* [Intel-gfx] [PATCH v9 0/6] More preparation for multi gt patches
@ 2021-12-19 21:24 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
Hi,
thanks Matt for merging the first 10 patches from v8. This series
contains only the last 6 patches from the previous that make use
of the newly inserted to_gt() to reach the ggtt that at the end
moves from the i915 structure to the gt.
I have reshuffled a bit the order of the patche (refer to the
changelog) so that from this series only patch 2 remains
unreviewed.
Thanks Matt and Sujaritha for the reviews.
Andi
Changelog:
==========
Patchwork: https://patchwork.freedesktop.org/series/97020/
v8 -> v9:
- The patch is down to the last 6 patches.
- Reshuffled a bit the order, it's more intuitive to apply the
changes starting from i915/gt/, i915/, i915/gem, i915/display,
i915/selftests
- Addressed Matt's comments in v8.
- Added Matt and Sujaritha's r-b tags
v7 -> v8:
- Removed patch 11 from v7 that was allocating statically the
ggtt in the gt structure instead of a dynamic allocation. As
Matt pointed out, we can have GT's sharing the same GGTT.
- The whole i915->ggtt to gt->ggtt patch is split in 5 patches
instead of one single to make it easier to review.
- The last patch removes i915->ggtt and allocates the gt->ggtt
with drmm_kzalloc in the early probe and mock device.
v6 -> v7:
- Patch 1: add a note about the double presence of
__intel_gt_init_early() and intel_gt_init_early().
- Added all Matt's r-b's for patches 2-10.
- Added a patch 12 that moves the i915->ggtt into gt->ggtt.
v5 -> v6:
- fixed the assignement of i915->gt->ggtt = ggtt in the mock gem
device that was making use of it before.
v4 -> v5:
- use to_gt() instead of to_root_gt() and use Michał work done
previously.
- split the /i915->gt/to_gt()/ patch in smaller chunks in order
to make review easier. (Thanks Lucas)
v3 -> v4:
- the intel_gt_init_early() has been split as it was causing
some headaches for the order of the early initialization. The
split has been done keeping in mind the coming next patch in
the series that wil make this a static function.
v2 -> v3:
- sed -i ... took too much freedom and changed more than it was
supposed to.
- fix a compile error which did not appear in my local build
v1 -> v2:
- patch 2: do not use anymore the reference i915->gt but use
to_root_gt(), coming from Matt Roper's patch.
- fix some comments from Chris.
Andi Shyti (4):
drm/i915/selftests: Use to_gt() helper
drm/i915/pxp: Use to_gt() helper
drm/i915: Rename i915->gt to i915->gt0
drm/i915: Move the GGTT from i915 private data to the GT
Andi Shyti (1):
drm/i915: Remove unused i915->ggtt
Michał Winiarski (5):
drm/i915/gt: Use to_gt() helper for GGTT accesses
drm/i915: Use to_gt() helper for GGTT accesses
drm/i915/gem: Use to_gt() helper for GGTT accesses
drm/i915/display: Use to_gt() helper for GGTT accesses
drm/i915/selftests: Use to_gt() helper for GGTT accesses
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
.../drm/i915/display/intel_plane_initial.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 19 +++++++-------
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 6 ++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8 +++---
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 15 ++++++-----
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c | 19 +++++++-------
.../drm/i915/gem/selftests/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++-----
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 ++---
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++--
drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 +--
drivers/gpu/drm/i915/i915_driver.c | 10 ++++---
drivers/gpu/drm/i915/i915_drv.h | 4 +--
drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++--------
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 +--
drivers/gpu/drm/i915/selftests/i915_gem.c | 8 +++---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 26 ++++++++++---------
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 22 +++++++++-------
.../gpu/drm/i915/selftests/mock_gem_device.c | 11 +++++---
drivers/gpu/drm/i915/selftests/mock_gtt.c | 9 +++----
drivers/gpu/drm/i915/selftests/mock_gtt.h | 3 ++-
35 files changed, 137 insertions(+), 119 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v9 1/6] drm/i915/gt: Use to_gt() helper for GGTT accesses
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-19 21:24 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++++-------
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 971e737b37b2..ec3b998392ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -89,7 +89,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
* beyond the end of the batch buffer, across the page boundary,
* and beyond the end of the GTT if we do not provide a guard.
*/
- ret = ggtt_init_hw(&i915->ggtt);
+ ret = ggtt_init_hw(to_gt(i915)->ggtt);
if (ret)
return ret;
@@ -725,14 +725,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)
{
int ret;
- ret = init_ggtt(&i915->ggtt);
+ ret = init_ggtt(to_gt(i915)->ggtt);
if (ret)
return ret;
if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
- ret = init_aliasing_ppgtt(&i915->ggtt);
+ ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
if (ret)
- cleanup_init_ggtt(&i915->ggtt);
+ cleanup_init_ggtt(to_gt(i915)->ggtt);
}
return 0;
@@ -775,7 +775,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
*/
void i915_ggtt_driver_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
fini_aliasing_ppgtt(ggtt);
@@ -790,7 +790,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)
*/
void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
dma_resv_fini(&ggtt->vm._resv);
@@ -1232,7 +1232,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
int ret;
- ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
+ ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..beabf3bc9b75 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
- i915->ggtt.bit_6_swizzle_x = swizzle_x;
- i915->ggtt.bit_6_swizzle_y = swizzle_y;
+ to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
+ to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
}
/*
@@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
if (GRAPHICS_VER(i915) < 5 ||
- i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+ to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fde2dcb59809..21215a080088 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,7 +15,7 @@
static int init_fake_lmem_bar(struct intel_memory_region *mem)
{
struct drm_i915_private *i915 = mem->i915;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
unsigned long n;
int ret;
@@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
if (!i915->params.fake_lmem_start)
return ERR_PTR(-ENODEV);
- GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
+ GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
/* Your mappable aperture belongs to me now! */
mappable_end = pci_resource_len(pdev, 2);
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 8a873f6bda7f..37c38bdd5f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
intel_engine_mask_t mask,
const char *msg)
{
- struct i915_ggtt *ggtt = >->i915->ggtt;
+ struct i915_ggtt *ggtt = gt->ggtt;
const struct resource *dsm = >->i915->dsm;
resource_size_t num_pages, page;
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 95174938b160..60f8cbf24de7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,6 +571,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
i915_perf_init(dev_priv);
+ intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
+
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
goto err_perf;
@@ -587,8 +589,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_ggtt;
- intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
-
ret = intel_gt_probe_lmem(to_gt(dev_priv));
if (ret)
goto err_mem_regions;
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v9 1/6] drm/i915/gt: Use to_gt() helper for GGTT accesses
@ 2021-12-19 21:24 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++++-------
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 971e737b37b2..ec3b998392ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -89,7 +89,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
* beyond the end of the batch buffer, across the page boundary,
* and beyond the end of the GTT if we do not provide a guard.
*/
- ret = ggtt_init_hw(&i915->ggtt);
+ ret = ggtt_init_hw(to_gt(i915)->ggtt);
if (ret)
return ret;
@@ -725,14 +725,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)
{
int ret;
- ret = init_ggtt(&i915->ggtt);
+ ret = init_ggtt(to_gt(i915)->ggtt);
if (ret)
return ret;
if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
- ret = init_aliasing_ppgtt(&i915->ggtt);
+ ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
if (ret)
- cleanup_init_ggtt(&i915->ggtt);
+ cleanup_init_ggtt(to_gt(i915)->ggtt);
}
return 0;
@@ -775,7 +775,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
*/
void i915_ggtt_driver_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
fini_aliasing_ppgtt(ggtt);
@@ -790,7 +790,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)
*/
void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
dma_resv_fini(&ggtt->vm._resv);
@@ -1232,7 +1232,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
int ret;
- ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
+ ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..beabf3bc9b75 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
- i915->ggtt.bit_6_swizzle_x = swizzle_x;
- i915->ggtt.bit_6_swizzle_y = swizzle_y;
+ to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
+ to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
}
/*
@@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
if (GRAPHICS_VER(i915) < 5 ||
- i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+ to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fde2dcb59809..21215a080088 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,7 +15,7 @@
static int init_fake_lmem_bar(struct intel_memory_region *mem)
{
struct drm_i915_private *i915 = mem->i915;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
unsigned long n;
int ret;
@@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
if (!i915->params.fake_lmem_start)
return ERR_PTR(-ENODEV);
- GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
+ GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
/* Your mappable aperture belongs to me now! */
mappable_end = pci_resource_len(pdev, 2);
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 8a873f6bda7f..37c38bdd5f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
intel_engine_mask_t mask,
const char *msg)
{
- struct i915_ggtt *ggtt = >->i915->ggtt;
+ struct i915_ggtt *ggtt = gt->ggtt;
const struct resource *dsm = >->i915->dsm;
resource_size_t num_pages, page;
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 95174938b160..60f8cbf24de7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,6 +571,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
i915_perf_init(dev_priv);
+ intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
+
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
goto err_perf;
@@ -587,8 +589,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_ggtt;
- intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
-
ret = intel_gt_probe_lmem(to_gt(dev_priv));
if (ret)
goto err_mem_regions;
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH v9 1/6] drm/i915/gt: Use to_gt() helper for GGTT accesses
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-21 16:47 ` Matt Roper
-1 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2021-12-21 16:47 UTC (permalink / raw)
To: Andi Shyti
Cc: Sujaritha Sundaresan, Intel GFX, Lucas De Marchi, DRI Devel,
Chris Wilson, Andi Shyti, Michał Winiarski
On Sun, Dec 19, 2021 at 11:24:55PM +0200, Andi Shyti wrote:
> From: Michał Winiarski <michal.winiarski@intel.com>
>
> GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> eventually want to get rid of the i915->ggtt one.
> Use to_gt() for all i915->ggtt accesses to help with the future
> refactoring.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++++-------
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +++---
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
> drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> 5 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 971e737b37b2..ec3b998392ff 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -89,7 +89,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
> * beyond the end of the batch buffer, across the page boundary,
> * and beyond the end of the GTT if we do not provide a guard.
> */
> - ret = ggtt_init_hw(&i915->ggtt);
> + ret = ggtt_init_hw(to_gt(i915)->ggtt);
> if (ret)
> return ret;
>
> @@ -725,14 +725,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)
> {
> int ret;
>
> - ret = init_ggtt(&i915->ggtt);
> + ret = init_ggtt(to_gt(i915)->ggtt);
> if (ret)
> return ret;
>
> if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
> - ret = init_aliasing_ppgtt(&i915->ggtt);
> + ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
> if (ret)
> - cleanup_init_ggtt(&i915->ggtt);
> + cleanup_init_ggtt(to_gt(i915)->ggtt);
> }
>
> return 0;
> @@ -775,7 +775,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
> */
> void i915_ggtt_driver_release(struct drm_i915_private *i915)
> {
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> fini_aliasing_ppgtt(ggtt);
>
> @@ -790,7 +790,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)
> */
> void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
> {
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
> dma_resv_fini(&ggtt->vm._resv);
> @@ -1232,7 +1232,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> {
> int ret;
>
> - ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
> + ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index f8948de72036..beabf3bc9b75 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> }
>
> - i915->ggtt.bit_6_swizzle_x = swizzle_x;
> - i915->ggtt.bit_6_swizzle_y = swizzle_y;
> + to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
> + to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
> }
>
> /*
> @@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
> struct intel_uncore *uncore = gt->uncore;
>
> if (GRAPHICS_VER(i915) < 5 ||
> - i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> + to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> return;
>
> intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index fde2dcb59809..21215a080088 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -15,7 +15,7 @@
> static int init_fake_lmem_bar(struct intel_memory_region *mem)
> {
> struct drm_i915_private *i915 = mem->i915;
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> unsigned long n;
> int ret;
>
> @@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
> if (!i915->params.fake_lmem_start)
> return ERR_PTR(-ENODEV);
>
> - GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
> + GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
>
> /* Your mappable aperture belongs to me now! */
> mappable_end = pci_resource_len(pdev, 2);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
> index 8a873f6bda7f..37c38bdd5f47 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> @@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
> intel_engine_mask_t mask,
> const char *msg)
> {
> - struct i915_ggtt *ggtt = >->i915->ggtt;
> + struct i915_ggtt *ggtt = gt->ggtt;
> const struct resource *dsm = >->i915->dsm;
> resource_size_t num_pages, page;
> struct intel_engine_cs *engine;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 95174938b160..60f8cbf24de7 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -571,6 +571,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>
> i915_perf_init(dev_priv);
>
> + intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
> +
Now that this function call has moved to this patch, you'll probably
want to mention/explain it in the commit message since it's different
from the rest of the changes in this patch.
Matt
> ret = i915_ggtt_probe_hw(dev_priv);
> if (ret)
> goto err_perf;
> @@ -587,8 +589,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> if (ret)
> goto err_ggtt;
>
> - intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
> -
> ret = intel_gt_probe_lmem(to_gt(dev_priv));
> if (ret)
> goto err_mem_regions;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v9 1/6] drm/i915/gt: Use to_gt() helper for GGTT accesses
@ 2021-12-21 16:47 ` Matt Roper
0 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2021-12-21 16:47 UTC (permalink / raw)
To: Andi Shyti
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Michał Winiarski
On Sun, Dec 19, 2021 at 11:24:55PM +0200, Andi Shyti wrote:
> From: Michał Winiarski <michal.winiarski@intel.com>
>
> GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> eventually want to get rid of the i915->ggtt one.
> Use to_gt() for all i915->ggtt accesses to help with the future
> refactoring.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++++-------
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +++---
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
> drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> 5 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 971e737b37b2..ec3b998392ff 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -89,7 +89,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
> * beyond the end of the batch buffer, across the page boundary,
> * and beyond the end of the GTT if we do not provide a guard.
> */
> - ret = ggtt_init_hw(&i915->ggtt);
> + ret = ggtt_init_hw(to_gt(i915)->ggtt);
> if (ret)
> return ret;
>
> @@ -725,14 +725,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)
> {
> int ret;
>
> - ret = init_ggtt(&i915->ggtt);
> + ret = init_ggtt(to_gt(i915)->ggtt);
> if (ret)
> return ret;
>
> if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
> - ret = init_aliasing_ppgtt(&i915->ggtt);
> + ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
> if (ret)
> - cleanup_init_ggtt(&i915->ggtt);
> + cleanup_init_ggtt(to_gt(i915)->ggtt);
> }
>
> return 0;
> @@ -775,7 +775,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
> */
> void i915_ggtt_driver_release(struct drm_i915_private *i915)
> {
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> fini_aliasing_ppgtt(ggtt);
>
> @@ -790,7 +790,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)
> */
> void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
> {
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
> dma_resv_fini(&ggtt->vm._resv);
> @@ -1232,7 +1232,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> {
> int ret;
>
> - ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
> + ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index f8948de72036..beabf3bc9b75 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> }
>
> - i915->ggtt.bit_6_swizzle_x = swizzle_x;
> - i915->ggtt.bit_6_swizzle_y = swizzle_y;
> + to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
> + to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
> }
>
> /*
> @@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
> struct intel_uncore *uncore = gt->uncore;
>
> if (GRAPHICS_VER(i915) < 5 ||
> - i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> + to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> return;
>
> intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index fde2dcb59809..21215a080088 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -15,7 +15,7 @@
> static int init_fake_lmem_bar(struct intel_memory_region *mem)
> {
> struct drm_i915_private *i915 = mem->i915;
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> unsigned long n;
> int ret;
>
> @@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
> if (!i915->params.fake_lmem_start)
> return ERR_PTR(-ENODEV);
>
> - GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
> + GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
>
> /* Your mappable aperture belongs to me now! */
> mappable_end = pci_resource_len(pdev, 2);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
> index 8a873f6bda7f..37c38bdd5f47 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> @@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
> intel_engine_mask_t mask,
> const char *msg)
> {
> - struct i915_ggtt *ggtt = >->i915->ggtt;
> + struct i915_ggtt *ggtt = gt->ggtt;
> const struct resource *dsm = >->i915->dsm;
> resource_size_t num_pages, page;
> struct intel_engine_cs *engine;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 95174938b160..60f8cbf24de7 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -571,6 +571,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>
> i915_perf_init(dev_priv);
>
> + intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
> +
Now that this function call has moved to this patch, you'll probably
want to mention/explain it in the commit message since it's different
from the rest of the changes in this patch.
Matt
> ret = i915_ggtt_probe_hw(dev_priv);
> if (ret)
> goto err_perf;
> @@ -587,8 +589,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> if (ret)
> goto err_ggtt;
>
> - intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
> -
> ret = intel_gt_probe_lmem(to_gt(dev_priv));
> if (ret)
> goto err_mem_regions;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* [PATCH v10 1/6] drm/i915/gt: Use to_gt() helper for GGTT accesses
2021-12-21 16:47 ` [Intel-gfx] " Matt Roper
@ 2021-12-21 19:59 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-21 19:59 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
During the probe of i915 the early intiialization of the gt
(intel_gt_init_hw_early()) is moved prior to any access to the
ggtt. This because it's in that moment we assign the ggtt to the
gt and we want to do that before using it.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
Hi Matt,
just added a small paragraph in this commit log to highlight the
even erlier early initialization of the gt.
Andi
drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++++-------
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 5263dda7f8d5..ab6c4322dc08 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -86,7 +86,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
* beyond the end of the batch buffer, across the page boundary,
* and beyond the end of the GTT if we do not provide a guard.
*/
- ret = ggtt_init_hw(&i915->ggtt);
+ ret = ggtt_init_hw(to_gt(i915)->ggtt);
if (ret)
return ret;
@@ -722,14 +722,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)
{
int ret;
- ret = init_ggtt(&i915->ggtt);
+ ret = init_ggtt(to_gt(i915)->ggtt);
if (ret)
return ret;
if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
- ret = init_aliasing_ppgtt(&i915->ggtt);
+ ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
if (ret)
- cleanup_init_ggtt(&i915->ggtt);
+ cleanup_init_ggtt(to_gt(i915)->ggtt);
}
return 0;
@@ -772,7 +772,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
*/
void i915_ggtt_driver_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
fini_aliasing_ppgtt(ggtt);
@@ -787,7 +787,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)
*/
void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
dma_resv_fini(&ggtt->vm._resv);
@@ -1208,7 +1208,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
int ret;
- ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
+ ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..beabf3bc9b75 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
- i915->ggtt.bit_6_swizzle_x = swizzle_x;
- i915->ggtt.bit_6_swizzle_y = swizzle_y;
+ to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
+ to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
}
/*
@@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
if (GRAPHICS_VER(i915) < 5 ||
- i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+ to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fde2dcb59809..21215a080088 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,7 +15,7 @@
static int init_fake_lmem_bar(struct intel_memory_region *mem)
{
struct drm_i915_private *i915 = mem->i915;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
unsigned long n;
int ret;
@@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
if (!i915->params.fake_lmem_start)
return ERR_PTR(-ENODEV);
- GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
+ GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
/* Your mappable aperture belongs to me now! */
mappable_end = pci_resource_len(pdev, 2);
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 8a873f6bda7f..37c38bdd5f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
intel_engine_mask_t mask,
const char *msg)
{
- struct i915_ggtt *ggtt = >->i915->ggtt;
+ struct i915_ggtt *ggtt = gt->ggtt;
const struct resource *dsm = >->i915->dsm;
resource_size_t num_pages, page;
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 95174938b160..60f8cbf24de7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,6 +571,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
i915_perf_init(dev_priv);
+ intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
+
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
goto err_perf;
@@ -587,8 +589,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_ggtt;
- intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
-
ret = intel_gt_probe_lmem(to_gt(dev_priv));
if (ret)
goto err_mem_regions;
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v10 1/6] drm/i915/gt: Use to_gt() helper for GGTT accesses
@ 2021-12-21 19:59 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-21 19:59 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
During the probe of i915 the early intiialization of the gt
(intel_gt_init_hw_early()) is moved prior to any access to the
ggtt. This because it's in that moment we assign the ggtt to the
gt and we want to do that before using it.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
Hi Matt,
just added a small paragraph in this commit log to highlight the
even erlier early initialization of the gt.
Andi
drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++++-------
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 5263dda7f8d5..ab6c4322dc08 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -86,7 +86,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
* beyond the end of the batch buffer, across the page boundary,
* and beyond the end of the GTT if we do not provide a guard.
*/
- ret = ggtt_init_hw(&i915->ggtt);
+ ret = ggtt_init_hw(to_gt(i915)->ggtt);
if (ret)
return ret;
@@ -722,14 +722,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)
{
int ret;
- ret = init_ggtt(&i915->ggtt);
+ ret = init_ggtt(to_gt(i915)->ggtt);
if (ret)
return ret;
if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
- ret = init_aliasing_ppgtt(&i915->ggtt);
+ ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
if (ret)
- cleanup_init_ggtt(&i915->ggtt);
+ cleanup_init_ggtt(to_gt(i915)->ggtt);
}
return 0;
@@ -772,7 +772,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
*/
void i915_ggtt_driver_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
fini_aliasing_ppgtt(ggtt);
@@ -787,7 +787,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)
*/
void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
dma_resv_fini(&ggtt->vm._resv);
@@ -1208,7 +1208,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
int ret;
- ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
+ ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..beabf3bc9b75 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
- i915->ggtt.bit_6_swizzle_x = swizzle_x;
- i915->ggtt.bit_6_swizzle_y = swizzle_y;
+ to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
+ to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
}
/*
@@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
if (GRAPHICS_VER(i915) < 5 ||
- i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+ to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fde2dcb59809..21215a080088 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,7 +15,7 @@
static int init_fake_lmem_bar(struct intel_memory_region *mem)
{
struct drm_i915_private *i915 = mem->i915;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
unsigned long n;
int ret;
@@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
if (!i915->params.fake_lmem_start)
return ERR_PTR(-ENODEV);
- GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
+ GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
/* Your mappable aperture belongs to me now! */
mappable_end = pci_resource_len(pdev, 2);
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 8a873f6bda7f..37c38bdd5f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
intel_engine_mask_t mask,
const char *msg)
{
- struct i915_ggtt *ggtt = >->i915->ggtt;
+ struct i915_ggtt *ggtt = gt->ggtt;
const struct resource *dsm = >->i915->dsm;
resource_size_t num_pages, page;
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 95174938b160..60f8cbf24de7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,6 +571,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
i915_perf_init(dev_priv);
+ intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
+
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
goto err_perf;
@@ -587,8 +589,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_ggtt;
- intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
-
ret = intel_gt_probe_lmem(to_gt(dev_priv));
if (ret)
goto err_mem_regions;
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-19 21:24 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
8 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 8e65cd8258b9..94c3eb1586b0 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
kfree(st);
return ret;
}
- gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+ gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
(fb_info->start >> PAGE_SHIFT);
for_each_sg(st->sgl, sg, page_num, i) {
dma_addr_t dma_addr =
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e0e052cdf8b8..6966fe08df92 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
intel_wakeref_t wakeref;
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
seq_puts(m, "L-shaped memory detected\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 60f8cbf24de7..3c984553d86f 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
/* Must be called before GGTT is suspended. */
intel_dpt_suspend(dev_priv);
- i915_ggtt_suspend(&dev_priv->ggtt);
+ i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
i915_save_display(dev_priv);
@@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
if (ret)
drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
/* Must be called after GGTT is resumed. */
intel_dpt_resume(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 471be2716abe..524025790fe0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1749,7 +1749,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
+ return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
i915_gem_object_is_tiled(obj);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8ba2119092f2..45e3b4c540a1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -88,7 +88,8 @@ int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
- struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
@@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
bool write)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
struct i915_gem_ww_ctx ww;
int ret;
@@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
struct i915_vma *vma)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
i915_gem_object_unpin_pages(obj);
if (drm_mm_node_allocated(node)) {
@@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
intel_wakeref_t wakeref;
struct drm_mm_node node;
void __user *user_data;
@@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t wakeref;
struct drm_mm_node node;
@@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
*/
list_for_each_entry_safe(obj, on,
- &i915->ggtt.userfault_list, userfault_link)
+ &to_gt(i915)->ggtt->userfault_list, userfault_link)
__i915_gem_object_release_mmap_gtt(obj);
/*
@@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
* in use by hardware (i.e. they are pinned), we should not be powering
* down! All other fences will be reacquired by the user upon waking.
*/
- for (i = 0; i < i915->ggtt.num_fences; i++) {
- struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
+ for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
+ struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
/*
* Ideally we want to assert that the fence register is not
@@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
u64 size, u64 alignment, u64 flags)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
int ret;
@@ -1101,7 +1102,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
/* Minimal basic recovery for KMS */
ret = i915_ggtt_enable_hw(dev_priv);
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
intel_init_clock_gating(dev_priv);
}
@@ -1124,7 +1125,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
{
- intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
+ intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
i915_gem_suspend_late(dev_priv);
intel_gt_driver_remove(to_gt(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cd5f2348a187..2f2ba7a2955d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
/* XXX This does not prevent more requests being submitted! */
if (unlikely(ggtt->do_idle_maps))
@@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(range_overflows(offset, size, vm->total));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
node->size = size;
@@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
GEM_BUG_ON(start >= end);
GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
if (unlikely(range_overflows(start, size, end)))
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 7f80ad247bc8..5b8a2157d797 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = pdev->revision;
break;
case I915_PARAM_NUM_FENCES_AVAIL:
- value = i915->ggtt.num_fences;
+ value = to_gt(i915)->ggtt->num_fences;
break;
case I915_PARAM_HAS_OVERLAY:
value = !!i915->overlay;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 170bba913c30..128315aec517 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0xffffffffffffffff -
- intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
+ intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
atomic64_read(&stream->perf->noa_programming_delay));
const u32 base = stream->engine->mmio_base;
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
@@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
{
- return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
+ return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
2ULL << exponent);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2021-12-19 21:24 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
8 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 8e65cd8258b9..94c3eb1586b0 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
kfree(st);
return ret;
}
- gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+ gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
(fb_info->start >> PAGE_SHIFT);
for_each_sg(st->sgl, sg, page_num, i) {
dma_addr_t dma_addr =
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e0e052cdf8b8..6966fe08df92 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
intel_wakeref_t wakeref;
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
seq_puts(m, "L-shaped memory detected\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 60f8cbf24de7..3c984553d86f 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
/* Must be called before GGTT is suspended. */
intel_dpt_suspend(dev_priv);
- i915_ggtt_suspend(&dev_priv->ggtt);
+ i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
i915_save_display(dev_priv);
@@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
if (ret)
drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
/* Must be called after GGTT is resumed. */
intel_dpt_resume(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 471be2716abe..524025790fe0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1749,7 +1749,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
+ return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
i915_gem_object_is_tiled(obj);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8ba2119092f2..45e3b4c540a1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -88,7 +88,8 @@ int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
- struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
@@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
bool write)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
struct i915_gem_ww_ctx ww;
int ret;
@@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
struct i915_vma *vma)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
i915_gem_object_unpin_pages(obj);
if (drm_mm_node_allocated(node)) {
@@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
intel_wakeref_t wakeref;
struct drm_mm_node node;
void __user *user_data;
@@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t wakeref;
struct drm_mm_node node;
@@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
*/
list_for_each_entry_safe(obj, on,
- &i915->ggtt.userfault_list, userfault_link)
+ &to_gt(i915)->ggtt->userfault_list, userfault_link)
__i915_gem_object_release_mmap_gtt(obj);
/*
@@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
* in use by hardware (i.e. they are pinned), we should not be powering
* down! All other fences will be reacquired by the user upon waking.
*/
- for (i = 0; i < i915->ggtt.num_fences; i++) {
- struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
+ for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
+ struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
/*
* Ideally we want to assert that the fence register is not
@@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
u64 size, u64 alignment, u64 flags)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
int ret;
@@ -1101,7 +1102,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
/* Minimal basic recovery for KMS */
ret = i915_ggtt_enable_hw(dev_priv);
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
intel_init_clock_gating(dev_priv);
}
@@ -1124,7 +1125,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
{
- intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
+ intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
i915_gem_suspend_late(dev_priv);
intel_gt_driver_remove(to_gt(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cd5f2348a187..2f2ba7a2955d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
/* XXX This does not prevent more requests being submitted! */
if (unlikely(ggtt->do_idle_maps))
@@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(range_overflows(offset, size, vm->total));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
node->size = size;
@@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
GEM_BUG_ON(start >= end);
GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
if (unlikely(range_overflows(start, size, end)))
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 7f80ad247bc8..5b8a2157d797 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = pdev->revision;
break;
case I915_PARAM_NUM_FENCES_AVAIL:
- value = i915->ggtt.num_fences;
+ value = to_gt(i915)->ggtt->num_fences;
break;
case I915_PARAM_HAS_OVERLAY:
value = !!i915->overlay;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 170bba913c30..128315aec517 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0xffffffffffffffff -
- intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
+ intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
atomic64_read(&stream->perf->noa_programming_delay));
const u32 base = stream->engine->mmio_base;
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
@@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
{
- return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
+ return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
2ULL << exponent);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-21 17:01 ` Matt Roper
-1 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2021-12-21 17:01 UTC (permalink / raw)
To: Andi Shyti
Cc: Sujaritha Sundaresan, Intel GFX, Lucas De Marchi, DRI Devel,
Chris Wilson, Andi Shyti, Michał Winiarski
On Sun, Dec 19, 2021 at 11:24:56PM +0200, Andi Shyti wrote:
> From: Michał Winiarski <michal.winiarski@intel.com>
>
> GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> eventually want to get rid of the i915->ggtt one.
> Use to_gt() for all i915->ggtt accesses to help with the future
> refactoring.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
> drivers/gpu/drm/i915/i915_getparam.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
> 8 files changed, 24 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
> index 8e65cd8258b9..94c3eb1586b0 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.c
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
> @@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
> kfree(st);
> return ret;
> }
> - gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
> + gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
> (fb_info->start >> PAGE_SHIFT);
> for_each_sg(st->sgl, sg, page_num, i) {
> dma_addr_t dma_addr =
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e0e052cdf8b8..6966fe08df92 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> intel_wakeref_t wakeref;
>
> seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
> seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
>
> if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
> seq_puts(m, "L-shaped memory detected\n");
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 60f8cbf24de7..3c984553d86f 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> /* Must be called before GGTT is suspended. */
> intel_dpt_suspend(dev_priv);
> - i915_ggtt_suspend(&dev_priv->ggtt);
> + i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
>
> i915_save_display(dev_priv);
>
> @@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
> if (ret)
> drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
>
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> /* Must be called after GGTT is resumed. */
> intel_dpt_resume(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 471be2716abe..524025790fe0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1749,7 +1749,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
>
> - return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> + return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> i915_gem_object_is_tiled(obj);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8ba2119092f2..45e3b4c540a1 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -88,7 +88,8 @@ int
> i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> - struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct drm_i915_gem_get_aperture *args = data;
> struct i915_vma *vma;
> u64 pinned;
> @@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
> bool write)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> struct i915_gem_ww_ctx ww;
> int ret;
> @@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
> struct i915_vma *vma)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> i915_gem_object_unpin_pages(obj);
> if (drm_mm_node_allocated(node)) {
> @@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pread *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> void __user *user_data;
> @@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pwrite *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct intel_runtime_pm *rpm = &i915->runtime_pm;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> @@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> */
>
> list_for_each_entry_safe(obj, on,
> - &i915->ggtt.userfault_list, userfault_link)
> + &to_gt(i915)->ggtt->userfault_list, userfault_link)
> __i915_gem_object_release_mmap_gtt(obj);
>
> /*
> @@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> * in use by hardware (i.e. they are pinned), we should not be powering
> * down! All other fences will be reacquired by the user upon waking.
> */
> - for (i = 0; i < i915->ggtt.num_fences; i++) {
> - struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
> + for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
> + struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
>
> /*
> * Ideally we want to assert that the fence register is not
> @@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
> u64 size, u64 alignment, u64 flags)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> int ret;
>
> @@ -1101,7 +1102,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>
> /* Minimal basic recovery for KMS */
> ret = i915_ggtt_enable_hw(dev_priv);
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> intel_init_clock_gating(dev_priv);
> }
>
> @@ -1124,7 +1125,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
>
> void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
> {
> - intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
> + intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
>
> i915_gem_suspend_late(dev_priv);
> intel_gt_driver_remove(to_gt(dev_priv));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cd5f2348a187..2f2ba7a2955d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
> struct sg_table *pages)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> /* XXX This does not prevent more requests being submitted! */
> if (unlikely(ggtt->do_idle_maps))
> @@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
> GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
> GEM_BUG_ON(range_overflows(offset, size, vm->total));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> node->size = size;
> @@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
> GEM_BUG_ON(start >= end);
> GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> if (unlikely(range_overflows(start, size, end)))
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 7f80ad247bc8..5b8a2157d797 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = pdev->revision;
> break;
> case I915_PARAM_NUM_FENCES_AVAIL:
> - value = i915->ggtt.num_fences;
> + value = to_gt(i915)->ggtt->num_fences;
> break;
> case I915_PARAM_HAS_OVERLAY:
> value = !!i915->overlay;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 170bba913c30..128315aec517 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> struct drm_i915_gem_object *bo;
> struct i915_vma *vma;
> const u64 delay_ticks = 0xffffffffffffffff -
> - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
I'm not too familiar with the perf code, but this looks a bit roundabout
since we're ultimately trying to get to a GT...do we even need to go
through the ggtt structure here or can we just pass
"to_gt(stream->perf->i915)" as the first parameter?
> atomic64_read(&stream->perf->noa_programming_delay));
> const u32 base = stream->engine->mmio_base;
> #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>
> static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> {
> - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
Ditto; this looks like "to_gt(perf->i915)" might be all we need?
Matt
> 2ULL << exponent);
> }
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2021-12-21 17:01 ` Matt Roper
0 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2021-12-21 17:01 UTC (permalink / raw)
To: Andi Shyti
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Michał Winiarski
On Sun, Dec 19, 2021 at 11:24:56PM +0200, Andi Shyti wrote:
> From: Michał Winiarski <michal.winiarski@intel.com>
>
> GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> eventually want to get rid of the i915->ggtt one.
> Use to_gt() for all i915->ggtt accesses to help with the future
> refactoring.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
> drivers/gpu/drm/i915/i915_getparam.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
> 8 files changed, 24 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
> index 8e65cd8258b9..94c3eb1586b0 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.c
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
> @@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
> kfree(st);
> return ret;
> }
> - gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
> + gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
> (fb_info->start >> PAGE_SHIFT);
> for_each_sg(st->sgl, sg, page_num, i) {
> dma_addr_t dma_addr =
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e0e052cdf8b8..6966fe08df92 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> intel_wakeref_t wakeref;
>
> seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
> seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
>
> if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
> seq_puts(m, "L-shaped memory detected\n");
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 60f8cbf24de7..3c984553d86f 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> /* Must be called before GGTT is suspended. */
> intel_dpt_suspend(dev_priv);
> - i915_ggtt_suspend(&dev_priv->ggtt);
> + i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
>
> i915_save_display(dev_priv);
>
> @@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
> if (ret)
> drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
>
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> /* Must be called after GGTT is resumed. */
> intel_dpt_resume(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 471be2716abe..524025790fe0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1749,7 +1749,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
>
> - return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> + return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> i915_gem_object_is_tiled(obj);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8ba2119092f2..45e3b4c540a1 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -88,7 +88,8 @@ int
> i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> - struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct drm_i915_gem_get_aperture *args = data;
> struct i915_vma *vma;
> u64 pinned;
> @@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
> bool write)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> struct i915_gem_ww_ctx ww;
> int ret;
> @@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
> struct i915_vma *vma)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> i915_gem_object_unpin_pages(obj);
> if (drm_mm_node_allocated(node)) {
> @@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pread *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> void __user *user_data;
> @@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pwrite *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct intel_runtime_pm *rpm = &i915->runtime_pm;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> @@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> */
>
> list_for_each_entry_safe(obj, on,
> - &i915->ggtt.userfault_list, userfault_link)
> + &to_gt(i915)->ggtt->userfault_list, userfault_link)
> __i915_gem_object_release_mmap_gtt(obj);
>
> /*
> @@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> * in use by hardware (i.e. they are pinned), we should not be powering
> * down! All other fences will be reacquired by the user upon waking.
> */
> - for (i = 0; i < i915->ggtt.num_fences; i++) {
> - struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
> + for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
> + struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
>
> /*
> * Ideally we want to assert that the fence register is not
> @@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
> u64 size, u64 alignment, u64 flags)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> int ret;
>
> @@ -1101,7 +1102,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>
> /* Minimal basic recovery for KMS */
> ret = i915_ggtt_enable_hw(dev_priv);
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> intel_init_clock_gating(dev_priv);
> }
>
> @@ -1124,7 +1125,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
>
> void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
> {
> - intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
> + intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
>
> i915_gem_suspend_late(dev_priv);
> intel_gt_driver_remove(to_gt(dev_priv));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cd5f2348a187..2f2ba7a2955d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
> struct sg_table *pages)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> /* XXX This does not prevent more requests being submitted! */
> if (unlikely(ggtt->do_idle_maps))
> @@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
> GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
> GEM_BUG_ON(range_overflows(offset, size, vm->total));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> node->size = size;
> @@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
> GEM_BUG_ON(start >= end);
> GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> if (unlikely(range_overflows(start, size, end)))
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 7f80ad247bc8..5b8a2157d797 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = pdev->revision;
> break;
> case I915_PARAM_NUM_FENCES_AVAIL:
> - value = i915->ggtt.num_fences;
> + value = to_gt(i915)->ggtt->num_fences;
> break;
> case I915_PARAM_HAS_OVERLAY:
> value = !!i915->overlay;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 170bba913c30..128315aec517 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> struct drm_i915_gem_object *bo;
> struct i915_vma *vma;
> const u64 delay_ticks = 0xffffffffffffffff -
> - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
I'm not too familiar with the perf code, but this looks a bit roundabout
since we're ultimately trying to get to a GT...do we even need to go
through the ggtt structure here or can we just pass
"to_gt(stream->perf->i915)" as the first parameter?
> atomic64_read(&stream->perf->noa_programming_delay));
> const u32 base = stream->engine->mmio_base;
> #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>
> static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> {
> - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
Ditto; this looks like "to_gt(perf->i915)" might be all we need?
Matt
> 2ULL << exponent);
> }
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2021-12-21 17:01 ` [Intel-gfx] " Matt Roper
@ 2021-12-21 19:46 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-21 19:46 UTC (permalink / raw)
To: Matt Roper
Cc: Sujaritha Sundaresan, Andi Shyti, Intel GFX, Lucas De Marchi,
DRI Devel, Chris Wilson, Andi Shyti, Michał Winiarski
Hi Matt,
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > index 170bba913c30..128315aec517 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> > struct drm_i915_gem_object *bo;
> > struct i915_vma *vma;
> > const u64 delay_ticks = 0xffffffffffffffff -
> > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
>
> I'm not too familiar with the perf code, but this looks a bit roundabout
> since we're ultimately trying to get to a GT...do we even need to go
> through the ggtt structure here or can we just pass
> "to_gt(stream->perf->i915)" as the first parameter?
>
> > atomic64_read(&stream->perf->noa_programming_delay));
> > const u32 base = stream->engine->mmio_base;
> > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
> >
> > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> > {
> > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
>
> Ditto; this looks like "to_gt(perf->i915)" might be all we need?
I think this function is looking for the GT coming from the VM,
otherwise originally it could have taken it from &i915->gt. In my
first version I proposed a wrapper around this but it was
rejected by Lucas.
Besides, as we discussed earlier when I was proposed the static
allocation, the ggtt might not always be linked to the same gt,
so that I assumed that sometimes:
to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
link be?
Thanks,
Andi
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2021-12-21 19:46 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-21 19:46 UTC (permalink / raw)
To: Matt Roper
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Michał Winiarski
Hi Matt,
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > index 170bba913c30..128315aec517 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> > struct drm_i915_gem_object *bo;
> > struct i915_vma *vma;
> > const u64 delay_ticks = 0xffffffffffffffff -
> > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
>
> I'm not too familiar with the perf code, but this looks a bit roundabout
> since we're ultimately trying to get to a GT...do we even need to go
> through the ggtt structure here or can we just pass
> "to_gt(stream->perf->i915)" as the first parameter?
>
> > atomic64_read(&stream->perf->noa_programming_delay));
> > const u32 base = stream->engine->mmio_base;
> > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
> >
> > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> > {
> > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
>
> Ditto; this looks like "to_gt(perf->i915)" might be all we need?
I think this function is looking for the GT coming from the VM,
otherwise originally it could have taken it from &i915->gt. In my
first version I proposed a wrapper around this but it was
rejected by Lucas.
Besides, as we discussed earlier when I was proposed the static
allocation, the ggtt might not always be linked to the same gt,
so that I assumed that sometimes:
to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
link be?
Thanks,
Andi
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2021-12-21 19:46 ` [Intel-gfx] " Andi Shyti
@ 2022-01-03 21:17 ` Matt Roper
-1 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2022-01-03 21:17 UTC (permalink / raw)
To: Andi Shyti
Cc: Sujaritha Sundaresan, Intel GFX, Lucas De Marchi, DRI Devel,
Chris Wilson, Andi Shyti, Michał Winiarski
On Tue, Dec 21, 2021 at 09:46:29PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > > index 170bba913c30..128315aec517 100644
> > > --- a/drivers/gpu/drm/i915/i915_perf.c
> > > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > > @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> > > struct drm_i915_gem_object *bo;
> > > struct i915_vma *vma;
> > > const u64 delay_ticks = 0xffffffffffffffff -
> > > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> > > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
> >
> > I'm not too familiar with the perf code, but this looks a bit roundabout
> > since we're ultimately trying to get to a GT...do we even need to go
> > through the ggtt structure here or can we just pass
> > "to_gt(stream->perf->i915)" as the first parameter?
> >
> > > atomic64_read(&stream->perf->noa_programming_delay));
> > > const u32 base = stream->engine->mmio_base;
> > > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> > > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
> > >
> > > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> > > {
> > > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> > > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
> >
> > Ditto; this looks like "to_gt(perf->i915)" might be all we need?
>
> I think this function is looking for the GT coming from the VM,
> otherwise originally it could have taken it from &i915->gt. In my
> first version I proposed a wrapper around this but it was
> rejected by Lucas.
>
> Besides, as we discussed earlier when I was proposed the static
> allocation, the ggtt might not always be linked to the same gt,
> so that I assumed that sometimes:
>
> to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
>
> if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
> link be?
From the git history, it doesn't look like this really needs to care
about the GGTT at all; I think it was just unintentionally written in a
roundabout manner when intel_gt was first being introduced in the code.
The reference here first showed up in commit f170523a7b8e ("drm/i915/gt:
Consolidate the CS timestamp clocks").
Actually the most correct thing to do is probably to use
'stream->engine->gt' to ensure we grab the GT actually associated with
the stream's engine.
Matt
>
> Thanks,
> Andi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2022-01-03 21:17 ` Matt Roper
0 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2022-01-03 21:17 UTC (permalink / raw)
To: Andi Shyti
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Michał Winiarski
On Tue, Dec 21, 2021 at 09:46:29PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > > index 170bba913c30..128315aec517 100644
> > > --- a/drivers/gpu/drm/i915/i915_perf.c
> > > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > > @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> > > struct drm_i915_gem_object *bo;
> > > struct i915_vma *vma;
> > > const u64 delay_ticks = 0xffffffffffffffff -
> > > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> > > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
> >
> > I'm not too familiar with the perf code, but this looks a bit roundabout
> > since we're ultimately trying to get to a GT...do we even need to go
> > through the ggtt structure here or can we just pass
> > "to_gt(stream->perf->i915)" as the first parameter?
> >
> > > atomic64_read(&stream->perf->noa_programming_delay));
> > > const u32 base = stream->engine->mmio_base;
> > > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> > > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
> > >
> > > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> > > {
> > > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> > > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
> >
> > Ditto; this looks like "to_gt(perf->i915)" might be all we need?
>
> I think this function is looking for the GT coming from the VM,
> otherwise originally it could have taken it from &i915->gt. In my
> first version I proposed a wrapper around this but it was
> rejected by Lucas.
>
> Besides, as we discussed earlier when I was proposed the static
> allocation, the ggtt might not always be linked to the same gt,
> so that I assumed that sometimes:
>
> to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
>
> if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
> link be?
From the git history, it doesn't look like this really needs to care
about the GGTT at all; I think it was just unintentionally written in a
roundabout manner when intel_gt was first being introduced in the code.
The reference here first showed up in commit f170523a7b8e ("drm/i915/gt:
Consolidate the CS timestamp clocks").
Actually the most correct thing to do is probably to use
'stream->engine->gt' to ensure we grab the GT actually associated with
the stream's engine.
Matt
>
> Thanks,
> Andi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2022-01-03 21:17 ` [Intel-gfx] " Matt Roper
@ 2022-01-04 17:52 ` Umesh Nerlige Ramappa
-1 siblings, 0 replies; 48+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-01-04 17:52 UTC (permalink / raw)
To: Matt Roper
Cc: Sujaritha Sundaresan, Andi Shyti, Intel GFX, Lucas De Marchi,
DRI Devel, Chris Wilson, Andi Shyti, Michał Winiarski
On Mon, Jan 03, 2022 at 01:17:10PM -0800, Matt Roper wrote:
>On Tue, Dec 21, 2021 at 09:46:29PM +0200, Andi Shyti wrote:
>> Hi Matt,
>>
>> > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> > > index 170bba913c30..128315aec517 100644
>> > > --- a/drivers/gpu/drm/i915/i915_perf.c
>> > > +++ b/drivers/gpu/drm/i915/i915_perf.c
>> > > @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>> > > struct drm_i915_gem_object *bo;
>> > > struct i915_vma *vma;
>> > > const u64 delay_ticks = 0xffffffffffffffff -
>> > > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
>> > > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
>> >
>> > I'm not too familiar with the perf code, but this looks a bit roundabout
>> > since we're ultimately trying to get to a GT...do we even need to go
>> > through the ggtt structure here or can we just pass
>> > "to_gt(stream->perf->i915)" as the first parameter?
>> >
>> > > atomic64_read(&stream->perf->noa_programming_delay));
>> > > const u32 base = stream->engine->mmio_base;
>> > > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
>> > > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>> > >
>> > > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
>> > > {
>> > > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
>> > > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
>> >
>> > Ditto; this looks like "to_gt(perf->i915)" might be all we need?
>>
>> I think this function is looking for the GT coming from the VM,
>> otherwise originally it could have taken it from &i915->gt. In my
>> first version I proposed a wrapper around this but it was
>> rejected by Lucas.
>>
>> Besides, as we discussed earlier when I was proposed the static
>> allocation, the ggtt might not always be linked to the same gt,
>> so that I assumed that sometimes:
>>
>> to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
>>
>> if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
>> link be?
>
>From the git history, it doesn't look like this really needs to care
>about the GGTT at all; I think it was just unintentionally written in a
>roundabout manner when intel_gt was first being introduced in the code.
>The reference here first showed up in commit f170523a7b8e ("drm/i915/gt:
>Consolidate the CS timestamp clocks").
>
>Actually the most correct thing to do is probably to use
>'stream->engine->gt' to ensure we grab the GT actually associated with
>the stream's engine.
>
stream is not yet created at this point, so I would do this:
pass intel_gt to the helper instead of perf:
static u64 oa_exponent_to_ns(struct intel_gt *gt, int exponent)
{
return intel_gt_clock_interval_to_ns(gt, 2ULL << exponent);
}
caller would then be:
oa_period = oa_exponent_to_ns(props->engine->gt, value);
Thanks,
Umesh
>
>Matt
>
>
>>
>> Thanks,
>> Andi
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2022-01-04 17:52 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 48+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-01-04 17:52 UTC (permalink / raw)
To: Matt Roper
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Michał Winiarski
On Mon, Jan 03, 2022 at 01:17:10PM -0800, Matt Roper wrote:
>On Tue, Dec 21, 2021 at 09:46:29PM +0200, Andi Shyti wrote:
>> Hi Matt,
>>
>> > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> > > index 170bba913c30..128315aec517 100644
>> > > --- a/drivers/gpu/drm/i915/i915_perf.c
>> > > +++ b/drivers/gpu/drm/i915/i915_perf.c
>> > > @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>> > > struct drm_i915_gem_object *bo;
>> > > struct i915_vma *vma;
>> > > const u64 delay_ticks = 0xffffffffffffffff -
>> > > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
>> > > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
>> >
>> > I'm not too familiar with the perf code, but this looks a bit roundabout
>> > since we're ultimately trying to get to a GT...do we even need to go
>> > through the ggtt structure here or can we just pass
>> > "to_gt(stream->perf->i915)" as the first parameter?
>> >
>> > > atomic64_read(&stream->perf->noa_programming_delay));
>> > > const u32 base = stream->engine->mmio_base;
>> > > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
>> > > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>> > >
>> > > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
>> > > {
>> > > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
>> > > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
>> >
>> > Ditto; this looks like "to_gt(perf->i915)" might be all we need?
>>
>> I think this function is looking for the GT coming from the VM,
>> otherwise originally it could have taken it from &i915->gt. In my
>> first version I proposed a wrapper around this but it was
>> rejected by Lucas.
>>
>> Besides, as we discussed earlier when I was proposed the static
>> allocation, the ggtt might not always be linked to the same gt,
>> so that I assumed that sometimes:
>>
>> to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
>>
>> if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
>> link be?
>
>From the git history, it doesn't look like this really needs to care
>about the GGTT at all; I think it was just unintentionally written in a
>roundabout manner when intel_gt was first being introduced in the code.
>The reference here first showed up in commit f170523a7b8e ("drm/i915/gt:
>Consolidate the CS timestamp clocks").
>
>Actually the most correct thing to do is probably to use
>'stream->engine->gt' to ensure we grab the GT actually associated with
>the stream's engine.
>
stream is not yet created at this point, so I would do this:
pass intel_gt to the helper instead of perf:
static u64 oa_exponent_to_ns(struct intel_gt *gt, int exponent)
{
return intel_gt_clock_interval_to_ns(gt, 2ULL << exponent);
}
caller would then be:
oa_period = oa_exponent_to_ns(props->engine->gt, value);
Thanks,
Umesh
>
>Matt
>
>
>>
>> Thanks,
>> Andi
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2022-01-04 17:52 ` [Intel-gfx] " Umesh Nerlige Ramappa
@ 2022-01-04 22:27 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2022-01-04 22:27 UTC (permalink / raw)
To: Umesh Nerlige Ramappa
Cc: Sujaritha Sundaresan, Andi Shyti, Intel GFX, Lucas De Marchi,
DRI Devel, Chris Wilson, Andi Shyti, Michał Winiarski
Hi guys,
> > > > > struct drm_i915_gem_object *bo;
> > > > > struct i915_vma *vma;
> > > > > const u64 delay_ticks = 0xffffffffffffffff -
> > > > > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> > > > > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
> > > >
> > > > I'm not too familiar with the perf code, but this looks a bit roundabout
> > > > since we're ultimately trying to get to a GT...do we even need to go
> > > > through the ggtt structure here or can we just pass
> > > > "to_gt(stream->perf->i915)" as the first parameter?
> > > >
> > > > > atomic64_read(&stream->perf->noa_programming_delay));
> > > > > const u32 base = stream->engine->mmio_base;
> > > > > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> > > > > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
> > > > >
> > > > > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> > > > > {
> > > > > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> > > > > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
> > > >
> > > > Ditto; this looks like "to_gt(perf->i915)" might be all we need?
> > >
> > > I think this function is looking for the GT coming from the VM,
> > > otherwise originally it could have taken it from &i915->gt. In my
> > > first version I proposed a wrapper around this but it was
> > > rejected by Lucas.
> > >
> > > Besides, as we discussed earlier when I was proposed the static
> > > allocation, the ggtt might not always be linked to the same gt,
> > > so that I assumed that sometimes:
> > >
> > > to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
> > >
> > > if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
> > > link be?
> >
> > From the git history, it doesn't look like this really needs to care
> > about the GGTT at all; I think it was just unintentionally written in a
> > roundabout manner when intel_gt was first being introduced in the code.
> > The reference here first showed up in commit f170523a7b8e ("drm/i915/gt:
> > Consolidate the CS timestamp clocks").
> >
> > Actually the most correct thing to do is probably to use
> > 'stream->engine->gt' to ensure we grab the GT actually associated with
> > the stream's engine.
> >
>
> stream is not yet created at this point, so I would do this:
>
> pass intel_gt to the helper instead of perf:
> static u64 oa_exponent_to_ns(struct intel_gt *gt, int exponent)
> {
> return intel_gt_clock_interval_to_ns(gt, 2ULL << exponent);
> }
>
> caller would then be:
> oa_period = oa_exponent_to_ns(props->engine->gt, value);
thanks for the suggestions, but this is out of the scope of this
patch... I did propose a wrapper but it was rejected because it
was, indeed, out of scope.
I'm going to use to_gt(perf->i915) as Matt suggested originally,
patch is ready.
Thanks,
Andi
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v9 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2022-01-04 22:27 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2022-01-04 22:27 UTC (permalink / raw)
To: Umesh Nerlige Ramappa
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Michał Winiarski
Hi guys,
> > > > > struct drm_i915_gem_object *bo;
> > > > > struct i915_vma *vma;
> > > > > const u64 delay_ticks = 0xffffffffffffffff -
> > > > > - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> > > > > + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
> > > >
> > > > I'm not too familiar with the perf code, but this looks a bit roundabout
> > > > since we're ultimately trying to get to a GT...do we even need to go
> > > > through the ggtt structure here or can we just pass
> > > > "to_gt(stream->perf->i915)" as the first parameter?
> > > >
> > > > > atomic64_read(&stream->perf->noa_programming_delay));
> > > > > const u32 base = stream->engine->mmio_base;
> > > > > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> > > > > @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
> > > > >
> > > > > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> > > > > {
> > > > > - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> > > > > + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
> > > >
> > > > Ditto; this looks like "to_gt(perf->i915)" might be all we need?
> > >
> > > I think this function is looking for the GT coming from the VM,
> > > otherwise originally it could have taken it from &i915->gt. In my
> > > first version I proposed a wrapper around this but it was
> > > rejected by Lucas.
> > >
> > > Besides, as we discussed earlier when I was proposed the static
> > > allocation, the ggtt might not always be linked to the same gt,
> > > so that I assumed that sometimes:
> > >
> > > to_gt(perf->i915)->ggtt->vm.gt != to_gt(perf->i915)
> > >
> > > if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
> > > link be?
> >
> > From the git history, it doesn't look like this really needs to care
> > about the GGTT at all; I think it was just unintentionally written in a
> > roundabout manner when intel_gt was first being introduced in the code.
> > The reference here first showed up in commit f170523a7b8e ("drm/i915/gt:
> > Consolidate the CS timestamp clocks").
> >
> > Actually the most correct thing to do is probably to use
> > 'stream->engine->gt' to ensure we grab the GT actually associated with
> > the stream's engine.
> >
>
> stream is not yet created at this point, so I would do this:
>
> pass intel_gt to the helper instead of perf:
> static u64 oa_exponent_to_ns(struct intel_gt *gt, int exponent)
> {
> return intel_gt_clock_interval_to_ns(gt, 2ULL << exponent);
> }
>
> caller would then be:
> oa_period = oa_exponent_to_ns(props->engine->gt, value);
thanks for the suggestions, but this is out of the scope of this
patch... I did propose a wrapper but it was rejected because it
was, indeed, out of scope.
I'm going to use to_gt(perf->i915) as Matt suggested originally,
patch is ready.
Thanks,
Andi
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v10 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2021-12-21 17:01 ` [Intel-gfx] " Matt Roper
@ 2022-01-04 22:35 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2022-01-04 22:35 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
Hi Matt,
I'm sending this this v10 as reply-to, if it confuses you I can
send the whole v10.
The only trivial difference is that in i915_perf.c I'm using
to_gt(perf->i915)
instead of
to_gt(perf->i915)->ggtt->vm.gt
Andi
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 6 +++---
8 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 8e65cd8258b9..94c3eb1586b0 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
kfree(st);
return ret;
}
- gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+ gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
(fb_info->start >> PAGE_SHIFT);
for_each_sg(st->sgl, sg, page_num, i) {
dma_addr_t dma_addr =
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e0e052cdf8b8..6966fe08df92 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
intel_wakeref_t wakeref;
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
seq_puts(m, "L-shaped memory detected\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 60f8cbf24de7..3c984553d86f 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
/* Must be called before GGTT is suspended. */
intel_dpt_suspend(dev_priv);
- i915_ggtt_suspend(&dev_priv->ggtt);
+ i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
i915_save_display(dev_priv);
@@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
if (ret)
drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
/* Must be called after GGTT is resumed. */
intel_dpt_resume(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index beeb42a14aae..01518ce8f401 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1748,7 +1748,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
+ return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
i915_gem_object_is_tiled(obj);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 915bf431f320..e3730096abd9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -88,7 +88,8 @@ int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
- struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
@@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
bool write)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
struct i915_gem_ww_ctx ww;
int ret;
@@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
struct i915_vma *vma)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
i915_gem_object_unpin_pages(obj);
if (drm_mm_node_allocated(node)) {
@@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
intel_wakeref_t wakeref;
struct drm_mm_node node;
void __user *user_data;
@@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t wakeref;
struct drm_mm_node node;
@@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
*/
list_for_each_entry_safe(obj, on,
- &i915->ggtt.userfault_list, userfault_link)
+ &to_gt(i915)->ggtt->userfault_list, userfault_link)
__i915_gem_object_release_mmap_gtt(obj);
/*
@@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
* in use by hardware (i.e. they are pinned), we should not be powering
* down! All other fences will be reacquired by the user upon waking.
*/
- for (i = 0; i < i915->ggtt.num_fences; i++) {
- struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
+ for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
+ struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
/*
* Ideally we want to assert that the fence register is not
@@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
u64 size, u64 alignment, u64 flags)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
int ret;
@@ -1123,7 +1124,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
/* Minimal basic recovery for KMS */
ret = i915_ggtt_enable_hw(dev_priv);
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
intel_init_clock_gating(dev_priv);
}
@@ -1146,7 +1147,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
{
- intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
+ intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
i915_gem_suspend_late(dev_priv);
intel_gt_driver_remove(to_gt(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cd5f2348a187..2f2ba7a2955d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
/* XXX This does not prevent more requests being submitted! */
if (unlikely(ggtt->do_idle_maps))
@@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(range_overflows(offset, size, vm->total));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
node->size = size;
@@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
GEM_BUG_ON(start >= end);
GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
if (unlikely(range_overflows(start, size, end)))
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 7f80ad247bc8..5b8a2157d797 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = pdev->revision;
break;
case I915_PARAM_NUM_FENCES_AVAIL:
- value = i915->ggtt.num_fences;
+ value = to_gt(i915)->ggtt->num_fences;
break;
case I915_PARAM_HAS_OVERLAY:
value = !!i915->overlay;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 170bba913c30..298857b69180 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,8 +1630,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0xffffffffffffffff -
- intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
- atomic64_read(&stream->perf->noa_programming_delay));
+ intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
+ atomic64_read(&stream->perf->noa_programming_delay));
const u32 base = stream->engine->mmio_base;
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
u32 *batch, *ts0, *cs, *jump;
@@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
{
- return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
+ return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
2ULL << exponent);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v10 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2022-01-04 22:35 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2022-01-04 22:35 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
Hi Matt,
I'm sending this this v10 as reply-to, if it confuses you I can
send the whole v10.
The only trivial difference is that in i915_perf.c I'm using
to_gt(perf->i915)
instead of
to_gt(perf->i915)->ggtt->vm.gt
Andi
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 6 +++---
8 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 8e65cd8258b9..94c3eb1586b0 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
kfree(st);
return ret;
}
- gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+ gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
(fb_info->start >> PAGE_SHIFT);
for_each_sg(st->sgl, sg, page_num, i) {
dma_addr_t dma_addr =
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e0e052cdf8b8..6966fe08df92 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
intel_wakeref_t wakeref;
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
- swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
+ swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
seq_puts(m, "L-shaped memory detected\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 60f8cbf24de7..3c984553d86f 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
/* Must be called before GGTT is suspended. */
intel_dpt_suspend(dev_priv);
- i915_ggtt_suspend(&dev_priv->ggtt);
+ i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
i915_save_display(dev_priv);
@@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
if (ret)
drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
/* Must be called after GGTT is resumed. */
intel_dpt_resume(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index beeb42a14aae..01518ce8f401 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1748,7 +1748,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
+ return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
i915_gem_object_is_tiled(obj);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 915bf431f320..e3730096abd9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -88,7 +88,8 @@ int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
- struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
@@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
bool write)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
struct i915_gem_ww_ctx ww;
int ret;
@@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
struct i915_vma *vma)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
i915_gem_object_unpin_pages(obj);
if (drm_mm_node_allocated(node)) {
@@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
intel_wakeref_t wakeref;
struct drm_mm_node node;
void __user *user_data;
@@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *args)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t wakeref;
struct drm_mm_node node;
@@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
*/
list_for_each_entry_safe(obj, on,
- &i915->ggtt.userfault_list, userfault_link)
+ &to_gt(i915)->ggtt->userfault_list, userfault_link)
__i915_gem_object_release_mmap_gtt(obj);
/*
@@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
* in use by hardware (i.e. they are pinned), we should not be powering
* down! All other fences will be reacquired by the user upon waking.
*/
- for (i = 0; i < i915->ggtt.num_fences; i++) {
- struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
+ for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
+ struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
/*
* Ideally we want to assert that the fence register is not
@@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
u64 size, u64 alignment, u64 flags)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma;
int ret;
@@ -1123,7 +1124,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
/* Minimal basic recovery for KMS */
ret = i915_ggtt_enable_hw(dev_priv);
- i915_ggtt_resume(&dev_priv->ggtt);
+ i915_ggtt_resume(to_gt(dev_priv)->ggtt);
intel_init_clock_gating(dev_priv);
}
@@ -1146,7 +1147,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
{
- intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
+ intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
i915_gem_suspend_late(dev_priv);
intel_gt_driver_remove(to_gt(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cd5f2348a187..2f2ba7a2955d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
/* XXX This does not prevent more requests being submitted! */
if (unlikely(ggtt->do_idle_maps))
@@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(range_overflows(offset, size, vm->total));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
node->size = size;
@@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
GEM_BUG_ON(start >= end);
GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
- GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
+ GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
GEM_BUG_ON(drm_mm_node_allocated(node));
if (unlikely(range_overflows(start, size, end)))
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 7f80ad247bc8..5b8a2157d797 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = pdev->revision;
break;
case I915_PARAM_NUM_FENCES_AVAIL:
- value = i915->ggtt.num_fences;
+ value = to_gt(i915)->ggtt->num_fences;
break;
case I915_PARAM_HAS_OVERLAY:
value = !!i915->overlay;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 170bba913c30..298857b69180 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,8 +1630,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0xffffffffffffffff -
- intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
- atomic64_read(&stream->perf->noa_programming_delay));
+ intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
+ atomic64_read(&stream->perf->noa_programming_delay));
const u32 base = stream->engine->mmio_base;
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
u32 *batch, *ts0, *cs, *jump;
@@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
{
- return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
+ return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
2ULL << exponent);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH v10 2/6] drm/i915: Use to_gt() helper for GGTT accesses
2022-01-04 22:35 ` [Intel-gfx] " Andi Shyti
@ 2022-01-05 5:31 ` Matt Roper
-1 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2022-01-05 5:31 UTC (permalink / raw)
To: Andi Shyti
Cc: Sujaritha Sundaresan, Intel GFX, Lucas De Marchi, DRI Devel,
Chris Wilson, Andi Shyti, Michał Winiarski
On Wed, Jan 05, 2022 at 12:35:50AM +0200, Andi Shyti wrote:
> From: Michał Winiarski <michal.winiarski@intel.com>
>
> GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> eventually want to get rid of the i915->ggtt one.
> Use to_gt() for all i915->ggtt accesses to help with the future
> refactoring.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> Hi Matt,
>
> I'm sending this this v10 as reply-to, if it confuses you I can
> send the whole v10.
>
> The only trivial difference is that in i915_perf.c I'm using
>
> to_gt(perf->i915)
>
> instead of
>
> to_gt(perf->i915)->ggtt->vm.gt
>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Andi
>
> drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
> drivers/gpu/drm/i915/i915_getparam.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 6 +++---
> 8 files changed, 25 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
> index 8e65cd8258b9..94c3eb1586b0 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.c
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
> @@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
> kfree(st);
> return ret;
> }
> - gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
> + gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
> (fb_info->start >> PAGE_SHIFT);
> for_each_sg(st->sgl, sg, page_num, i) {
> dma_addr_t dma_addr =
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e0e052cdf8b8..6966fe08df92 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> intel_wakeref_t wakeref;
>
> seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
> seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
>
> if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
> seq_puts(m, "L-shaped memory detected\n");
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 60f8cbf24de7..3c984553d86f 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> /* Must be called before GGTT is suspended. */
> intel_dpt_suspend(dev_priv);
> - i915_ggtt_suspend(&dev_priv->ggtt);
> + i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
>
> i915_save_display(dev_priv);
>
> @@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
> if (ret)
> drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
>
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> /* Must be called after GGTT is resumed. */
> intel_dpt_resume(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index beeb42a14aae..01518ce8f401 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1748,7 +1748,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
>
> - return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> + return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> i915_gem_object_is_tiled(obj);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 915bf431f320..e3730096abd9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -88,7 +88,8 @@ int
> i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> - struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct drm_i915_gem_get_aperture *args = data;
> struct i915_vma *vma;
> u64 pinned;
> @@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
> bool write)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> struct i915_gem_ww_ctx ww;
> int ret;
> @@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
> struct i915_vma *vma)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> i915_gem_object_unpin_pages(obj);
> if (drm_mm_node_allocated(node)) {
> @@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pread *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> void __user *user_data;
> @@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pwrite *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct intel_runtime_pm *rpm = &i915->runtime_pm;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> @@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> */
>
> list_for_each_entry_safe(obj, on,
> - &i915->ggtt.userfault_list, userfault_link)
> + &to_gt(i915)->ggtt->userfault_list, userfault_link)
> __i915_gem_object_release_mmap_gtt(obj);
>
> /*
> @@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> * in use by hardware (i.e. they are pinned), we should not be powering
> * down! All other fences will be reacquired by the user upon waking.
> */
> - for (i = 0; i < i915->ggtt.num_fences; i++) {
> - struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
> + for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
> + struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
>
> /*
> * Ideally we want to assert that the fence register is not
> @@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
> u64 size, u64 alignment, u64 flags)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> int ret;
>
> @@ -1123,7 +1124,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>
> /* Minimal basic recovery for KMS */
> ret = i915_ggtt_enable_hw(dev_priv);
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> intel_init_clock_gating(dev_priv);
> }
>
> @@ -1146,7 +1147,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
>
> void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
> {
> - intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
> + intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
>
> i915_gem_suspend_late(dev_priv);
> intel_gt_driver_remove(to_gt(dev_priv));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cd5f2348a187..2f2ba7a2955d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
> struct sg_table *pages)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> /* XXX This does not prevent more requests being submitted! */
> if (unlikely(ggtt->do_idle_maps))
> @@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
> GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
> GEM_BUG_ON(range_overflows(offset, size, vm->total));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> node->size = size;
> @@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
> GEM_BUG_ON(start >= end);
> GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> if (unlikely(range_overflows(start, size, end)))
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 7f80ad247bc8..5b8a2157d797 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = pdev->revision;
> break;
> case I915_PARAM_NUM_FENCES_AVAIL:
> - value = i915->ggtt.num_fences;
> + value = to_gt(i915)->ggtt->num_fences;
> break;
> case I915_PARAM_HAS_OVERLAY:
> value = !!i915->overlay;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 170bba913c30..298857b69180 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1630,8 +1630,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> struct drm_i915_gem_object *bo;
> struct i915_vma *vma;
> const u64 delay_ticks = 0xffffffffffffffff -
> - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> - atomic64_read(&stream->perf->noa_programming_delay));
> + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
> + atomic64_read(&stream->perf->noa_programming_delay));
> const u32 base = stream->engine->mmio_base;
> #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> u32 *batch, *ts0, *cs, *jump;
> @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>
> static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> {
> - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> + return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
> 2ULL << exponent);
> }
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v10 2/6] drm/i915: Use to_gt() helper for GGTT accesses
@ 2022-01-05 5:31 ` Matt Roper
0 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2022-01-05 5:31 UTC (permalink / raw)
To: Andi Shyti
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Michał Winiarski
On Wed, Jan 05, 2022 at 12:35:50AM +0200, Andi Shyti wrote:
> From: Michał Winiarski <michal.winiarski@intel.com>
>
> GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> eventually want to get rid of the i915->ggtt one.
> Use to_gt() for all i915->ggtt accesses to help with the future
> refactoring.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> Hi Matt,
>
> I'm sending this this v10 as reply-to, if it confuses you I can
> send the whole v10.
>
> The only trivial difference is that in i915_perf.c I'm using
>
> to_gt(perf->i915)
>
> instead of
>
> to_gt(perf->i915)->ggtt->vm.gt
>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Andi
>
> drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++++++-----------
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
> drivers/gpu/drm/i915/i915_getparam.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 6 +++---
> 8 files changed, 25 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
> index 8e65cd8258b9..94c3eb1586b0 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.c
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
> @@ -84,7 +84,7 @@ static int vgpu_gem_get_pages(
> kfree(st);
> return ret;
> }
> - gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
> + gtt_entries = (gen8_pte_t __iomem *)to_gt(dev_priv)->ggtt->gsm +
> (fb_info->start >> PAGE_SHIFT);
> for_each_sg(st->sgl, sg, page_num, i) {
> dma_addr_t dma_addr =
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e0e052cdf8b8..6966fe08df92 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -390,9 +390,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> intel_wakeref_t wakeref;
>
> seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
> seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> - swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
> + swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
>
> if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
> seq_puts(m, "L-shaped memory detected\n");
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 60f8cbf24de7..3c984553d86f 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1146,7 +1146,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> /* Must be called before GGTT is suspended. */
> intel_dpt_suspend(dev_priv);
> - i915_ggtt_suspend(&dev_priv->ggtt);
> + i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
>
> i915_save_display(dev_priv);
>
> @@ -1270,7 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
> if (ret)
> drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
>
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> /* Must be called after GGTT is resumed. */
> intel_dpt_resume(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index beeb42a14aae..01518ce8f401 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1748,7 +1748,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
>
> - return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> + return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
> i915_gem_object_is_tiled(obj);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 915bf431f320..e3730096abd9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -88,7 +88,8 @@ int
> i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> - struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct drm_i915_gem_get_aperture *args = data;
> struct i915_vma *vma;
> u64 pinned;
> @@ -289,7 +290,7 @@ static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
> bool write)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> struct i915_gem_ww_ctx ww;
> int ret;
> @@ -350,7 +351,7 @@ static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
> struct i915_vma *vma)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> i915_gem_object_unpin_pages(obj);
> if (drm_mm_node_allocated(node)) {
> @@ -366,7 +367,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pread *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> void __user *user_data;
> @@ -522,7 +523,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pwrite *args)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct intel_runtime_pm *rpm = &i915->runtime_pm;
> intel_wakeref_t wakeref;
> struct drm_mm_node node;
> @@ -823,7 +824,7 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> */
>
> list_for_each_entry_safe(obj, on,
> - &i915->ggtt.userfault_list, userfault_link)
> + &to_gt(i915)->ggtt->userfault_list, userfault_link)
> __i915_gem_object_release_mmap_gtt(obj);
>
> /*
> @@ -831,8 +832,8 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915)
> * in use by hardware (i.e. they are pinned), we should not be powering
> * down! All other fences will be reacquired by the user upon waking.
> */
> - for (i = 0; i < i915->ggtt.num_fences; i++) {
> - struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
> + for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
> + struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
>
> /*
> * Ideally we want to assert that the fence register is not
> @@ -873,7 +874,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
> u64 size, u64 alignment, u64 flags)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct i915_vma *vma;
> int ret;
>
> @@ -1123,7 +1124,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>
> /* Minimal basic recovery for KMS */
> ret = i915_ggtt_enable_hw(dev_priv);
> - i915_ggtt_resume(&dev_priv->ggtt);
> + i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> intel_init_clock_gating(dev_priv);
> }
>
> @@ -1146,7 +1147,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915)
>
> void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
> {
> - intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
> + intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
>
> i915_gem_suspend_late(dev_priv);
> intel_gt_driver_remove(to_gt(dev_priv));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cd5f2348a187..2f2ba7a2955d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -56,7 +56,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
> struct sg_table *pages)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
>
> /* XXX This does not prevent more requests being submitted! */
> if (unlikely(ggtt->do_idle_maps))
> @@ -103,7 +103,7 @@ int i915_gem_gtt_reserve(struct i915_address_space *vm,
> GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
> GEM_BUG_ON(range_overflows(offset, size, vm->total));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> node->size = size;
> @@ -201,7 +201,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
> GEM_BUG_ON(start >= end);
> GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> - GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> + GEM_BUG_ON(vm == &to_gt(vm->i915)->ggtt->alias->vm);
> GEM_BUG_ON(drm_mm_node_allocated(node));
>
> if (unlikely(range_overflows(start, size, end)))
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 7f80ad247bc8..5b8a2157d797 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -31,7 +31,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = pdev->revision;
> break;
> case I915_PARAM_NUM_FENCES_AVAIL:
> - value = i915->ggtt.num_fences;
> + value = to_gt(i915)->ggtt->num_fences;
> break;
> case I915_PARAM_HAS_OVERLAY:
> value = !!i915->overlay;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 170bba913c30..298857b69180 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1630,8 +1630,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> struct drm_i915_gem_object *bo;
> struct i915_vma *vma;
> const u64 delay_ticks = 0xffffffffffffffff -
> - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> - atomic64_read(&stream->perf->noa_programming_delay));
> + intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
> + atomic64_read(&stream->perf->noa_programming_delay));
> const u32 base = stream->engine->mmio_base;
> #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> u32 *batch, *ts0, *cs, *jump;
> @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>
> static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> {
> - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> + return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
> 2ULL << exponent);
> }
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v9 3/6] drm/i915/gem: Use to_gt() helper for GGTT accesses
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-19 21:24 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 19 ++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8 +++++---
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 15 ++++++++-------
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c | 19 ++++++++++---------
.../drm/i915/gem/selftests/i915_gem_object.c | 2 +-
11 files changed, 42 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index babfecb17ad1..e5b0f66ea1fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -174,7 +174,7 @@ i915_gem_context_get_eb_vm(struct i915_gem_context *ctx)
vm = ctx->vm;
if (!vm)
- vm = &ctx->i915->ggtt.vm;
+ vm = &to_gt(ctx->i915)->ggtt->vm;
vm = i915_vm_get(vm);
return vm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ec7c4a29a720..3078611d5bfe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1106,7 +1106,7 @@ static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
{
struct drm_i915_private *i915 =
container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
- return &i915->ggtt;
+ return to_gt(i915)->ggtt;
}
static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index aaf970c37aa2..ee5ec0fd4807 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -295,7 +295,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_runtime_pm *rpm = &i915->runtime_pm;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
bool write = area->vm_flags & VM_WRITE;
struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
@@ -388,16 +388,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
assert_rpm_wakelock_held(rpm);
/* Mark as being mmapped into userspace for later revocation */
- mutex_lock(&i915->ggtt.vm.mutex);
+ mutex_lock(&to_gt(i915)->ggtt->vm.mutex);
if (!i915_vma_set_userfault(vma) && !obj->userfault_count++)
- list_add(&obj->userfault_link, &i915->ggtt.userfault_list);
- mutex_unlock(&i915->ggtt.vm.mutex);
+ list_add(&obj->userfault_link, &to_gt(i915)->ggtt->userfault_list);
+ mutex_unlock(&to_gt(i915)->ggtt->vm.mutex);
/* Track the mmo associated with the fenced vma */
vma->mmo = mmo;
if (CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND)
- intel_wakeref_auto(&i915->ggtt.userfault_wakeref,
+ intel_wakeref_auto(&to_gt(i915)->ggtt->userfault_wakeref,
msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND));
if (write) {
@@ -512,7 +512,7 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj)
* wakeref.
*/
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
- mutex_lock(&i915->ggtt.vm.mutex);
+ mutex_lock(&to_gt(i915)->ggtt->vm.mutex);
if (!obj->userfault_count)
goto out;
@@ -530,7 +530,7 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj)
wmb();
out:
- mutex_unlock(&i915->ggtt.vm.mutex);
+ mutex_unlock(&to_gt(i915)->ggtt->vm.mutex);
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
}
@@ -733,13 +733,14 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
u32 handle,
u64 *offset)
{
+ struct drm_i915_private *i915 = to_i915(dev);
enum i915_mmap_type mmap_type;
if (HAS_LMEM(to_i915(dev)))
mmap_type = I915_MMAP_TYPE_FIXED;
else if (pat_enabled())
mmap_type = I915_MMAP_TYPE_WC;
- else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
+ else if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return -ENODEV;
else
mmap_type = I915_MMAP_TYPE_GTT;
@@ -787,7 +788,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
switch (args->flags) {
case I915_MMAP_OFFSET_GTT:
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return -ENODEV;
type = I915_MMAP_TYPE_GTT;
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index ac56124760e1..6da68b38f00f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -23,7 +23,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
{
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
- intel_wakeref_auto(&i915->ggtt.userfault_wakeref, 0);
+ intel_wakeref_auto(&to_gt(i915)->ggtt->userfault_wakeref, 0);
flush_workqueue(i915->wq);
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 05a1ba2f2e7b..793fbf3da46b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -403,9 +403,9 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
I915_SHRINK_VMAPS);
/* We also want to clear any cached iomaps as they wrap vmap */
- mutex_lock(&i915->ggtt.vm.mutex);
+ mutex_lock(&to_gt(i915)->ggtt->vm.mutex);
list_for_each_entry_safe(vma, next,
- &i915->ggtt.vm.bound_list, vm_link) {
+ &to_gt(i915)->ggtt->vm.bound_list, vm_link) {
unsigned long count = vma->node.size >> PAGE_SHIFT;
if (!vma->iomap || i915_vma_is_active(vma))
@@ -414,7 +414,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
if (__i915_vma_unbind(vma) == 0)
freed_pages += count;
}
- mutex_unlock(&i915->ggtt.vm.mutex);
+ mutex_unlock(&to_gt(i915)->ggtt->vm.mutex);
*(unsigned long *)ptr += freed_pages;
return NOTIFY_DONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ad7a8e9e13e7..ef524817ad7e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -71,7 +71,7 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
static int i915_adjust_stolen(struct drm_i915_private *i915,
struct resource *dsm)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct resource *r;
@@ -582,6 +582,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct sg_table *pages =
i915_pages_create_for_stolen(obj->base.dev,
obj->stolen->start,
@@ -589,7 +590,7 @@ static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
if (IS_ERR(pages))
return PTR_ERR(pages);
- dbg_poison(&to_i915(obj->base.dev)->ggtt,
+ dbg_poison(to_gt(i915)->ggtt,
sg_dma_address(pages->sgl),
sg_dma_len(pages->sgl),
POISON_INUSE);
@@ -602,9 +603,10 @@ static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
/* Should only be called from i915_gem_object_release_stolen() */
- dbg_poison(&to_i915(obj->base.dev)->ggtt,
+ dbg_poison(to_gt(i915)->ggtt,
sg_dma_address(pages->sgl),
sg_dma_len(pages->sgl),
POISON_FREE);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ef4d0f7dc118..c3d432e314c9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -181,7 +181,8 @@ static int
i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
int tiling_mode, unsigned int stride)
{
- struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma, *vn;
LIST_HEAD(unbind);
int ret = 0;
@@ -336,7 +337,7 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *obj;
int err;
- if (!dev_priv->ggtt.num_fences)
+ if (!to_gt(dev_priv)->ggtt->num_fences)
return -EOPNOTSUPP;
obj = i915_gem_object_lookup(file, args->handle);
@@ -362,9 +363,9 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
args->stride = 0;
} else {
if (args->tiling_mode == I915_TILING_X)
- args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_x;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_x;
else
- args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_y;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_y;
/* Hide bit 17 swizzling from the user. This prevents old Mesa
* from aborting the application on sw fallbacks to bit 17,
@@ -419,7 +420,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *obj;
int err = -ENOENT;
- if (!dev_priv->ggtt.num_fences)
+ if (!to_gt(dev_priv)->ggtt->num_fences)
return -EOPNOTSUPP;
rcu_read_lock();
@@ -435,10 +436,10 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
switch (args->tiling_mode) {
case I915_TILING_X:
- args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_x;
break;
case I915_TILING_Y:
- args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_y;
break;
default:
case I915_TILING_NONE:
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 75947e9dada2..c08f766e6e15 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -543,7 +543,7 @@ static bool has_bit17_swizzle(int sw)
static bool bad_swizzling(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 45398adda9c8..250fe3ba6def 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1374,7 +1374,7 @@ static int igt_ctx_readonly(void *arg)
goto out_file;
}
- vm = ctx->vm ?: &i915->ggtt.alias->vm;
+ vm = ctx->vm ?: &to_gt(i915)->ggtt->alias->vm;
if (!vm || !vm->has_read_only) {
err = 0;
goto out_file;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 743e6ab2c40b..743a098facf2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -307,7 +307,7 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
/* We want to check the page mapping and fencing of a large object
@@ -320,7 +320,7 @@ static int igt_partial_tiling(void *arg)
obj = huge_gem_object(i915,
nreal << PAGE_SHIFT,
- (1 + next_prime_number(i915->ggtt.vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
if (IS_ERR(obj))
return PTR_ERR(obj);
@@ -366,10 +366,10 @@ static int igt_partial_tiling(void *arg)
tile.tiling = tiling;
switch (tiling) {
case I915_TILING_X:
- tile.swizzle = i915->ggtt.bit_6_swizzle_x;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
break;
case I915_TILING_Y:
- tile.swizzle = i915->ggtt.bit_6_swizzle_y;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
break;
}
@@ -440,7 +440,7 @@ static int igt_smoke_tiling(void *arg)
IGT_TIMEOUT(end);
int err;
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
/*
@@ -457,7 +457,7 @@ static int igt_smoke_tiling(void *arg)
obj = huge_gem_object(i915,
nreal << PAGE_SHIFT,
- (1 + next_prime_number(i915->ggtt.vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
if (IS_ERR(obj))
return PTR_ERR(obj);
@@ -486,10 +486,10 @@ static int igt_smoke_tiling(void *arg)
break;
case I915_TILING_X:
- tile.swizzle = i915->ggtt.bit_6_swizzle_x;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
break;
case I915_TILING_Y:
- tile.swizzle = i915->ggtt.bit_6_swizzle_y;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
break;
}
@@ -856,6 +856,7 @@ static int wc_check(struct drm_i915_gem_object *obj)
static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
bool no_map;
if (obj->ops->mmap_offset)
@@ -864,7 +865,7 @@ static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
return false;
if (type == I915_MMAP_TYPE_GTT &&
- !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
+ !i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return false;
i915_gem_object_lock(obj, NULL);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
index 740ee8086a27..fe0a890775e2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
@@ -43,7 +43,7 @@ static int igt_gem_huge(void *arg)
obj = huge_gem_object(i915,
nreal * PAGE_SIZE,
- i915->ggtt.vm.total + PAGE_SIZE);
+ to_gt(i915)->ggtt->vm.total + PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v9 3/6] drm/i915/gem: Use to_gt() helper for GGTT accesses
@ 2021-12-19 21:24 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 19 ++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8 +++++---
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 15 ++++++++-------
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c | 19 ++++++++++---------
.../drm/i915/gem/selftests/i915_gem_object.c | 2 +-
11 files changed, 42 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index babfecb17ad1..e5b0f66ea1fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -174,7 +174,7 @@ i915_gem_context_get_eb_vm(struct i915_gem_context *ctx)
vm = ctx->vm;
if (!vm)
- vm = &ctx->i915->ggtt.vm;
+ vm = &to_gt(ctx->i915)->ggtt->vm;
vm = i915_vm_get(vm);
return vm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ec7c4a29a720..3078611d5bfe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1106,7 +1106,7 @@ static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
{
struct drm_i915_private *i915 =
container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
- return &i915->ggtt;
+ return to_gt(i915)->ggtt;
}
static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index aaf970c37aa2..ee5ec0fd4807 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -295,7 +295,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_runtime_pm *rpm = &i915->runtime_pm;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
bool write = area->vm_flags & VM_WRITE;
struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
@@ -388,16 +388,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
assert_rpm_wakelock_held(rpm);
/* Mark as being mmapped into userspace for later revocation */
- mutex_lock(&i915->ggtt.vm.mutex);
+ mutex_lock(&to_gt(i915)->ggtt->vm.mutex);
if (!i915_vma_set_userfault(vma) && !obj->userfault_count++)
- list_add(&obj->userfault_link, &i915->ggtt.userfault_list);
- mutex_unlock(&i915->ggtt.vm.mutex);
+ list_add(&obj->userfault_link, &to_gt(i915)->ggtt->userfault_list);
+ mutex_unlock(&to_gt(i915)->ggtt->vm.mutex);
/* Track the mmo associated with the fenced vma */
vma->mmo = mmo;
if (CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND)
- intel_wakeref_auto(&i915->ggtt.userfault_wakeref,
+ intel_wakeref_auto(&to_gt(i915)->ggtt->userfault_wakeref,
msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND));
if (write) {
@@ -512,7 +512,7 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj)
* wakeref.
*/
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
- mutex_lock(&i915->ggtt.vm.mutex);
+ mutex_lock(&to_gt(i915)->ggtt->vm.mutex);
if (!obj->userfault_count)
goto out;
@@ -530,7 +530,7 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj)
wmb();
out:
- mutex_unlock(&i915->ggtt.vm.mutex);
+ mutex_unlock(&to_gt(i915)->ggtt->vm.mutex);
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
}
@@ -733,13 +733,14 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
u32 handle,
u64 *offset)
{
+ struct drm_i915_private *i915 = to_i915(dev);
enum i915_mmap_type mmap_type;
if (HAS_LMEM(to_i915(dev)))
mmap_type = I915_MMAP_TYPE_FIXED;
else if (pat_enabled())
mmap_type = I915_MMAP_TYPE_WC;
- else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
+ else if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return -ENODEV;
else
mmap_type = I915_MMAP_TYPE_GTT;
@@ -787,7 +788,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
switch (args->flags) {
case I915_MMAP_OFFSET_GTT:
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return -ENODEV;
type = I915_MMAP_TYPE_GTT;
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index ac56124760e1..6da68b38f00f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -23,7 +23,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
{
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
- intel_wakeref_auto(&i915->ggtt.userfault_wakeref, 0);
+ intel_wakeref_auto(&to_gt(i915)->ggtt->userfault_wakeref, 0);
flush_workqueue(i915->wq);
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 05a1ba2f2e7b..793fbf3da46b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -403,9 +403,9 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
I915_SHRINK_VMAPS);
/* We also want to clear any cached iomaps as they wrap vmap */
- mutex_lock(&i915->ggtt.vm.mutex);
+ mutex_lock(&to_gt(i915)->ggtt->vm.mutex);
list_for_each_entry_safe(vma, next,
- &i915->ggtt.vm.bound_list, vm_link) {
+ &to_gt(i915)->ggtt->vm.bound_list, vm_link) {
unsigned long count = vma->node.size >> PAGE_SHIFT;
if (!vma->iomap || i915_vma_is_active(vma))
@@ -414,7 +414,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
if (__i915_vma_unbind(vma) == 0)
freed_pages += count;
}
- mutex_unlock(&i915->ggtt.vm.mutex);
+ mutex_unlock(&to_gt(i915)->ggtt->vm.mutex);
*(unsigned long *)ptr += freed_pages;
return NOTIFY_DONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ad7a8e9e13e7..ef524817ad7e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -71,7 +71,7 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
static int i915_adjust_stolen(struct drm_i915_private *i915,
struct resource *dsm)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct resource *r;
@@ -582,6 +582,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct sg_table *pages =
i915_pages_create_for_stolen(obj->base.dev,
obj->stolen->start,
@@ -589,7 +590,7 @@ static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
if (IS_ERR(pages))
return PTR_ERR(pages);
- dbg_poison(&to_i915(obj->base.dev)->ggtt,
+ dbg_poison(to_gt(i915)->ggtt,
sg_dma_address(pages->sgl),
sg_dma_len(pages->sgl),
POISON_INUSE);
@@ -602,9 +603,10 @@ static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
/* Should only be called from i915_gem_object_release_stolen() */
- dbg_poison(&to_i915(obj->base.dev)->ggtt,
+ dbg_poison(to_gt(i915)->ggtt,
sg_dma_address(pages->sgl),
sg_dma_len(pages->sgl),
POISON_FREE);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ef4d0f7dc118..c3d432e314c9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -181,7 +181,8 @@ static int
i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
int tiling_mode, unsigned int stride)
{
- struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct i915_vma *vma, *vn;
LIST_HEAD(unbind);
int ret = 0;
@@ -336,7 +337,7 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *obj;
int err;
- if (!dev_priv->ggtt.num_fences)
+ if (!to_gt(dev_priv)->ggtt->num_fences)
return -EOPNOTSUPP;
obj = i915_gem_object_lookup(file, args->handle);
@@ -362,9 +363,9 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
args->stride = 0;
} else {
if (args->tiling_mode == I915_TILING_X)
- args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_x;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_x;
else
- args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_y;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_y;
/* Hide bit 17 swizzling from the user. This prevents old Mesa
* from aborting the application on sw fallbacks to bit 17,
@@ -419,7 +420,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *obj;
int err = -ENOENT;
- if (!dev_priv->ggtt.num_fences)
+ if (!to_gt(dev_priv)->ggtt->num_fences)
return -EOPNOTSUPP;
rcu_read_lock();
@@ -435,10 +436,10 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
switch (args->tiling_mode) {
case I915_TILING_X:
- args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_x;
break;
case I915_TILING_Y:
- args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
+ args->swizzle_mode = to_gt(dev_priv)->ggtt->bit_6_swizzle_y;
break;
default:
case I915_TILING_NONE:
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 75947e9dada2..c08f766e6e15 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -543,7 +543,7 @@ static bool has_bit17_swizzle(int sw)
static bool bad_swizzling(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 45398adda9c8..250fe3ba6def 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1374,7 +1374,7 @@ static int igt_ctx_readonly(void *arg)
goto out_file;
}
- vm = ctx->vm ?: &i915->ggtt.alias->vm;
+ vm = ctx->vm ?: &to_gt(i915)->ggtt->alias->vm;
if (!vm || !vm->has_read_only) {
err = 0;
goto out_file;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 743e6ab2c40b..743a098facf2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -307,7 +307,7 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
/* We want to check the page mapping and fencing of a large object
@@ -320,7 +320,7 @@ static int igt_partial_tiling(void *arg)
obj = huge_gem_object(i915,
nreal << PAGE_SHIFT,
- (1 + next_prime_number(i915->ggtt.vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
if (IS_ERR(obj))
return PTR_ERR(obj);
@@ -366,10 +366,10 @@ static int igt_partial_tiling(void *arg)
tile.tiling = tiling;
switch (tiling) {
case I915_TILING_X:
- tile.swizzle = i915->ggtt.bit_6_swizzle_x;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
break;
case I915_TILING_Y:
- tile.swizzle = i915->ggtt.bit_6_swizzle_y;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
break;
}
@@ -440,7 +440,7 @@ static int igt_smoke_tiling(void *arg)
IGT_TIMEOUT(end);
int err;
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
/*
@@ -457,7 +457,7 @@ static int igt_smoke_tiling(void *arg)
obj = huge_gem_object(i915,
nreal << PAGE_SHIFT,
- (1 + next_prime_number(i915->ggtt.vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
if (IS_ERR(obj))
return PTR_ERR(obj);
@@ -486,10 +486,10 @@ static int igt_smoke_tiling(void *arg)
break;
case I915_TILING_X:
- tile.swizzle = i915->ggtt.bit_6_swizzle_x;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
break;
case I915_TILING_Y:
- tile.swizzle = i915->ggtt.bit_6_swizzle_y;
+ tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
break;
}
@@ -856,6 +856,7 @@ static int wc_check(struct drm_i915_gem_object *obj)
static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
bool no_map;
if (obj->ops->mmap_offset)
@@ -864,7 +865,7 @@ static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
return false;
if (type == I915_MMAP_TYPE_GTT &&
- !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
+ !i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return false;
i915_gem_object_lock(obj, NULL);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
index 740ee8086a27..fe0a890775e2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
@@ -43,7 +43,7 @@ static int igt_gem_huge(void *arg)
obj = huge_gem_object(i915,
nreal * PAGE_SIZE,
- i915->ggtt.vm.total + PAGE_SIZE);
+ to_gt(i915)->ggtt->vm.total + PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v9 4/6] drm/i915/display: Use to_gt() helper for GGTT accesses
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-19 21:24 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 987ea4c4b5d0..edb2ad5bf6e4 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -605,7 +605,7 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
else if (DISPLAY_VER(i915) == 9)
skl_fbc_program_cfb_stride(fbc);
- if (i915->ggtt.num_fences)
+ if (to_gt(i915)->ggtt->num_fences)
snb_fbc_program_fence(fbc);
intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..41d279db2be6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -180,7 +180,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = to_gt(dev_priv)->ggtt;
const struct i915_ggtt_view view = {
.type = I915_GGTT_VIEW_NORMAL,
};
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 01ce1d72297f..e4186a0b8edb 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -94,7 +94,7 @@ initial_plane_vma(struct drm_i915_private *i915,
goto err_obj;
}
- vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma))
goto err_obj;
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v9 4/6] drm/i915/display: Use to_gt() helper for GGTT accesses
@ 2021-12-19 21:24 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 987ea4c4b5d0..edb2ad5bf6e4 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -605,7 +605,7 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
else if (DISPLAY_VER(i915) == 9)
skl_fbc_program_cfb_stride(fbc);
- if (i915->ggtt.num_fences)
+ if (to_gt(i915)->ggtt->num_fences)
snb_fbc_program_fence(fbc);
intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..41d279db2be6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -180,7 +180,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = to_gt(dev_priv)->ggtt;
const struct i915_ggtt_view view = {
.type = I915_GGTT_VIEW_NORMAL,
};
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 01ce1d72297f..e4186a0b8edb 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -94,7 +94,7 @@ initial_plane_vma(struct drm_i915_private *i915,
goto err_obj;
}
- vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma))
goto err_obj;
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v9 5/6] drm/i915/selftests: Use to_gt() helper for GGTT accesses
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-19 21:24 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/selftests/i915_gem.c | 8 ++++----
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c
index b5576888cd78..1628b81d0a35 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -41,7 +41,7 @@ static int switch_to_context(struct i915_gem_context *ctx)
static void trash_stolen(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
const u64 slot = ggtt->error_capture.start;
const resource_size_t size = resource_size(&i915->dsm);
unsigned long page;
@@ -99,7 +99,7 @@ static void igt_pm_suspend(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- i915_ggtt_suspend(&i915->ggtt);
+ i915_ggtt_suspend(to_gt(i915)->ggtt);
i915_gem_suspend_late(i915);
}
}
@@ -109,7 +109,7 @@ static void igt_pm_hibernate(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- i915_ggtt_suspend(&i915->ggtt);
+ i915_ggtt_suspend(to_gt(i915)->ggtt);
i915_gem_freeze(i915);
i915_gem_freeze_late(i915);
@@ -125,7 +125,7 @@ static void igt_pm_resume(struct drm_i915_private *i915)
* that runtime-pm just works.
*/
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- i915_ggtt_resume(&i915->ggtt);
+ i915_ggtt_resume(to_gt(i915)->ggtt);
i915_gem_resume(i915);
}
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 48123c3e1ff0..9afe7cf9d068 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1122,7 +1122,7 @@ static int exercise_ggtt(struct drm_i915_private *i915,
u64 hole_start, u64 hole_end,
unsigned long end_time))
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
u64 hole_start, hole_end, last = 0;
struct drm_mm_node *node;
IGT_TIMEOUT(end_time);
@@ -1182,7 +1182,7 @@ static int igt_ggtt_page(void *arg)
const unsigned int count = PAGE_SIZE/sizeof(u32);
I915_RND_STATE(prng);
struct drm_i915_private *i915 = arg;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_object *obj;
intel_wakeref_t wakeref;
struct drm_mm_node tmp;
@@ -2110,7 +2110,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_cs_tlb),
};
- GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));
+ GEM_BUG_ON(offset_in_page(to_gt(i915)->ggtt->vm.total));
return i915_subtests(tests, i915);
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 92a859b34190..7f66f6d299b2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -843,7 +843,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private *i915)
intel_gt_chipset_flush(to_gt(i915));
- vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 1f10fe36619b..6ac15d3bc5bc 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -967,7 +967,7 @@ static int igt_vma_remapped_gtt(void *arg)
intel_wakeref_t wakeref;
int err = 0;
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8aa7b1d33865..0b469ae0f474 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -69,7 +69,7 @@ static void mock_device_release(struct drm_device *dev)
i915_gem_drain_workqueue(i915);
i915_gem_drain_freed_objects(i915);
- mock_fini_ggtt(&i915->ggtt);
+ mock_fini_ggtt(to_gt(i915)->ggtt);
destroy_workqueue(i915->wq);
intel_region_ttm_device_fini(i915);
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v9 5/6] drm/i915/selftests: Use to_gt() helper for GGTT accesses
@ 2021-12-19 21:24 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:24 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
From: Michał Winiarski <michal.winiarski@intel.com>
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/selftests/i915_gem.c | 8 ++++----
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c
index b5576888cd78..1628b81d0a35 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -41,7 +41,7 @@ static int switch_to_context(struct i915_gem_context *ctx)
static void trash_stolen(struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
const u64 slot = ggtt->error_capture.start;
const resource_size_t size = resource_size(&i915->dsm);
unsigned long page;
@@ -99,7 +99,7 @@ static void igt_pm_suspend(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- i915_ggtt_suspend(&i915->ggtt);
+ i915_ggtt_suspend(to_gt(i915)->ggtt);
i915_gem_suspend_late(i915);
}
}
@@ -109,7 +109,7 @@ static void igt_pm_hibernate(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- i915_ggtt_suspend(&i915->ggtt);
+ i915_ggtt_suspend(to_gt(i915)->ggtt);
i915_gem_freeze(i915);
i915_gem_freeze_late(i915);
@@ -125,7 +125,7 @@ static void igt_pm_resume(struct drm_i915_private *i915)
* that runtime-pm just works.
*/
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- i915_ggtt_resume(&i915->ggtt);
+ i915_ggtt_resume(to_gt(i915)->ggtt);
i915_gem_resume(i915);
}
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 48123c3e1ff0..9afe7cf9d068 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1122,7 +1122,7 @@ static int exercise_ggtt(struct drm_i915_private *i915,
u64 hole_start, u64 hole_end,
unsigned long end_time))
{
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
u64 hole_start, hole_end, last = 0;
struct drm_mm_node *node;
IGT_TIMEOUT(end_time);
@@ -1182,7 +1182,7 @@ static int igt_ggtt_page(void *arg)
const unsigned int count = PAGE_SIZE/sizeof(u32);
I915_RND_STATE(prng);
struct drm_i915_private *i915 = arg;
- struct i915_ggtt *ggtt = &i915->ggtt;
+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_object *obj;
intel_wakeref_t wakeref;
struct drm_mm_node tmp;
@@ -2110,7 +2110,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_cs_tlb),
};
- GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));
+ GEM_BUG_ON(offset_in_page(to_gt(i915)->ggtt->vm.total));
return i915_subtests(tests, i915);
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 92a859b34190..7f66f6d299b2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -843,7 +843,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private *i915)
intel_gt_chipset_flush(to_gt(i915));
- vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 1f10fe36619b..6ac15d3bc5bc 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -967,7 +967,7 @@ static int igt_vma_remapped_gtt(void *arg)
intel_wakeref_t wakeref;
int err = 0;
- if (!i915_ggtt_has_aperture(&i915->ggtt))
+ if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8aa7b1d33865..0b469ae0f474 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -69,7 +69,7 @@ static void mock_device_release(struct drm_device *dev)
i915_gem_drain_workqueue(i915);
i915_gem_drain_freed_objects(i915);
- mock_fini_ggtt(&i915->ggtt);
+ mock_fini_ggtt(to_gt(i915)->ggtt);
destroy_workqueue(i915->wq);
intel_region_ttm_device_fini(i915);
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v9 6/6] drm/i915: Remove unused i915->ggtt
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
@ 2021-12-19 21:25 ` Andi Shyti
-1 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:25 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Andi Shyti, Lucas De Marchi, Chris Wilson,
Andi Shyti, Michał Winiarski
The reference to the GGTT from the private date is not used
anymore. Remove it.
The ggtt in the root gt will now be dynamically allocated and the
deallocation handled by the drmm_* managed allocation.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++--
drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 +++-
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 20 ++++++++++---------
drivers/gpu/drm/i915/selftests/i915_vma.c | 20 ++++++++++---------
.../gpu/drm/i915/selftests/mock_gem_device.c | 9 +++++++--
drivers/gpu/drm/i915/selftests/mock_gtt.c | 9 ++++-----
drivers/gpu/drm/i915/selftests/mock_gtt.h | 3 ++-
9 files changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f98f0fb21efb..298ff32c8d0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -3,6 +3,7 @@
* Copyright © 2019 Intel Corporation
*/
+#include <drm/drm_managed.h>
#include <drm/intel-gtt.h>
#include "intel_gt_debugfs.h"
@@ -85,9 +86,11 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return 0;
}
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
+int intel_gt_assign_ggtt(struct intel_gt *gt)
{
- gt->ggtt = ggtt;
+ gt->ggtt = drmm_kzalloc(>->i915->drm, sizeof(*gt->ggtt), GFP_KERNEL);
+
+ return gt->ggtt ? 0 : -ENOMEM;
}
static const struct intel_mmio_range icl_l3bank_steering_table[] = {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 3ace129eb2af..94e1bac8c0cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -36,7 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
+int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_probe_lmem(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 3c984553d86f..5f2343389b5e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,7 +571,9 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
i915_perf_init(dev_priv);
- intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
+ ret = intel_gt_assign_ggtt(to_gt(dev_priv));
+ if (ret)
+ goto err_perf;
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 524025790fe0..041b24927e74 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -825,8 +825,6 @@ struct drm_i915_private {
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
- struct i915_ggtt ggtt; /* VM representing the global address space */
-
struct i915_gem_mm mm;
/* Kernel Modesetting */
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 9afe7cf9d068..f62f7dac57f2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1737,26 +1737,28 @@ int i915_gem_gtt_mock_selftests(void)
SUBTEST(igt_gtt_insert),
};
struct drm_i915_private *i915;
- struct i915_ggtt *ggtt;
+ struct intel_gt *gt;
int err;
i915 = mock_gem_device();
if (!i915)
return -ENOMEM;
- ggtt = kmalloc(sizeof(*ggtt), GFP_KERNEL);
- if (!ggtt) {
- err = -ENOMEM;
+ /* allocate the ggtt */
+ err = intel_gt_assign_ggtt(to_gt(i915));
+ if (err)
goto out_put;
- }
- mock_init_ggtt(i915, ggtt);
- err = i915_subtests(tests, ggtt);
+ gt = to_gt(i915);
+
+ mock_init_ggtt(gt);
+
+ err = i915_subtests(tests, gt->ggtt);
mock_device_flush(i915);
i915_gem_drain_freed_objects(i915);
- mock_fini_ggtt(ggtt);
- kfree(ggtt);
+ mock_fini_ggtt(gt->ggtt);
+
out_put:
mock_destroy_device(i915);
return err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 6ac15d3bc5bc..a87cba4eb92f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -907,26 +907,28 @@ int i915_vma_mock_selftests(void)
SUBTEST(igt_vma_partial),
};
struct drm_i915_private *i915;
- struct i915_ggtt *ggtt;
+ struct intel_gt *gt;
int err;
i915 = mock_gem_device();
if (!i915)
return -ENOMEM;
- ggtt = kmalloc(sizeof(*ggtt), GFP_KERNEL);
- if (!ggtt) {
- err = -ENOMEM;
+ /* allocate the ggtt */
+ err = intel_gt_assign_ggtt(to_gt(i915));
+ if (err)
goto out_put;
- }
- mock_init_ggtt(i915, ggtt);
- err = i915_subtests(tests, ggtt);
+ gt = to_gt(i915);
+
+ mock_init_ggtt(gt);
+
+ err = i915_subtests(tests, gt->ggtt);
mock_device_flush(i915);
i915_gem_drain_freed_objects(i915);
- mock_fini_ggtt(ggtt);
- kfree(ggtt);
+ mock_fini_ggtt(gt->ggtt);
+
out_put:
mock_destroy_device(i915);
return err;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 0b469ae0f474..28a0f054009a 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -194,8 +194,13 @@ struct drm_i915_private *mock_gem_device(void)
mock_init_contexts(i915);
- mock_init_ggtt(i915, &i915->ggtt);
- to_gt(i915)->vm = i915_vm_get(&i915->ggtt.vm);
+ /* allocate the ggtt */
+ ret = intel_gt_assign_ggtt(to_gt(i915));
+ if (ret)
+ goto err_unlock;
+
+ mock_init_ggtt(to_gt(i915));
+ to_gt(i915)->vm = i915_vm_get(&to_gt(i915)->ggtt->vm);
mkwrite_device_info(i915)->platform_engine_mask = BIT(0);
to_gt(i915)->info.engine_mask = BIT(0);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index 13bb0c3c3f0d..a36f46d50e83 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -106,12 +106,12 @@ static void mock_unbind_ggtt(struct i915_address_space *vm,
{
}
-void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
+void mock_init_ggtt(struct intel_gt *gt)
{
- memset(ggtt, 0, sizeof(*ggtt));
+ struct i915_ggtt *ggtt = gt->ggtt;
- ggtt->vm.gt = to_gt(i915);
- ggtt->vm.i915 = i915;
+ ggtt->vm.gt = gt;
+ ggtt->vm.i915 = gt->i915;
ggtt->vm.is_ggtt = true;
ggtt->gmadr = (struct resource) DEFINE_RES_MEM(0, 2048 * PAGE_SIZE);
@@ -132,7 +132,6 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
ggtt->vm.vma_ops.clear_pages = clear_pages;
i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
- to_gt(i915)->ggtt = ggtt;
}
void mock_fini_ggtt(struct i915_ggtt *ggtt)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.h b/drivers/gpu/drm/i915/selftests/mock_gtt.h
index e3f224f43beb..d6eb90bd7f3f 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.h
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.h
@@ -27,8 +27,9 @@
struct drm_i915_private;
struct i915_ggtt;
+struct intel_gt;
-void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt);
+void mock_init_ggtt(struct intel_gt *gt);
void mock_fini_ggtt(struct i915_ggtt *ggtt);
struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name);
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v9 6/6] drm/i915: Remove unused i915->ggtt
@ 2021-12-19 21:25 ` Andi Shyti
0 siblings, 0 replies; 48+ messages in thread
From: Andi Shyti @ 2021-12-19 21:25 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Michał Winiarski
The reference to the GGTT from the private date is not used
anymore. Remove it.
The ggtt in the root gt will now be dynamically allocated and the
deallocation handled by the drmm_* managed allocation.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++--
drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 +++-
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 20 ++++++++++---------
drivers/gpu/drm/i915/selftests/i915_vma.c | 20 ++++++++++---------
.../gpu/drm/i915/selftests/mock_gem_device.c | 9 +++++++--
drivers/gpu/drm/i915/selftests/mock_gtt.c | 9 ++++-----
drivers/gpu/drm/i915/selftests/mock_gtt.h | 3 ++-
9 files changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f98f0fb21efb..298ff32c8d0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -3,6 +3,7 @@
* Copyright © 2019 Intel Corporation
*/
+#include <drm/drm_managed.h>
#include <drm/intel-gtt.h>
#include "intel_gt_debugfs.h"
@@ -85,9 +86,11 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return 0;
}
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
+int intel_gt_assign_ggtt(struct intel_gt *gt)
{
- gt->ggtt = ggtt;
+ gt->ggtt = drmm_kzalloc(>->i915->drm, sizeof(*gt->ggtt), GFP_KERNEL);
+
+ return gt->ggtt ? 0 : -ENOMEM;
}
static const struct intel_mmio_range icl_l3bank_steering_table[] = {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 3ace129eb2af..94e1bac8c0cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -36,7 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
+int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_probe_lmem(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 3c984553d86f..5f2343389b5e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,7 +571,9 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
i915_perf_init(dev_priv);
- intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
+ ret = intel_gt_assign_ggtt(to_gt(dev_priv));
+ if (ret)
+ goto err_perf;
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 524025790fe0..041b24927e74 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -825,8 +825,6 @@ struct drm_i915_private {
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
- struct i915_ggtt ggtt; /* VM representing the global address space */
-
struct i915_gem_mm mm;
/* Kernel Modesetting */
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 9afe7cf9d068..f62f7dac57f2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1737,26 +1737,28 @@ int i915_gem_gtt_mock_selftests(void)
SUBTEST(igt_gtt_insert),
};
struct drm_i915_private *i915;
- struct i915_ggtt *ggtt;
+ struct intel_gt *gt;
int err;
i915 = mock_gem_device();
if (!i915)
return -ENOMEM;
- ggtt = kmalloc(sizeof(*ggtt), GFP_KERNEL);
- if (!ggtt) {
- err = -ENOMEM;
+ /* allocate the ggtt */
+ err = intel_gt_assign_ggtt(to_gt(i915));
+ if (err)
goto out_put;
- }
- mock_init_ggtt(i915, ggtt);
- err = i915_subtests(tests, ggtt);
+ gt = to_gt(i915);
+
+ mock_init_ggtt(gt);
+
+ err = i915_subtests(tests, gt->ggtt);
mock_device_flush(i915);
i915_gem_drain_freed_objects(i915);
- mock_fini_ggtt(ggtt);
- kfree(ggtt);
+ mock_fini_ggtt(gt->ggtt);
+
out_put:
mock_destroy_device(i915);
return err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 6ac15d3bc5bc..a87cba4eb92f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -907,26 +907,28 @@ int i915_vma_mock_selftests(void)
SUBTEST(igt_vma_partial),
};
struct drm_i915_private *i915;
- struct i915_ggtt *ggtt;
+ struct intel_gt *gt;
int err;
i915 = mock_gem_device();
if (!i915)
return -ENOMEM;
- ggtt = kmalloc(sizeof(*ggtt), GFP_KERNEL);
- if (!ggtt) {
- err = -ENOMEM;
+ /* allocate the ggtt */
+ err = intel_gt_assign_ggtt(to_gt(i915));
+ if (err)
goto out_put;
- }
- mock_init_ggtt(i915, ggtt);
- err = i915_subtests(tests, ggtt);
+ gt = to_gt(i915);
+
+ mock_init_ggtt(gt);
+
+ err = i915_subtests(tests, gt->ggtt);
mock_device_flush(i915);
i915_gem_drain_freed_objects(i915);
- mock_fini_ggtt(ggtt);
- kfree(ggtt);
+ mock_fini_ggtt(gt->ggtt);
+
out_put:
mock_destroy_device(i915);
return err;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 0b469ae0f474..28a0f054009a 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -194,8 +194,13 @@ struct drm_i915_private *mock_gem_device(void)
mock_init_contexts(i915);
- mock_init_ggtt(i915, &i915->ggtt);
- to_gt(i915)->vm = i915_vm_get(&i915->ggtt.vm);
+ /* allocate the ggtt */
+ ret = intel_gt_assign_ggtt(to_gt(i915));
+ if (ret)
+ goto err_unlock;
+
+ mock_init_ggtt(to_gt(i915));
+ to_gt(i915)->vm = i915_vm_get(&to_gt(i915)->ggtt->vm);
mkwrite_device_info(i915)->platform_engine_mask = BIT(0);
to_gt(i915)->info.engine_mask = BIT(0);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index 13bb0c3c3f0d..a36f46d50e83 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -106,12 +106,12 @@ static void mock_unbind_ggtt(struct i915_address_space *vm,
{
}
-void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
+void mock_init_ggtt(struct intel_gt *gt)
{
- memset(ggtt, 0, sizeof(*ggtt));
+ struct i915_ggtt *ggtt = gt->ggtt;
- ggtt->vm.gt = to_gt(i915);
- ggtt->vm.i915 = i915;
+ ggtt->vm.gt = gt;
+ ggtt->vm.i915 = gt->i915;
ggtt->vm.is_ggtt = true;
ggtt->gmadr = (struct resource) DEFINE_RES_MEM(0, 2048 * PAGE_SIZE);
@@ -132,7 +132,6 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
ggtt->vm.vma_ops.clear_pages = clear_pages;
i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
- to_gt(i915)->ggtt = ggtt;
}
void mock_fini_ggtt(struct i915_ggtt *ggtt)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.h b/drivers/gpu/drm/i915/selftests/mock_gtt.h
index e3f224f43beb..d6eb90bd7f3f 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.h
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.h
@@ -27,8 +27,9 @@
struct drm_i915_private;
struct i915_ggtt;
+struct intel_gt;
-void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt);
+void mock_init_ggtt(struct intel_gt *gt);
void mock_fini_ggtt(struct i915_ggtt *ggtt);
struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name);
--
2.34.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More preparation for multi gt patches
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (6 preceding siblings ...)
(?)
@ 2021-12-19 21:54 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-19 21:54 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
99fedc5dc623 drm/i915/gt: Use to_gt() helper for GGTT accesses
3c62ac9c17e8 drm/i915: Use to_gt() helper for GGTT accesses
0a746b790559 drm/i915/gem: Use to_gt() helper for GGTT accesses
-:304: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#304: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:323:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
-:335: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#335: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:460:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
total: 0 errors, 2 warnings, 0 checks, 287 lines checked
d7ce0b926483 drm/i915/display: Use to_gt() helper for GGTT accesses
eadd746d2b64 drm/i915/selftests: Use to_gt() helper for GGTT accesses
cc5f53a75582 drm/i915: Remove unused i915->ggtt
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for More preparation for multi gt patches
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (7 preceding siblings ...)
(?)
@ 2021-12-19 21:56 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-19 21:56 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for More preparation for multi gt patches
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (8 preceding siblings ...)
(?)
@ 2021-12-19 22:23 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-19 22:23 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8392 bytes --]
== Series Details ==
Series: More preparation for multi gt patches
URL : https://patchwork.freedesktop.org/series/98215/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11014 -> Patchwork_21876
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/index.html
Participating hosts (41 -> 35)
------------------------------
Additional (3): fi-bxt-dsi fi-bdw-5557u fi-tgl-u2
Missing (9): fi-kbl-soraka bat-dg1-6 bat-dg1-5 fi-skl-guc fi-icl-u2 fi-bsw-cyan bat-adlp-6 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_21876 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: NOTRUN -> [INCOMPLETE][2] ([i915#4006])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][3] -> [FAIL][4] ([i915#4547])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
- fi-bxt-dsi: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bxt-dsi/igt@gem_lmem_swapping@verify-random.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bxt-dsi: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bxt-dsi/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
- fi-bsw-nick: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bsw-nick/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827]) +8 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][13] ([i915#4103]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-dsi: NOTRUN -> [SKIP][14] ([fdo#109271]) +30 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bxt-dsi/igt@kms_force_connector_basic@force-load-detect.html
- fi-tgl-u2: NOTRUN -> [SKIP][15] ([fdo#109285])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-bxt-dsi: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bxt-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-fence-flip:
- fi-bsw-nick: NOTRUN -> [SKIP][17] ([fdo#109271]) +62 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bsw-nick/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][18] ([i915#3301])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][19] ([i915#4312])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-skl-6600u/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][20] ([i915#2722] / [i915#4312])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic:
- fi-bsw-nick: [DMESG-WARN][21] ([i915#3428]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-bsw-nick/igt@gem_ctx_exec@basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-bsw-nick/igt@gem_ctx_exec@basic.html
* igt@i915_selftest@live@gem_contexts:
- {fi-tgl-dsi}: [INCOMPLETE][23] ([i915#402]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hugepages:
- {fi-tgl-dsi}: [INCOMPLETE][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-tgl-dsi/igt@i915_selftest@live@hugepages.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/fi-tgl-dsi/igt@i915_selftest@live@hugepages.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11014 -> Patchwork_21876
CI-20190529: 20190529
CI_DRM_11014: c4f095f24fcdc6e85ae112052b3034328e24ae66 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6313: 1793ed798cc09966c27bf478781e0c1d6bb23bad @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21876: cc5f53a7558201bb07db6ac91c31634e03c9de92 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cc5f53a75582 drm/i915: Remove unused i915->ggtt
eadd746d2b64 drm/i915/selftests: Use to_gt() helper for GGTT accesses
d7ce0b926483 drm/i915/display: Use to_gt() helper for GGTT accesses
0a746b790559 drm/i915/gem: Use to_gt() helper for GGTT accesses
3c62ac9c17e8 drm/i915: Use to_gt() helper for GGTT accesses
99fedc5dc623 drm/i915/gt: Use to_gt() helper for GGTT accesses
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/index.html
[-- Attachment #2: Type: text/html, Size: 10358 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for More preparation for multi gt patches
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (9 preceding siblings ...)
(?)
@ 2021-12-19 23:24 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-19 23:24 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30260 bytes --]
== Series Details ==
Series: More preparation for multi gt patches
URL : https://patchwork.freedesktop.org/series/98215/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11014_full -> Patchwork_21876_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 11)
------------------------------
Additional (1): shard-rkl
Known issues
------------
Here are the changes found in Patchwork_21876_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [FAIL][23], [PASS][24], [PASS][25]) ([i915#4386]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl8/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl8/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl8/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl7/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl7/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl7/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl6/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl6/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl6/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl4/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl4/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl4/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl3/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl3/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl3/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl2/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl2/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl2/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl2/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl3/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl6/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl7/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl7/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl7/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][51] ([i915#3002])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl6/igt@gem_create@create-massive.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-iclb: [PASS][52] -> [TIMEOUT][53] ([i915#3070])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb5/igt@gem_eio@in-flight-contexts-immediate.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [PASS][54] -> [TIMEOUT][55] ([i915#3063])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-skl8/igt@gem_eio@unwedge-stress.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][56] ([i915#4547])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [PASS][57] -> [FAIL][58] ([i915#2842])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk8/igt@gem_exec_fair@basic-none@vecs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-glk6/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][59] -> [FAIL][60] ([i915#2842])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][61] -> [FAIL][62] ([i915#2842]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][63] -> [FAIL][64] ([i915#2849])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2190])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#4613])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl7/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@random-engines:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl6/igt@gem_lmem_swapping@random-engines.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-iclb: NOTRUN -> [SKIP][69] ([i915#4270]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271]) +132 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#768])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3323])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#3297])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][74] -> [DMESG-WARN][75] ([i915#1436] / [i915#716])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk6/igt@gen9_exec_parse@allowed-all.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@unaligned-access:
- shard-iclb: NOTRUN -> [SKIP][76] ([i915#2856])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][77] -> [INCOMPLETE][78] ([i915#3921])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-snb6/igt@i915_selftest@live@hangcheck.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#110725] / [fdo#111614])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3777])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglb: [PASS][81] -> [FAIL][82] ([i915#3743])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-tglb7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-tglb6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#3777])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#110723])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][85] ([i915#3743])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271]) +91 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +5 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl7/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109278]) +10 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#3886]) +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl4/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109284] / [fdo#111827]) +4 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111827]) +6 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [fdo#111827]) +14 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl7/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [fdo#111827]) +7 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][95] ([i915#1319])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl4/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-iclb: NOTRUN -> [SKIP][96] ([i915#3116])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][97] ([i915#2105])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109278] / [fdo#109279]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109274] / [fdo#109278]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-skl: [PASS][100] -> [FAIL][101] ([i915#533])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-skl4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109274])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [PASS][103] -> [FAIL][104] ([i915#79])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][105] -> [DMESG-WARN][106] ([i915#180]) +8 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][107] ([i915#165] / [i915#180])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl7/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][108] ([i915#180]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][109] -> [FAIL][110] ([i915#2122])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2672])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
- shard-iclb: NOTRUN -> [SKIP][112] ([i915#2587])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][113] ([fdo#109271]) +103 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][114] ([fdo#109280]) +10 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#533])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#533]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-kbl: [PASS][117] -> [DMESG-WARN][118] ([i915#180])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][119] ([i915#265])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][120] ([fdo#108145] / [i915#265]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl7/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_lowres@pipe-c-tiling-none:
- shard-iclb: NOTRUN -> [SKIP][121] ([i915#3536])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_plane_lowres@pipe-c-tiling-none.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: NOTRUN -> [SKIP][122] ([fdo#111068] / [i915#658])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
- shard-apl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#658])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-kbl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#658])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][125] -> [SKIP][126] ([fdo#109441]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: NOTRUN -> [SKIP][127] ([fdo#109441])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-skl: [PASS][128] -> [DMESG-WARN][129] ([i915#1982])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-skl9/igt@kms_universal_plane@universal-plane-pipe-c-functional.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl6/igt@kms_universal_plane@universal-plane-pipe-c-functional.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][130] -> [DMESG-WARN][131] ([i915#180] / [i915#295])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-iclb: NOTRUN -> [SKIP][132] ([i915#2437])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@kms_writeback@writeback-pixel-formats.html
- shard-apl: NOTRUN -> [SKIP][133] ([fdo#109271] / [i915#2437])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl1/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][134] -> [FAIL][135] ([i915#1722])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-skl4/igt@perf@polling-small-buf.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl2/igt@perf@polling-small-buf.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-iclb: NOTRUN -> [SKIP][136] ([fdo#109291])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@prime_nv_api@i915_nv_import_twice.html
* igt@prime_vgem@fence-read-hang:
- shard-iclb: NOTRUN -> [SKIP][137] ([fdo#109295])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb7/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#2994]) +2 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl7/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#2994])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][140] ([fdo#109271] / [i915#2994]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl4/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_eio@in-flight-suspend:
- shard-skl: [INCOMPLETE][141] -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-skl6/igt@gem_eio@in-flight-suspend.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl6/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][143] ([i915#2846]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk7/igt@gem_exec_fair@basic-deadline.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-glk4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][145] ([i915#2842]) -> [PASS][146] +2 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [FAIL][147] ([i915#2851]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][149] ([i915#454]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][151] ([i915#72]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][153] ([i915#2122]) -> [PASS][154] +1 similar issue
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [SKIP][155] ([i915#3701]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][157] ([i915#180]) -> [PASS][158] +5 similar issues
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [DMESG-WARN][159] ([i915#180]) -> [PASS][160] +2 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][161] ([fdo#109441]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][163] ([i915#180] / [i915#295]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspen
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21876/index.html
[-- Attachment #2: Type: text/html, Size: 33594 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More preparation for multi gt patches (rev2)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (10 preceding siblings ...)
(?)
@ 2021-12-21 22:09 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-21 22:09 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches (rev2)
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5769c7bdc47d drm/i915/gt: Use to_gt() helper for GGTT accesses
8678fc77a7bf drm/i915: Use to_gt() helper for GGTT accesses
32ce44f3d3ac drm/i915/gem: Use to_gt() helper for GGTT accesses
-:304: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#304: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:323:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
-:335: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#335: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:460:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
total: 0 errors, 2 warnings, 0 checks, 287 lines checked
18c94c42d751 drm/i915/display: Use to_gt() helper for GGTT accesses
94fe21e353b2 drm/i915/selftests: Use to_gt() helper for GGTT accesses
4b3d9538659c drm/i915: Remove unused i915->ggtt
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for More preparation for multi gt patches (rev2)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (11 preceding siblings ...)
(?)
@ 2021-12-21 22:10 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-21 22:10 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches (rev2)
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for More preparation for multi gt patches (rev2)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (12 preceding siblings ...)
(?)
@ 2021-12-21 22:39 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-21 22:39 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5608 bytes --]
== Series Details ==
Series: More preparation for multi gt patches (rev2)
URL : https://patchwork.freedesktop.org/series/98215/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11025 -> Patchwork_21886
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/index.html
Participating hosts (45 -> 36)
------------------------------
Additional (1): fi-pnv-d510
Missing (10): bat-dg1-6 fi-tgl-u2 bat-dg1-5 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_21886 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-blb-e6850/igt@amdgpu/amd_basic@cs-multi-fence.html
* igt@debugfs_test@read_all_entries:
- fi-bsw-kefka: [PASS][2] -> [DMESG-WARN][3] ([i915#1982])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-bsw-kefka/igt@debugfs_test@read_all_entries.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-bsw-kefka/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-tgl-1115g4: [PASS][4] -> [FAIL][5] ([i915#1888])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0@smem.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][6] -> [INCOMPLETE][7] ([i915#4547])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_module_load@reload:
- fi-tgl-1115g4: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-tgl-1115g4/igt@i915_module_load@reload.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-tgl-1115g4/igt@i915_module_load@reload.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][10] -> [DMESG-WARN][11] ([i915#4269])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][12] ([fdo#109271]) +57 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][13] ([i915#4528]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-blb-e6850/igt@i915_selftest@live@requests.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][15] ([i915#295]) -> [PASS][16] +12 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Warnings ####
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][17] ([i915#2722] / [i915#4312]) -> [FAIL][18] ([i915#4312])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/fi-skl-6600u/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/fi-skl-6600u/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
Build changes
-------------
* Linux: CI_DRM_11025 -> Patchwork_21886
CI-20190529: 20190529
CI_DRM_11025: 22bb175d528e42a3fc0dab8fcb3071773319da6f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6316: 731e09c15b4fd559ce8aec30065fccde17a9b834 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21886: 4b3d9538659c55a64dbea1bf1a001e2b9b582686 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4b3d9538659c drm/i915: Remove unused i915->ggtt
94fe21e353b2 drm/i915/selftests: Use to_gt() helper for GGTT accesses
18c94c42d751 drm/i915/display: Use to_gt() helper for GGTT accesses
32ce44f3d3ac drm/i915/gem: Use to_gt() helper for GGTT accesses
8678fc77a7bf drm/i915: Use to_gt() helper for GGTT accesses
5769c7bdc47d drm/i915/gt: Use to_gt() helper for GGTT accesses
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/index.html
[-- Attachment #2: Type: text/html, Size: 6690 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for More preparation for multi gt patches (rev2)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (13 preceding siblings ...)
(?)
@ 2021-12-22 2:47 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-22 2:47 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30267 bytes --]
== Series Details ==
Series: More preparation for multi gt patches (rev2)
URL : https://patchwork.freedesktop.org/series/98215/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11025_full -> Patchwork_21886_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21886_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21886_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21886_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl9/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
Known issues
------------
Here are the changes found in Patchwork_21886_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk2/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk8/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk7/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk6/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk5/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk3/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk3/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk6/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk8/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk8/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][53] -> [SKIP][54] ([i915#658])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-iclb2/igt@feature_discovery@psr2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb5/igt@feature_discovery@psr2.html
* igt@gem_ctx_sseu@invalid-args:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271]) +166 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl8/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#4525])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][57] ([i915#4547])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl1/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][58] -> [FAIL][59] ([i915#2842])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][60] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][61] -> [FAIL][62] ([i915#2842])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][63] ([i915#2842])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][64] -> [FAIL][65] ([i915#2842]) +3 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][66] -> [FAIL][67] ([i915#2849])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#112283])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-glk: [PASS][69] -> [DMESG-WARN][70] ([i915#118])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-glk3/igt@gem_exec_whisper@basic-queues-forked.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-glk8/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2190])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-random:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#4613]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl4/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#4613])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl8/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#4613]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl6/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@verify:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#4613]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb2/igt@gem_lmem_swapping@verify.html
* igt@gem_lmem_swapping@verify-random:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#4613]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb3/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pxp@display-protected-crc:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#4270])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@gem_pxp@display-protected-crc.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#768])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][79] ([fdo#110542])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@gem_userptr_blits@coherency-sync.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#2856])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: NOTRUN -> [FAIL][81] ([i915#454])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][82] ([fdo#111644] / [i915#1397] / [i915#2411]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][83] ([fdo#110892])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb6/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][84] -> [INCOMPLETE][85] ([i915#151])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-skl7/igt@i915_pm_rpm@system-suspend.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl7/igt@i915_pm_rpm@system-suspend.html
* igt@i915_pm_sseu@full-enable:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#4387])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][87] -> [INCOMPLETE][88] ([i915#3921])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-snb2/igt@i915_selftest@live@hangcheck.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][89] -> [DMESG-WARN][90] ([i915#180]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#111614])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#110725] / [fdo#111614])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglb: [PASS][93] -> [FAIL][94] ([i915#3743])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-tglb7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3777]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#111615])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#3777]) +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#3777])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][99] ([fdo#111615] / [i915#3689]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb3/igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#3886]) +5 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][101] ([fdo#109278] / [i915#3886])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#3886]) +7 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
- shard-skl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#3886]) +4 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl8/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#3689]) +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109284] / [fdo#111827])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [fdo#111827]) +12 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl7/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@vga-hpd:
- shard-tglb: NOTRUN -> [SKIP][107] ([fdo#109284] / [fdo#111827]) +5 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-kbl: NOTRUN -> [SKIP][108] ([fdo#109271] / [fdo#111827]) +19 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl7/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color@pipe-d-ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109278] / [i915#1149])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_color@pipe-d-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][110] ([fdo#109271] / [fdo#111827]) +7 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl8/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-iclb: NOTRUN -> [SKIP][111] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_content_protection@atomic:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109300] / [fdo#111066])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][113] ([i915#1319])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl6/igt@kms_content_protection@srm.html
- shard-apl: NOTRUN -> [TIMEOUT][114] ([i915#1319])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl7/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109278] / [fdo#109279])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][116] ([i915#180])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][117] ([i915#3319])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-tglb: NOTRUN -> [SKIP][118] ([fdo#109279] / [i915#3359])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-iclb: [PASS][119] -> [FAIL][120] ([i915#2370])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-iclb1/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [PASS][121] -> [FAIL][122] ([i915#2346])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglb: NOTRUN -> [SKIP][123] ([i915#3528])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][124] -> [INCOMPLETE][125] ([i915#180])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
- shard-kbl: [PASS][126] -> [INCOMPLETE][127] ([i915#180] / [i915#636])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-iclb: NOTRUN -> [SKIP][128] ([fdo#109274]) +4 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][129] -> [FAIL][130] ([i915#2122]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-iclb: NOTRUN -> [SKIP][131] ([i915#2587])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][132] ([fdo#109271]) +115 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][133] ([fdo#109280]) +7 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][134] ([fdo#111825]) +13 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][135] -> [FAIL][136] ([i915#1188])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-skl9/igt@kms_hdr@bpc-switch.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl10/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-tglb: NOTRUN -> [SKIP][137] ([fdo#109289])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#533])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#533])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [PASS][140] -> [DMESG-WARN][141] ([i915#180]) +2 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][142] ([fdo#108145] / [i915#265])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][143] -> [FAIL][144] ([fdo#108145] / [i915#265])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][145] ([fdo#108145] / [i915#265]) +1 similar issue
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
- shard-skl: NOTRUN -> [FAIL][146] ([fdo#108145] / [i915#265])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_cursor@pipe-d-viewport-size-128:
- shard-iclb: NOTRUN -> [SKIP][147] ([fdo#109278]) +9 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_plane_cursor@pipe-d-viewport-size-128.html
* igt@kms_plane_lowres@pipe-a-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][148] ([fdo#111615] / [fdo#112054])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_plane_lowres@pipe-a-tiling-yf.html
* igt@kms_plane_lowres@pipe-c-tiling-yf:
- shard-iclb: NOTRUN -> [SKIP][149] ([i915#3536])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb3/igt@kms_plane_lowres@pipe-c-tiling-yf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-tglb: NOTRUN -> [SKIP][150] ([i915#1911])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb6/igt@kms_psr2_su@page_flip-nv12.html
- shard-iclb: NOTRUN -> [SKIP][151] ([fdo#111068] / [i915#658])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb5/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][152] ([fdo#109271] / [i915#658]) +2 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-skl7/igt@kms_psr2_su@page_flip-xrgb8888.html
- shard-kbl: NOTRUN -> [SKIP][153] ([fdo#109271] / [i915#658]) +1 similar issue
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-kbl3/igt@kms_psr2_su@page_flip-xrgb8888.html
- shard-apl: NOTRUN -> [SKIP][154] ([fdo#109271] / [i915#658]) +2 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-apl7/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][155] ([i915#132] / [i915#3467])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-tglb7/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][156] -> [SKIP][157] ([fdo#109441])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [PASS][158] -> [INCOMPLETE][159] ([i915#2828])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11025/shard-skl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[159]: https://intel
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21886/index.html
[-- Attachment #2: Type: text/html, Size: 33715 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More preparation for multi gt patches (rev3)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (14 preceding siblings ...)
(?)
@ 2022-01-04 23:07 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2022-01-04 23:07 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches (rev3)
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c7c755be7a63 drm/i915/gt: Use to_gt() helper for GGTT accesses
9eaaac9e4a25 drm/i915: Use to_gt() helper for GGTT accesses
-:234: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#234: FILE: drivers/gpu/drm/i915/i915_perf.c:1634:
+ intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
+ atomic64_read(&stream->perf->noa_programming_delay));
total: 0 errors, 0 warnings, 1 checks, 176 lines checked
0062e64281bd drm/i915/gem: Use to_gt() helper for GGTT accesses
-:304: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#304: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:323:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
-:335: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#335: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:460:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
total: 0 errors, 2 warnings, 0 checks, 287 lines checked
4d0e5e2c0049 drm/i915/display: Use to_gt() helper for GGTT accesses
7e25a514b822 drm/i915/selftests: Use to_gt() helper for GGTT accesses
462f50e3499f drm/i915: Remove unused i915->ggtt
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for More preparation for multi gt patches (rev3)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (15 preceding siblings ...)
(?)
@ 2022-01-04 23:08 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2022-01-04 23:08 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches (rev3)
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for More preparation for multi gt patches (rev3)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (16 preceding siblings ...)
(?)
@ 2022-01-04 23:34 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2022-01-04 23:34 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4866 bytes --]
== Series Details ==
Series: More preparation for multi gt patches (rev3)
URL : https://patchwork.freedesktop.org/series/98215/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11046 -> Patchwork_21921
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21921 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21921, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/index.html
Participating hosts (50 -> 35)
------------------------------
Missing (15): fi-kbl-soraka fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21921:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11046/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_21921 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][4] -> [DMESG-WARN][5] ([i915#4269])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11046/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][6] ([i915#2426] / [i915#4312])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/fi-bdw-5557u/igt@runner@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/fi-bsw-n3050/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][8] ([i915#2940]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11046/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
#### Warnings ####
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: [SKIP][10] ([i915#1072]) -> [SKIP][11] ([fdo#110189]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11046/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
Build changes
-------------
* Linux: CI_DRM_11046 -> Patchwork_21921
CI-20190529: 20190529
CI_DRM_11046: ee55310525cbff1a700aeeaf08f63a0f7b33c521 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6322: b0b7679b358b300b7b6bf42c6921d0aa1fc14388 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21921: 462f50e3499f5b4a791814c4821fa8120f0c7dd3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
462f50e3499f drm/i915: Remove unused i915->ggtt
7e25a514b822 drm/i915/selftests: Use to_gt() helper for GGTT accesses
4d0e5e2c0049 drm/i915/display: Use to_gt() helper for GGTT accesses
0062e64281bd drm/i915/gem: Use to_gt() helper for GGTT accesses
9eaaac9e4a25 drm/i915: Use to_gt() helper for GGTT accesses
c7c755be7a63 drm/i915/gt: Use to_gt() helper for GGTT accesses
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21921/index.html
[-- Attachment #2: Type: text/html, Size: 5786 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More preparation for multi gt patches (rev4)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (17 preceding siblings ...)
(?)
@ 2022-01-05 5:45 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2022-01-05 5:45 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches (rev4)
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4f190d35025d drm/i915/gt: Use to_gt() helper for GGTT accesses
afd4ed1a47d2 drm/i915: Use to_gt() helper for GGTT accesses
-:235: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#235: FILE: drivers/gpu/drm/i915/i915_perf.c:1634:
+ intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
+ atomic64_read(&stream->perf->noa_programming_delay));
total: 0 errors, 0 warnings, 1 checks, 176 lines checked
5f1faa95095c drm/i915/gem: Use to_gt() helper for GGTT accesses
-:304: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#304: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:323:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
-:335: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#335: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:460:
+ (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
total: 0 errors, 2 warnings, 0 checks, 287 lines checked
d1f4dc7bb6bb drm/i915/display: Use to_gt() helper for GGTT accesses
dd2830cfee21 drm/i915/selftests: Use to_gt() helper for GGTT accesses
7f9fe7d9fcfd drm/i915: Remove unused i915->ggtt
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for More preparation for multi gt patches (rev4)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (18 preceding siblings ...)
(?)
@ 2022-01-05 5:46 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2022-01-05 5:46 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: More preparation for multi gt patches (rev4)
URL : https://patchwork.freedesktop.org/series/98215/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for More preparation for multi gt patches (rev4)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (19 preceding siblings ...)
(?)
@ 2022-01-05 6:10 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2022-01-05 6:10 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3145 bytes --]
== Series Details ==
Series: More preparation for multi gt patches (rev4)
URL : https://patchwork.freedesktop.org/series/98215/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11047 -> Patchwork_21923
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/index.html
Participating hosts (48 -> 35)
------------------------------
Missing (13): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21923 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][1] -> [INCOMPLETE][2] ([i915#3921])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@i915_selftest@live:
- fi-skl-6600u: [INCOMPLETE][3] ([i915#4794]) -> [FAIL][4] ([i915#4547])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/fi-skl-6600u/igt@i915_selftest@live.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/fi-skl-6600u/igt@i915_selftest@live.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][5] ([i915#1436] / [i915#2722] / [i915#4312]) -> [FAIL][6] ([i915#1436] / [i915#4312])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/fi-skl-6600u/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/fi-skl-6600u/igt@runner@aborted.html
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4794]: https://gitlab.freedesktop.org/drm/intel/issues/4794
Build changes
-------------
* Linux: CI_DRM_11047 -> Patchwork_21923
CI-20190529: 20190529
CI_DRM_11047: f50e5d7abd1873b3488081da88dc8412584280b9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6323: 9dbaa0d5be7a859cda9b7d54c20ba96a596f43bd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21923: 7f9fe7d9fcfd87c623d051ffa9d57996dfd08131 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7f9fe7d9fcfd drm/i915: Remove unused i915->ggtt
dd2830cfee21 drm/i915/selftests: Use to_gt() helper for GGTT accesses
d1f4dc7bb6bb drm/i915/display: Use to_gt() helper for GGTT accesses
5f1faa95095c drm/i915/gem: Use to_gt() helper for GGTT accesses
afd4ed1a47d2 drm/i915: Use to_gt() helper for GGTT accesses
4f190d35025d drm/i915/gt: Use to_gt() helper for GGTT accesses
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/index.html
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^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for More preparation for multi gt patches (rev4)
2021-12-19 21:24 ` [Intel-gfx] " Andi Shyti
` (20 preceding siblings ...)
(?)
@ 2022-01-05 7:15 ` Patchwork
2022-01-05 19:08 ` Matt Roper
-1 siblings, 1 reply; 48+ messages in thread
From: Patchwork @ 2022-01-05 7:15 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30267 bytes --]
== Series Details ==
Series: More preparation for multi gt patches (rev4)
URL : https://patchwork.freedesktop.org/series/98215/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11047_full -> Patchwork_21923_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21923_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21923_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 12)
------------------------------
Missing (1): shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21923_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@perf@region:
- shard-snb: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-snb5/igt@i915_selftest@perf@region.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-snb5/igt@i915_selftest@perf@region.html
* igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb7/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb3/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_flush@basic-wb-prw-default:
- {shard-rkl}: [PASS][5] -> [INCOMPLETE][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-2/igt@gem_exec_flush@basic-wb-prw-default.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-5/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_schedule@u-submit-early-slice@bcs0:
- {shard-tglu}: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-8/igt@gem_exec_schedule@u-submit-early-slice@bcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-7/igt@gem_exec_schedule@u-submit-early-slice@bcs0.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- {shard-rkl}: [PASS][9] -> ([PASS][10], [INCOMPLETE][11])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@gem_exec_whisper@basic-contexts-forked-all.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-4/igt@gem_exec_whisper@basic-contexts-forked-all.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-5/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@i915_pm_dc@dc6-psr:
- {shard-tglu}: NOTRUN -> [SKIP][12]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-3/igt@i915_pm_dc@dc6-psr.html
* igt@testdisplay:
- {shard-tglu}: [PASS][13] -> [DMESG-WARN][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@testdisplay.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-5/igt@testdisplay.html
Known issues
------------
Here are the changes found in Patchwork_21923_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-tglb: NOTRUN -> [DMESG-WARN][15] ([i915#3002])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@gem_create@create-massive.html
- shard-skl: NOTRUN -> [DMESG-WARN][16] ([i915#3002])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl1/igt@gem_create@create-massive.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][17] -> [TIMEOUT][18] ([i915#3063])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb7/igt@gem_eio@in-flight-contexts-10ms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4525])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [PASS][20] -> [FAIL][21] ([i915#2842])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][22] -> [FAIL][23] ([i915#2842])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][24] -> [FAIL][25] ([i915#2842])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-kbl: [PASS][26] -> [DMESG-WARN][27] ([i915#180]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl3/igt@gem_exec_suspend@basic-s3@smem.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl4/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#2190])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#4613])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@gem_lmem_swapping@parallel-random.html
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#4613]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#4613])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@random:
- shard-skl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#4613])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl10/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@smem-oom:
- shard-tglb: NOTRUN -> [SKIP][33] ([i915#4613])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_softpin@allocator-evict@rcs0:
- shard-iclb: NOTRUN -> [DMESG-WARN][34] ([i915#4391])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@gem_softpin@allocator-evict@rcs0.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][35] ([i915#3318])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl1/igt@gem_userptr_blits@vma-merge.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][36] ([i915#454])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271]) +102 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl8/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][38] ([i915#3743])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3777]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][40] ([i915#3763])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3777])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886]) +8 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +5 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278] / [i915#3886])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +6 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_color@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278] / [i915#1149])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_color@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +12 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +10 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl10/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][51] ([i915#1319])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl8/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-random:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109279] / [i915#3359])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109278]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#109274] / [fdo#111825])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#2346] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: NOTRUN -> [INCOMPLETE][57] ([i915#180] / [i915#636])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][58] -> [FAIL][59] ([i915#79]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +4 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][62] -> [FAIL][63] ([i915#2122]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][64] -> [FAIL][65] ([i915#4911])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [PASS][66] -> [SKIP][67] ([i915#3701]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271]) +163 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][69] ([fdo#109280] / [fdo#111825]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271]) +123 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109280]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][78] -> [SKIP][79] ([fdo#109441])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109441])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_psr@psr2_sprite_render.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2437])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_writeback@writeback-invalid-parameters.html
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2437])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2437])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl10/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#2530])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-b-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#2530])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
* igt@sysfs_clients@create:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@sysfs_clients@create.html
* igt@sysfs_clients@split-10:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2994])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl4/igt@sysfs_clients@split-10.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][90] ([i915#658]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb4/igt@feature_discovery@psr2.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-skl: [TIMEOUT][92] ([i915#3063]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl4/igt@gem_eio@in-flight-contexts-10ms.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][94] ([i915#2481] / [i915#3070]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@gem_eio@unwedge-stress.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][96] ([i915#4525]) -> [PASS][97] +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][98] ([i915#2842]) -> [PASS][99] +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][100] ([i915#2842]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][102] ([i915#2842]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][104] ([i915#2842]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_parallel@fds@bcs0:
- {shard-rkl}: [INCOMPLETE][106] -> ([PASS][107], [PASS][108])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@gem_exec_parallel@fds@bcs0.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-4/igt@gem_exec_parallel@fds@bcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-2/igt@gem_exec_parallel@fds@bcs0.html
* igt@gem_exec_suspend@basic@smem:
- {shard-rkl}: [INCOMPLETE][109] -> [PASS][110] +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@gem_exec_suspend@basic@smem.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@gem_exec_suspend@basic@smem.html
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-glk: [DMESG-WARN][111] ([i915#118]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk8/igt@gem_exec_whisper@basic-contexts-priority.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- {shard-tglu}: [INCOMPLETE][113] ([i915#750]) -> [PASS][114] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-7/igt@gem_ppgtt@blt-vs-render-ctxn.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-8/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][115] ([i915#180]) -> [PASS][116] +3 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rc6_residency@rc6-fence:
- {shard-tglu}: [WARN][117] ([i915#2681]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@gem-mmap-type@uc:
- {shard-rkl}: [SKIP][119] ([fdo#109308]) -> [PASS][120] +3 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@i915_pm_rpm@gem-mmap-type@uc.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@i915_pm_rpm@gem-mmap-type@uc.html
* igt@i915_selftest@live@gt_pm:
- {shard-tglu}: [DMESG-FAIL][121] ([i915#3987]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-8/igt@i915_selftest@live@gt_pm.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-7/igt@i915_selftest@live@gt_pm.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs:
- {shard-rkl}: [SKIP][123] ([i915#1845] / [i915#4098]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
- {shard-rkl}: ([PASS][125], [SKIP][126]) ([fdo#112022]) -> [PASS][127]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][128] ([i915#180]) -> [PASS][129] +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [FAIL][130] ([i915#2346]) -> [PASS][131] +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
- {shard-rkl}: [SKIP][132] ([fdo#111314]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [SKIP][134] ([i915#3701]) -> [PASS][135] +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- {shard-rkl}: [SKIP][136] ([i915#4098]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- {shard-rkl}: [SKIP][138] ([i915#1849]) -> [PASS][139] +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_frontbuff
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/index.html
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^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for More preparation for multi gt patches (rev4)
2022-01-05 7:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-01-05 19:08 ` Matt Roper
0 siblings, 0 replies; 48+ messages in thread
From: Matt Roper @ 2022-01-05 19:08 UTC (permalink / raw)
To: intel-gfx
On Wed, Jan 05, 2022 at 07:15:51AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: More preparation for multi gt patches (rev4)
> URL : https://patchwork.freedesktop.org/series/98215/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11047_full -> Patchwork_21923_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_21923_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_21923_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (13 -> 12)
> ------------------------------
>
> Missing (1): shard-dg1
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_21923_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@perf@region:
> - shard-snb: [PASS][1] -> [DMESG-FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-snb5/igt@i915_selftest@perf@region.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-snb5/igt@i915_selftest@perf@region.html
Looks to be the same as
https://gitlab.freedesktop.org/drm/intel/-/issues/4610
>
> * igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb:
> - shard-tglb: [PASS][3] -> [INCOMPLETE][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb7/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb3/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html
Random system crash / connection loss? Incomplete result doesn't appear
to be related to the series here.
Series applied to drm-intel-gt-next. Thanks for the patches.
Matt
>
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_flush@basic-wb-prw-default:
> - {shard-rkl}: [PASS][5] -> [INCOMPLETE][6] +1 similar issue
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-2/igt@gem_exec_flush@basic-wb-prw-default.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-5/igt@gem_exec_flush@basic-wb-prw-default.html
>
> * igt@gem_exec_schedule@u-submit-early-slice@bcs0:
> - {shard-tglu}: [PASS][7] -> [INCOMPLETE][8]
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-8/igt@gem_exec_schedule@u-submit-early-slice@bcs0.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-7/igt@gem_exec_schedule@u-submit-early-slice@bcs0.html
>
> * igt@gem_exec_whisper@basic-contexts-forked-all:
> - {shard-rkl}: [PASS][9] -> ([PASS][10], [INCOMPLETE][11])
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@gem_exec_whisper@basic-contexts-forked-all.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-4/igt@gem_exec_whisper@basic-contexts-forked-all.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-5/igt@gem_exec_whisper@basic-contexts-forked-all.html
>
> * igt@i915_pm_dc@dc6-psr:
> - {shard-tglu}: NOTRUN -> [SKIP][12]
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-3/igt@i915_pm_dc@dc6-psr.html
>
> * igt@testdisplay:
> - {shard-tglu}: [PASS][13] -> [DMESG-WARN][14]
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@testdisplay.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-5/igt@testdisplay.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_21923_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_create@create-massive:
> - shard-tglb: NOTRUN -> [DMESG-WARN][15] ([i915#3002])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@gem_create@create-massive.html
> - shard-skl: NOTRUN -> [DMESG-WARN][16] ([i915#3002])
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl1/igt@gem_create@create-massive.html
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - shard-tglb: [PASS][17] -> [TIMEOUT][18] ([i915#3063])
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb7/igt@gem_eio@in-flight-contexts-10ms.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb2/igt@gem_eio@in-flight-contexts-10ms.html
>
> * igt@gem_exec_balancer@parallel-contexts:
> - shard-iclb: NOTRUN -> [SKIP][19] ([i915#4525])
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@gem_exec_balancer@parallel-contexts.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-apl: [PASS][20] -> [FAIL][21] ([i915#2842])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
>
> * igt@gem_exec_fair@basic-none@vecs0:
> - shard-kbl: [PASS][22] -> [FAIL][23] ([i915#2842])
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
>
> * igt@gem_exec_fair@basic-throttle@rcs0:
> - shard-iclb: [PASS][24] -> [FAIL][25] ([i915#2842])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
>
> * igt@gem_exec_suspend@basic-s3@smem:
> - shard-kbl: [PASS][26] -> [DMESG-WARN][27] ([i915#180]) +2 similar issues
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl3/igt@gem_exec_suspend@basic-s3@smem.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl4/igt@gem_exec_suspend@basic-s3@smem.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#2190])
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_lmem_swapping@parallel-random:
> - shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#4613])
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@gem_lmem_swapping@parallel-random.html
> - shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#4613]) +1 similar issue
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@gem_lmem_swapping@parallel-random.html
>
> * igt@gem_lmem_swapping@parallel-random-verify:
> - shard-iclb: NOTRUN -> [SKIP][31] ([i915#4613])
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@gem_lmem_swapping@parallel-random-verify.html
>
> * igt@gem_lmem_swapping@random:
> - shard-skl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#4613])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl10/igt@gem_lmem_swapping@random.html
>
> * igt@gem_lmem_swapping@smem-oom:
> - shard-tglb: NOTRUN -> [SKIP][33] ([i915#4613])
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@gem_lmem_swapping@smem-oom.html
>
> * igt@gem_softpin@allocator-evict@rcs0:
> - shard-iclb: NOTRUN -> [DMESG-WARN][34] ([i915#4391])
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@gem_softpin@allocator-evict@rcs0.html
>
> * igt@gem_userptr_blits@vma-merge:
> - shard-skl: NOTRUN -> [FAIL][35] ([i915#3318])
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl1/igt@gem_userptr_blits@vma-merge.html
>
> * igt@i915_pm_dc@dc6-dpms:
> - shard-kbl: NOTRUN -> [FAIL][36] ([i915#454])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@i915_pm_dc@dc6-dpms.html
>
> * igt@i915_pm_rpm@modeset-pc8-residency-stress:
> - shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271]) +102 similar issues
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl8/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
>
> * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
> - shard-skl: NOTRUN -> [FAIL][38] ([i915#3743])
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
>
> * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
> - shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3777]) +1 similar issue
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
>
> * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
> - shard-skl: NOTRUN -> [FAIL][40] ([i915#3763])
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
>
> * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
> - shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3777])
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
>
> * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
> - shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777])
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
>
> * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
> - shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886]) +8 similar issues
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
> - shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +5 similar issues
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
> - shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +4 similar issues
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
> - shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278] / [i915#3886])
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_chamelium@dp-hpd-storm-disable:
> - shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +6 similar issues
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_chamelium@dp-hpd-storm-disable.html
>
> * igt@kms_color@pipe-d-ctm-0-25:
> - shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278] / [i915#1149])
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_color@pipe-d-ctm-0-25.html
>
> * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
> - shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +12 similar issues
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
>
> * igt@kms_color_chamelium@pipe-b-ctm-max:
> - shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +10 similar issues
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl10/igt@kms_color_chamelium@pipe-b-ctm-max.html
>
> * igt@kms_content_protection@atomic-dpms:
> - shard-apl: NOTRUN -> [TIMEOUT][51] ([i915#1319])
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl8/igt@kms_content_protection@atomic-dpms.html
>
> * igt@kms_cursor_crc@pipe-d-cursor-512x170-random:
> - shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109279] / [i915#3359])
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x170-random.html
>
> * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
> - shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109278]) +1 similar issue
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
>
> * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
> - shard-tglb: NOTRUN -> [SKIP][54] ([fdo#109274] / [fdo#111825])
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-skl: [PASS][55] -> [FAIL][56] ([i915#2346] / [i915#533])
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-kbl: NOTRUN -> [INCOMPLETE][57] ([i915#180] / [i915#636])
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
> - shard-skl: [PASS][58] -> [FAIL][59] ([i915#79]) +1 similar issue
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> - shard-apl: [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +4 similar issues
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>
> * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
> - shard-skl: [PASS][62] -> [FAIL][63] ([i915#2122]) +1 similar issue
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
> - shard-glk: [PASS][64] -> [FAIL][65] ([i915#4911])
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
> - shard-iclb: [PASS][66] -> [SKIP][67] ([i915#3701]) +1 similar issue
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
>
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
> - shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271]) +163 similar issues
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
> - shard-tglb: NOTRUN -> [SKIP][69] ([fdo#109280] / [fdo#111825]) +1 similar issue
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
> - shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271]) +123 similar issues
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
> - shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109280]) +3 similar issues
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
>
> * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
> - shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533])
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
>
> * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> - shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>
> * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
> - shard-skl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +1 similar issue
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
>
> * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
> - shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658])
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
> - shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +1 similar issue
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
>
> * igt@kms_psr@psr2_sprite_blt:
> - shard-iclb: [PASS][78] -> [SKIP][79] ([fdo#109441])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
>
> * igt@kms_psr@psr2_sprite_render:
> - shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109441])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@kms_psr@psr2_sprite_render.html
>
> * igt@kms_vblank@pipe-d-wait-idle:
> - shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533]) +2 similar issues
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_vblank@pipe-d-wait-idle.html
>
> * igt@kms_writeback@writeback-invalid-parameters:
> - shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2437])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl3/igt@kms_writeback@writeback-invalid-parameters.html
> - shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2437])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl2/igt@kms_writeback@writeback-invalid-parameters.html
>
> * igt@kms_writeback@writeback-pixel-formats:
> - shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2437])
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl10/igt@kms_writeback@writeback-pixel-formats.html
>
> * igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
> - shard-iclb: NOTRUN -> [SKIP][85] ([i915#2530])
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb7/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html
>
> * igt@nouveau_crc@pipe-b-ctx-flip-detection:
> - shard-tglb: NOTRUN -> [SKIP][86] ([i915#2530])
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
>
> * igt@sysfs_clients@create:
> - shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994])
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl3/igt@sysfs_clients@create.html
>
> * igt@sysfs_clients@split-10:
> - shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2994])
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl4/igt@sysfs_clients@split-10.html
>
> * igt@sysfs_clients@split-50:
> - shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +1 similar issue
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@sysfs_clients@split-50.html
>
>
> #### Possible fixes ####
>
> * igt@feature_discovery@psr2:
> - shard-iclb: [SKIP][90] ([i915#658]) -> [PASS][91]
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb4/igt@feature_discovery@psr2.html
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@feature_discovery@psr2.html
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - shard-skl: [TIMEOUT][92] ([i915#3063]) -> [PASS][93]
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl4/igt@gem_eio@in-flight-contexts-10ms.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-skl4/igt@gem_eio@in-flight-contexts-10ms.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-iclb: [TIMEOUT][94] ([i915#2481] / [i915#3070]) -> [PASS][95]
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@gem_eio@unwedge-stress.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb8/igt@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_balancer@parallel-out-fence:
> - shard-iclb: [SKIP][96] ([i915#4525]) -> [PASS][97] +1 similar issue
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - shard-iclb: [FAIL][98] ([i915#2842]) -> [PASS][99] +1 similar issue
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
>
> * igt@gem_exec_fair@basic-none@rcs0:
> - shard-kbl: [FAIL][100] ([i915#2842]) -> [PASS][101]
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vecs0:
> - shard-apl: [FAIL][102] ([i915#2842]) -> [PASS][103]
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-tglb: [FAIL][104] ([i915#2842]) -> [PASS][105]
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_parallel@fds@bcs0:
> - {shard-rkl}: [INCOMPLETE][106] -> ([PASS][107], [PASS][108])
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@gem_exec_parallel@fds@bcs0.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-4/igt@gem_exec_parallel@fds@bcs0.html
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-2/igt@gem_exec_parallel@fds@bcs0.html
>
> * igt@gem_exec_suspend@basic@smem:
> - {shard-rkl}: [INCOMPLETE][109] -> [PASS][110] +2 similar issues
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@gem_exec_suspend@basic@smem.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@gem_exec_suspend@basic@smem.html
>
> * igt@gem_exec_whisper@basic-contexts-priority:
> - shard-glk: [DMESG-WARN][111] ([i915#118]) -> [PASS][112] +1 similar issue
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk8/igt@gem_exec_whisper@basic-contexts-priority.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority.html
>
> * igt@gem_ppgtt@blt-vs-render-ctxn:
> - {shard-tglu}: [INCOMPLETE][113] ([i915#750]) -> [PASS][114] +1 similar issue
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-7/igt@gem_ppgtt@blt-vs-render-ctxn.html
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-8/igt@gem_ppgtt@blt-vs-render-ctxn.html
>
> * igt@gem_workarounds@suspend-resume-context:
> - shard-apl: [DMESG-WARN][115] ([i915#180]) -> [PASS][116] +3 similar issues
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
>
> * igt@i915_pm_rc6_residency@rc6-fence:
> - {shard-tglu}: [WARN][117] ([i915#2681]) -> [PASS][118]
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-fence.html
>
> * igt@i915_pm_rpm@gem-mmap-type@uc:
> - {shard-rkl}: [SKIP][119] ([fdo#109308]) -> [PASS][120] +3 similar issues
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@i915_pm_rpm@gem-mmap-type@uc.html
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@i915_pm_rpm@gem-mmap-type@uc.html
>
> * igt@i915_selftest@live@gt_pm:
> - {shard-tglu}: [DMESG-FAIL][121] ([i915#3987]) -> [PASS][122]
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-8/igt@i915_selftest@live@gt_pm.html
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-tglu-7/igt@i915_selftest@live@gt_pm.html
>
> * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs:
> - {shard-rkl}: [SKIP][123] ([i915#1845] / [i915#4098]) -> [PASS][124]
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs.html
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
> - {shard-rkl}: ([PASS][125], [SKIP][126]) ([fdo#112022]) -> [PASS][127]
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-kbl: [DMESG-WARN][128] ([i915#180]) -> [PASS][129] +3 similar issues
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
> - shard-iclb: [FAIL][130] ([i915#2346]) -> [PASS][131] +1 similar issue
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
>
> * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
> - {shard-rkl}: [SKIP][132] ([fdo#111314]) -> [PASS][133]
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
> - shard-iclb: [SKIP][134] ([i915#3701]) -> [PASS][135] +1 similar issue
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
> - {shard-rkl}: [SKIP][136] ([i915#4098]) -> [PASS][137]
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
> - {shard-rkl}: [SKIP][138] ([i915#1849]) -> [PASS][139] +3 similar issues
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/shard-rkl-6/igt@kms_frontbuff
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21923/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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